103results about How to "Improve manufacturing yield" patented technology

The invention relates to an electron beam additive manufacturing method and system for a titanium-aluminum intermetallic compound, and the electron beam additive manufacturing method for the titanium-aluminum intermetallic compound is realized through the electron beam additive manufacturing system for the titanium-aluminum intermetallic compound. The invention relates to a method for carrying out layer-by-layer stacking forming according to a preset track, carrying out follow-up scanning heating by adopting at least two electron beams and homogenizing a temperature field of a formed part, in particular to a rapid additive manufacturing method for a high-temperature material which is difficult to weld and needs a small temperature gradient and low stress in the forming process. The method can solve the problems of high manufacturing difficulty, high manufacturing cost and the like of the current common processing technology of intermetallic compound parts such as titanium and aluminum.

The invention provides a back contact photovoltaic cell piece capable of preventing stacking scratch in a high-temperature passivation process. The back contact photovoltaic cell piece comprises a back contact photovoltaic cell piece body and a plurality of soft isolation protrusions located on the light receiving face of the back contact photovoltaic cell piece body. The soft isolation protrusions are used for supporting photovoltaic cells to be mutually isolated when the photovoltaic cells are stacked layer by layer, and the soft isolation protrusions are resistant to high temperature of 300 DEG C and do not become sticky or yellow within 3 hours. According to the invention, the soft isolation projections are arranged on the light receiving surface of the back contact photovoltaic cell sheet body to support mutual isolation of the photovoltaic cell sheets when the photovoltaic cell sheets are stacked layer by layer, so that the photovoltaic cell sheets can be protected from being scratched in the stacking and moving process; the flexible isolation protrusions are arranged on the back contact photovoltaic cell piece, the flexible isolation protrusions can be prevented from scratching the surface of the photovoltaic cell piece due to the specific flexibility of the flexible isolation protrusions, meanwhile, the flexible isolation protrusions can bear the passivation temperature of 300 DEG C or above and do not crack or yellow or adhere to the cell piece, and therefore it can be ensured that the back contact photovoltaic cell piece is subjected to high-temperature passivation in a multi-layer stacking mode, and the passivation efficiency is improved.

The invention discloses a light guide plate processing machine table and a light guide plate processing method. The light guide plate processing machine table comprises rollers, an upper clamping platform and a lower clamping platform. The roller has a plurality of teeth. The upper clamping platform is provided with a first rack side, the first rack side is provided with a plurality of first meshing grooves, and the first meshing grooves are meshed with gear teeth of the rolling wheels. The lower clamping platform is arranged on the opposite side of the upper clamping platform, the lower clamping platform and the upper clamping platform are in a clutch state, the lower clamping platform is provided with a second rack side, the second rack side is provided with a plurality of second meshing grooves, and the second meshing grooves correspond to the first meshing grooves and are meshed with the wheel teeth of the rolling wheel. According to the light guide plate processing machine table and the light guide plate processing method, the stress applied to the light guide plate sheet can be reduced, the situation of poor microstructure forming is greatly reduced, and the manufacturing yield of the light guide plate is increased.

The invention provides a chip test data analysis method. The chip test data analysis method comprises the following steps: 1, firstly, collecting test data by adopting a data collection module, and then dividing the data into single-table data and multi-table data through a single-table data processing module and a multi-table data processing module, in the process, the data processed by the single-table data processing module is judged through a judgment module; and 2, if the data is qualified, forming a data table and displaying the data table through a single table data display module, and if the data is unqualified, processing the data table through a failure data processing module. According to the chip test data analysis method provided by the invention, the test data of different test systems can be quickly and automatically arranged and analyzed through the method. And data arrangement can be completed conveniently and quickly in a time-saving and labor-saving Parameter differences of chips of different batches can be found through data arrangement and analysis and are fed back to a design end to effectively analyze a failure mode, design is improved, and the manufacturing yield is increased.

The invention discloses an iron-modified molybdenum disulfide-based piezoelectric catalytic material and a preparation method and application thereof.The preparation method comprises the following steps that ammonium molybdate and thiourea are mixed with water in proportion, and then a mixed solution is subjected to a hydrothermal reaction; drying the solution after the hydrothermal reaction to obtain molybdenum disulfide; molybdenum disulfide and a ferric iron salt solution are mixed and stirred, and then a reducing agent is added for reduction; and collecting and drying the reduced solution to obtain the iron-modified molybdenum disulfide-based piezoelectric catalytic material. A piezoelectric catalysis system of molybdenum disulfide can be more effectively utilized to generate hydrogen peroxide in situ, and Fenton-like reaction is carried out, so that pollutants are better removed.

A method of forming a semiconductor memory structure includes forming a bottom electrode layer over an active region, depositing a first high dielectric constant dielectric material over the bottom electrode layer, depositing a second high dielectric constant dielectric material over the first high dielectric constant dielectric material, and forming a second high dielectric constant dielectric material over the second high dielectric constant dielectric material. Performing an annealing process on the first high-dielectric-constant dielectric material and the second high-dielectric-constant dielectric material, and after the annealing process, depositing a third high-dielectric-constant dielectric material on the second high-dielectric-constant dielectric material; and forming a top electrode layer on the third high dielectric constant dielectric material.

Provided in the present application are a determination method and apparatus for a superconducting impedance transformation parametric amplifier, a superconducting impedance transformation parametric amplifier, an electronic device, a computer program product and a computer-readable storage medium. The method comprises: based on a wavelength parameter, a gain parameter and a bandwidth parameter, calculating an impedance value of an impedance transformation line of a superconducting impedance transformation parametric amplifier and a capacitance value of the amplifier; based on the impedance value of the impedance transformation line, calculating a linewidth dimension of a coplanar waveguide of the superconducting impedance transformation parametric amplifier; based on the impedance value of the impedance transformation line and the capacitance value of the amplifier, calculating a stub dimension of the superconducting impedance transformation parametric amplifier; and based on the linewidth dimension and the stub dimension, determining structural parameters of the superconducting impedance transformation parametric amplifier.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device and a manufacturing method thereof, the IGBT device comprises an N-type semiconductor layer and a plurality of grooves located in the N-type semiconductor layer, gate electrodes are arranged in the grooves, and the gate electrodes are insulated and isolated from the N-type semiconductor layer through gate dielectric layers; the P-type body region is located between the adjacent grooves, and an N-type emitter region is arranged in the P-type body region; the N-type carrier storage layer is positioned below the P-type body region and is positioned between the adjacent grooves; the bottom of each groove is provided with a P-type protection layer, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the groove. The IGBT device adopts the shallow trench, so that the on-state voltage drop can be reduced, and the process yield can be improved; the bottom of the groove is surrounded by the P-type protection layer, so that local charge balance can be formed, and voltage resistance is improved.

The invention provides a correction jig, a correction method, a rotating shaft cover plate and foldable electronic equipment. The correction jig is used for correcting the straightness of a long-strip-shaped part and is provided with a first groove, and the first groove extends in the first direction; in the second direction, the range of the difference value w1-w1'between the width w1 of the first groove and the width w1 'of the long-strip-shaped part is larger than or equal to 0.05 mm and smaller than or equal to 0.1 mm, and the first direction intersects with the second direction. The correction jig is simple in structure.

This invention discloses a method, system, storage medium, and electronic device for X-ray detector quality inspection. The method includes: acquiring an original brightness field image captured by an X-ray detector, and correcting the original brightness field image to obtain a corrected brightness field image; determining target parameters for the corrected brightness field image; if the target parameters exceed a corresponding threshold range, determining the corrected brightness field image as an abnormal image; otherwise, determining the corrected brightness field image as a normal image; if the corrected brightness field image is an abnormal image, determining the X-ray detector quality is abnormal; otherwise, determining the X-ray detector quality is normal. This invention monitors the production quality of X-ray detectors by detecting the quality of X-ray images captured by the X-ray detector, thereby helping to optimize the research and development of X-ray detectors and improve their manufacturing yield.

A display device is provided. The display device including a first pixel and a second pixel includes a light-emitting layer, a color conversion layer disposed on the light-emitting layer, and a color filter layer disposed on the color conversion layer, wherein the light-emitting layer includes a first light-emitting element disposed in the first pixel and a second light-emitting element disposed in the second pixel, wherein the color conversion layer includes a first color conversion layer disposed in the first pixel and a second color conversion layer disposed in the second pixel, the color filter layer includes a first color filter layer disposed in the first pixel and a second color filter layer disposed in the second pixel, the first light-emitting element and the second light-emitting element emit a first light, the center wavelength range of the first light is a first wavelength, the first color conversion layer and the second color conversion layer contain color conversion particles that convert the first light into a second light, the center wavelength range of the second light is a second wavelength longer than the first wavelength, the first color filter layer transmits the first light and blocks the transmission of the second light, and the second color filter layer transmits the second light and blocks the transmission of the first light.

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode and a covering layer. Wherein the channel layer is located on the substrate, the barrier layer is located on the channel layer, the source electrode, the gate electrode and the drain electrode are respectively located on the barrier layer, and the covering layer covers the source electrode and the drain electrode except above the source electrode and the drain electrode.

The invention discloses a trench isolation structure, a preparation method thereof and a semiconductor device, and the preparation method comprises the steps: providing a semiconductor substrate which comprises a trench; at least the interior of the groove is filled with a sacrificial layer, and the filled sacrificial layer exposes a part of height of the side wall of the groove in the depth direction from the port of the groove to the interior of the groove. A first oxidation film layer is at least formed on the side wall of the groove and above the sacrificial layer in the groove, a first part of the first oxidation film layer is formed on the side wall of the groove, and a gap is formed in the first part; the second portion is formed at the bottom of the gap and on the sacrificial layer. Forming a window on the second part, wherein the window exposes part of the sacrificial layer; and removing the sacrificial layer in the groove based on the window. And filling the gap in the first part with a second oxide film layer until the gap is completely filled with the second oxide film layer. Therefore, the preparation process of the trench isolation structure can be simplified, the preparation difficulty and cost can be reduced, and the performance of the semiconductor device can be improved.

This invention discloses a middle plate, an electrode chamber assembly, and an electrolytic hydrogen production device. The middle plate includes a body and a circulation plate. The body is integrally stamped from a metal plate. An S-shaped annular sealing channel is stamped around the perimeter of the body surface. Several first protrusions and second protrusions are stamped on two surfaces of the body inside the annular sealing channel. The circulation plate is inclined and fixedly connected to the first protrusions. The circulation plate is disposed within the annular sealing channel, and the distance between its top edge and the body surface is less than the distance between its bottom edge and the body surface. The electrode chamber assembly is assembled using the aforementioned middle plate, and the electrolytic hydrogen production device utilizes the aforementioned electrode chamber assembly. This invention provides excellent sealing performance. The stamped structure integrating the anode and cathode chambers and the middle plate effectively reduces leakage points and lowers the risk of external leakage. Furthermore, it reduces spot welding processes, lowers internal contact resistance, and thus reduces the energy consumption of the electrolyzer. The above structure is rationally configured and easy to install.

The utility model discloses a semiconductor equipment sampling device, which relates to the technical field of semiconductor processing, and comprises a driving mechanism, a buffer mechanism and at least two suction heads, the buffer mechanism comprises at least two elastic expansion pieces; the elastic expansion pieces are connected with the suction heads in a one-to-one correspondence manner, so that the suction heads can elastically move; the driving mechanism is connected with the elastic expansion pieces and used for driving the elastic expansion pieces to move close to each other or away from each other. According to the design, by optimizing the buffering effect and the adsorption stability, the sample rejection rate is reduced, and the semiconductor manufacturing yield is increased; and the continuity and the efficiency of the production process can be improved by adopting the universal design and reducing the remodeling operation.

The utility model relates to semiconductor ion implantation equipment technical field, and disclose a kind of multi-functional high-efficiency boron fluoride ion implantation chamber, including support connecting mechanism, sealing assembly, support connecting mechanism contains chamber main body, internal injection component, multifunctional component assembly interface, upper sealing ring assembly groove, side sealing ring assembly groove, top connecting hole, top auxiliary sealing ring assembly groove, side fixed base, assembly interface sealing ring assembly groove, through slot, toughened glass sheet.The utility model is through the curved surface gradual change flow guide structure of internal injection component, boron fluoride ion distribution in chamber is accurately controlled, ion distribution uniformity is significantly improved, guarantee semiconductor material doping consistency, effectively improve device manufacturing yield, adapt high-precision semiconductor process demand.

This invention relates to the field of wearable electronic device technology, specifically disclosing a partitioned, double-sided, skin-contact, sweat-wicking hybrid energy harvesting armband and its manufacturing method. The armband includes a flexible strip substrate, an organic photovoltaic (PV) power generation unit, a polymer thermoelectric power generation unit, a skin-contact thermal interface layer, a cold-end heat dissipation structure, and a circuit integration module. The PV power generation unit and the polymer thermoelectric power generation unit are partitioned and mounted on the same flexible strip substrate. Microstructured channels are pre-set within the skin-contact thermal interface layer to guide sweat and reduce contact thermal resistance. A process route is adopted where the organic PV is first fabricated and encapsulated with high barrier properties, followed by the printing of the polymer thermoelectric power generation unit. A porous fabric or fin array heat dissipation structure is integrated at the cold end of the polymer thermoelectric power generation unit. This invention can improve photoelectric conversion efficiency, stabilize operating temperature difference, reduce contact thermal resistance, increase manufacturing yield, enhance output power, and improve wearing comfort.

A vertical cavity surface emitting laser diode includes a substrate and an epitaxial stack on the substrate, the epitaxial stack including an active region, a current confinement layer, and a mode filter layer, wherein the mode filter layer has an optical aperture, the mode filter layer is oxidizable, and the mode filter layer is oxidized to form the optical aperture.

The invention relates to a preparation method of a composite substrate and the composite substrate, and the method comprises the steps: providing a wafer bonding structure to be processed, the wafer bonding structure comprises a supporting substrate, a device substrate, and an insulating layer located between the supporting substrate and the device substrate, and the first surface side of the supporting substrate is provided with a cavity structure, the first surface is arranged towards the second surface of the device substrate; the device substrate is thinned to a preset thickness from the third surface of the device substrate, and the preset thickness is smaller than or equal to 10 micrometers; the thinning step comprises the substeps of thinning the device substrate by adopting a mechanical grinding process, wherein the mechanical grinding process comprises the substeps of thinning the device substrate by adopting a coarse grinding process until the thickness is greater than or equal to 120 microns; thinning the device substrate until the thickness is greater than or equal to 60 microns by adopting an accurate grinding process; thinning the device substrate to a third preset thickness by adopting a wet etching process; and reducing the thickness of the device substrate to a preset thickness by adopting a chemical mechanical grinding process. In this way, the device substrate can be thinned to be below 10 microns and is not damaged.

This invention discloses a warm isostatic pressing (WIP) densification process for solid-state batteries. This invention relates to the field of solid-state battery manufacturing technology and aims to solve the problem of uneven stress and cracking of thin electrolyte membranes caused by existing isostatic pressing processes. The method involves aligning and bonding the negative electrode sheet with a solid electrolyte membrane containing a substrate, followed by cold isostatic pressing pre-pressing. The substrate is then removed, and the positive electrode sheet is bonded to complete cell assembly. The cell is placed in a perforated fixture and a flexible sheath, vacuum-sealed, and then sent into the warm isostatic pressing chamber. A pressure-transmitting medium is injected, and the temperature is programmed to reach the target process temperature, followed by pressurization to the target process pressure. Based on the material system of the solid electrolyte membrane, pressure and temperature are maintained at the corresponding temperature and pressure. Controllable pressure release is performed at a rate slower than the pressurization rate, while simultaneously cooling to below the set temperature. This method improves the manufacturing yield, interface densification, and consistency of the cell through step-by-step pre-pressing and programmed temperature and pressure control.

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of word lines, a dielectric layer, and a plurality of bit lines. The substrate comprises active structures and shallow trench isolations. The word lines are embedded in the substrate and staggered with the active structures and the shallow trench isolations, respectively. The dielectric layer is arranged on the substrate and covers the top surfaces of the word lines. The bit lines extend on the substrate in a first direction. The bit lines comprise at least one first bit line which simultaneously overlaps the active structures and the shallow trench isolations and has a bottom surface physically contacting only the dielectric layer, and a plurality of second bit lines which are arranged below a plurality of bit line plugs penetrating through the dielectric layer and directly contacting the active structures. The first bit line is arranged as a dummy bit line to maintain the same overall light flux when the photolithography manufacturing process is performed, and to improve the manufacturing yield of the semiconductor device.

The invention relates to a process method for improving channel mobility and gate dielectric layer reliability of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The process method comprises the following steps of: forming a channel layer on an epitaxial layer by adopting ion implantation; carrying out surface treatment on the SiC epitaxial layer in a sacrificial oxidation mode; forming SiO2 on the surface of SiC by adopting a low-pressure chemical vapor deposition process to serve as a gate dielectric layer; and performing an NO post-deposition annealing process on the gate dielectric layer. The SiC / SiO2 interface roughness formed by the method is reduced, the problem that carbon clusters and carbon particles are generated in traditional thermal oxidation is avoided, and the interface state density is reduced, so that the channel carrier mobility is enhanced; besides, a step-by-step low-pressure chemical vapor deposition process is adopted, gate dielectric layer densification is carried out in a gap between two or more stages of deposition processes, residues of a precursor in deposition are fully decomposed, stress of the gate dielectric layer is released, the electric leakage level of the gate dielectric layer is reduced, the reliability of the gate dielectric layer is enhanced, and the device yield is improved.

The invention discloses an organic compound taking adamantane as a core and an organic electroluminescent device containing the organic compound. The organic compound with adamantane as the core has a low visible light refractive index in the visible light field, is matched with a high-refractive-index material to form a low-high double-layer light extraction layer, and can effectively improve the light extraction efficiency of the organic electroluminescent device and greatly reduce the angle dependence after being applied to the organic electroluminescent device. Therefore, the luminous efficiency of the device is improved and the visual bias performance is optimized.

The invention provides a packaging structure and a manufacturing method thereof, and the packaging structure comprises a packaging body which comprises an accommodation cavity with an upward opening; the chip is positioned in the accommodating cavity; the surface of the chip is provided with a photosensitive area; the light-transmitting cover plate is positioned above the chip; a first groove is formed by the space between the light-transmitting cover plate and the inner wall of the containing cavity. The first groove is used for accommodating a colloid for bonding the light-transmitting cover plate and the packaging body; the blocking structure is located between the chip and the light-transmitting cover plate and located on the outer side of the light sensing area; the top of the blocking structure is in contact with the light-transmitting cover plate; the blocking structure is used for blocking colloid from entering the photosensitive area.

The invention provides a power semiconductor module which is not provided with a base plate serving as a supporting part of an insulating substrate and a heat radiator, and can effectively inhibit the crack of the insulating substrate, which is easily generated when the sealing resin is cooled and solidified, in the resin sealing type power semiconductor module. In a resin-sealed power semiconductor module having no support member for an insulating substrate, the resin-sealed power semiconductor module is characterized by being provided with: an insulating substrate; a first conductor layer pattern disposed on the insulating substrate; a second conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern; a third conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern and the second conductor layer pattern; a first semiconductor chip group having one or more semiconductor chips bonded to the first conductor layer pattern; a second semiconductor chip group having one or more semiconductor chips bonded to the second conductor layer pattern; a first lead frame that electrically connects the second conductor layer pattern and the side of the first semiconductor chip group opposite to the joining surface of the first conductor layer pattern; and a second lead frame that electrically connects the third conductor layer pattern and the side of the second semiconductor chip group that is opposite the joining surface with the second conductor layer pattern, the first lead frame and the second lead frame being disposed so as to respectively span a slit between the first conductor layer pattern and the second conductor layer pattern. The lead frame is disposed so as to be one layer in a direction perpendicular to the surface on which the conductor layer patterns of the insulating substrate are disposed.

The present invention discloses a semiconductor test structure and a manufacturing method thereof, belonging to the field of semiconductor technology, wherein the test structure at least comprises: a substrate, comprising a plurality of active regions arranged in parallel; a plurality of gates, arranged in parallel on the plurality of active regions, a gate dielectric layer arranged between the gates and the active regions, the gates and the active regions being perpendicular; a first metal silicide, arranged at least on a portion of the gates and the sidewalls on one side of the gates, and extending to the active regions; at least one test hole group is arranged on a single active region between adjacent gates, the test hole group and the first metal silicide are staggered; a connecting hole is arranged on the active regions on one side of the plurality of gates; at least one first test point is arranged on the test hole group and connected to the test hole group; a second test point is arranged on the connecting hole and connected to the connecting hole. Through the semiconductor test structure and the manufacturing method thereof provided by the present invention, the manufacturing quality of the metal silicide can be fed back in time, and the monitoring efficiency can be improved.

The application provides a braiding device and a braiding method for manufacturing a double-head closed-loop dense net support. The braiding device comprises a rotating disc, a spindle assembly with a plurality of spindles, the spindle assembly being mounted on the rotating disc, the plurality of spindles being arranged in sequence along the circumference of the rotating disc, every two spindles being symmetrical about the center of the rotating disc, and any two symmetrical spindles being used for sleeving a braiding ring so that the centers of all the braiding rings intersect at the center of the rotating disc; and a braiding core rod coaxially arranged with the rotating disc, the braiding core rod being movable in the axial direction of the rotating disc, the braiding core rod penetrating the center intersection area of the braiding ring and making the center intersection area located at a braiding starting point of the braiding core rod, and the braiding core rod tensioning all the braiding rings at the braiding starting point. The braiding device can braiding the double-head closed-loop dense net support on the braiding core rod at one time through the movement of all the spindles along the circumference of the rotating disc and the movement of the braiding core rod along the axial direction of the rotating disc, thereby effectively reducing the manufacturing difficulty of the double-head closed-loop dense net support and improving the manufacturing yield.

The embodiment of the invention provides a display panel and a display device.The display panel comprises a substrate, a crack detection line, a crack detection transistor and a touch electrode layer, the crack detection line and the crack detection transistor are both located in a non-display area, and the touch electrode layer is located on the side, away from the substrate, of a film layer where a crack detection signal line is located; the crack detection transistor is arranged on one side, far away from the substrate, of the film layer; wherein the touch electrode layer comprises a first line changing part located in the non-display area, and the crack detection line is electrically connected with the crack detection transistor through the first line changing part. According to the display panel, the electrostatic charges transmitted to the crack detection transistor by the crack detection line are reduced, the probability that the crack detection transistor is damaged by static electricity is reduced, and the preparation yield of the display panel is improved.

The invention relates to a conductive agent and a preparation method thereof, a pole piece, a secondary battery and an electric device. The conductive agent comprises a nitrogen-doped porous carbon nanosheet with a lamellar structure. According to the conductive agent provided by the invention, the nitrogen-doped porous carbon nanosheet with the lamellar structure is adopted as the conductive agent, on one hand, the lamellar structure forms a large-area conductive network, so that electrons can be conducted in a two-dimensional space, and meanwhile, nitrogen is doped in the carbon nanosheet to introduce additional conductive contact sites; the porous structure effectively increases the specific surface area, so that the conductivity of the conductive agent is improved. And on the other hand, the material cost of the conductive agent is reduced, and through the synergistic effect of nitrogen doping and the porous structure, the dispersity of the conductive agent in the slurry is improved, the agglomeration phenomenon is reduced, the preparation yield of the pole piece is improved, and large-scale industrial application is further facilitated.

The present application relates to the technical fields of intelligent manufacturing and automation control, and discloses a kind of intelligent regulation and control methods for the wall thickness of crucible spin pressing in piezoelectric single crystal growth, comprising: collecting data in the process of spin pressing, and obtaining stable acquisition sequence by preprocessing;Stable acquisition sequence is fused by adaptive weighted fusion and Kalman filtering, and the fused wall thickness is obtained by fusing the laser thickness value and the wall thickness value and compensation value respectively mapped by the spin pressing force, torque and eccentricity;Calculate the comprehensive deviation vector of wall thickness deviation, local wall thickness thinning rate, eccentricity deviation and roundness error;Based on the comprehensive deviation vector and the wall thickness deviation, the fuzzy adaptive PID output correction value and the hierarchical threshold comparison are executed in parallel to generate pass jump and trajectory reconstruction instructions, and the closed-loop cooperative control is formed by issuing the numerical control spin pressing system;After each pass is completed, the wall thickness distribution is obtained by fusion and solution, and the deviation is determined to add compensation pass or trajectory reconstruction, and iteration is carried out until the requirements are met.The present application realizes the online intelligent closed-loop regulation and control of the wall thickness of crucible spin pressing.