41 results about "Integrated circuit interconnect" patented technology

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and / or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

The present application discloses a Gaussian surface establishment method for integrated circuit interconnect capacitance extraction, comprising: obtaining the interconnect capacitance extraction result based on the grid division of the three-dimensional simulation area in the Gaussian surface in the main line network and the spatial data information of the conductor block information contained therein, controlling each conductor block in the main line network to expand outward to obtain the corresponding query cuboid, obtaining the conductor blocks contained in all spatial grids intersecting with each query cuboid to obtain a candidate conductor list, if the candidate conductor list is empty, then controlling the corresponding conductor block to expand outward with half of the minimum distance from the conductor block corresponding to the query cuboid to the outer boundary of the above-mentioned intersecting spatial grid to obtain the corresponding Gaussian surface, otherwise, controlling the corresponding conductor block to expand outward with half of the minimum distance from the conductor block corresponding to the query cuboid to the conductor block in the candidate conductor list to obtain the corresponding Gaussian surface. In this way, efficient processing of establishing Gaussian surfaces for conductor blocks in the main line network is achieved.

This invention discloses a method for evaluating the performance impact of porosity in integrated circuit interconnect dielectric materials, comprising the following steps: S1: Testing the porosity, pore size, and pore distribution of the dielectric material in subsequent processes; S2: Establishing a molecular model of the dielectric material at the microscale and calculating the electrical, structural, mechanical, and thermal parameters related to porosity; S3: Performing finite element simulation calculations with coupled electro-thermal-solid multiphysics fields at the macroscale to simulate the electric field, temperature field, stress and deformation field, and the formation and evolution of macroscopic pores during the interconnect process in subsequent processes; S4: Analyzing the impact of porosity on electrical, structural, thermal, and mechanical properties and the manufacturing process based on the multi-scale simulation results. This invention establishes a quantitative relationship between dielectric material, porosity, process, and performance through multi-scale multiphysics field coupled simulation to evaluate the performance impact of porosity in integrated circuit interconnect dielectric materials and guide the design of dielectric materials and structures.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die transmits a test pattern to the second circuit die via the interconnect layer. Then, the second circuit die determines that a first interconnect has failed based on the test pattern and generates a signature. Finally, the second circuit die uses signatures to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

An optoelectronic component may include a substrate, an electronic integrated circuit supported by the substrate, and a photonic integrated circuit supported by the substrate. The optoelectronic component may include a plurality of substrate interconnect connectors disposed on the substrate, a plurality of electronic integrated circuit interconnect connectors disposed on the electronic integrated circuit, and a plurality of photonic integrated circuit interconnect connectors disposed on the photonic integrated circuit. The optoelectronic component may include a first plurality of cable connectors, each cable connector connected to the substrate, the electronic integrated circuit, and the photonic integrated circuit via respective interconnect connectors. The first plurality of cable connectors may be configured to facilitate electrical communication between the substrate, the electronic integrated circuit, and the photonic integrated circuit. The first plurality of cable connectors may define a first layout, and an overall connectivity of the optoelectronic component may correspond to the first layout.

The embodiment of the invention provides a brightness control method, electronic equipment, a storage medium and a program product, relates to the technical field of display, and can realize brightness adjustment without depending on a display drive. The brightness control method comprises the following steps: acquiring an APL (Average Picture Language) of a picture to be displayed; if the APL is smaller than a preset value, a first instruction is sent to an embedded controller EC, and the first instruction is used for controlling the embedded controller EC to write the first brightness into a display port configuration data DPCD register through an integrated circuit interconnection I2C bus; if the APL is not smaller than the preset value, a second instruction is sent, the second instruction is used for writing second brightness into a display port configuration data DPCD register, and the second brightness is smaller than the first brightness.

A semiconductor structure and a method for fabricating this structure are disclosed. The semiconductor structure comprises a substrate, a fixture layer arranged on the substrate, a current conductor arranged on the fixture layer, a first capacitor circuit, a second capacitor circuit, and a control circuit arranged on the current conductor and configured to control the first capacitor circuit. The first capacitor circuit comprises a first conductive via arranged on the current conductor, a first conductor track arranged on the first conductive via and aligned with a first side of the current conductor, and a first trench capacitor arranged on the first conductor track.The second capacitor circuit features a second conductive via arranged on the power line, a second conductor track arranged on the second conductive via and aligned to a second side of the power line, and a second trench capacitor arranged on the second conductor track.

The present invention discloses a method for determining the transient temperature of interconnection based on a tensor analysis network, which mainly solves the problem of low efficiency of the prior art interconnection electrothermal transient temperature simulation. The implementation scheme is: constructing an equivalent thermal circuit of a single-layer interconnection structure; cascading the equivalent thermal circuits of a single-layer interconnection structure to form a thermal circuit model of a multi-layer interconnection structure; splitting the thermal circuit model of the multi-layer interconnection structure to obtain different thermal circuit units; cascading the impedance matrix of the thermal circuit units to obtain the impedance matrix of the multi-layer interconnection equivalent thermal circuit; porting the impedance matrix of the thermal circuit; porting the preprocessed impedance matrix; multiplying the ported impedance matrix with the excitation to obtain the temperature response in the frequency domain; performing a Laplace numerical inverse transform on the frequency domain temperature response to obtain the final determined temperature that changes with time. Compared with the prior art, the present invention saves 99% of the operation time at the same accuracy, improves the efficiency of transient temperature solution, and can be used for integrated circuit interconnection and package interconnection.

The invention discloses an integrated circuit interconnection line stray capacitance extraction method based on a random matrix, and belongs to the technical field of integrated circuits, and the method comprises the steps: constructing a conductor system geometric model; constructing an internal and external sampling point sequence; constructing a random matrix to compress a matrix to be solved; constructing final to-be-solved left and right end matrixes in batches; solving a compressed matrix equation; a result obtained by solving is brought back to the previous matrix construction step to construct a new matrix to be solved; repeatedly executing the step of constructing and solving until the obtained solution meets a convergence condition; and generating a final capacitance matrix. According to the method, the coupling parasitic capacitance of the interconnection line can be efficiently and accurately extracted.

In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistive element (MRE) disposed above the first conductive layer and coupled to the first conductive layer through a first via. The MRE is magnetized to produce a first magnetic orientation. The first conductive layer is disposed above a second conductive layer in the circuit and coupled to the second conductive layer through a second via. The circuit also includes a metal fill disposed in a vicinity of the MRE. The metal fill is positioned above the second conductive layer and coupled to the second conductive layer through a third via. The circuit also includes a heat dissipation path resulting from a physical input applied to the first MRE. The heat dissipation path extends through the first via to the third via, the first conductive layer and the second conductive layer, an integrated circuit interconnect, and the metal fill.

In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

Systems, devices, and methods for optimization of conducting interconnects are described. A method includes receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect. The method includes generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information. The method includes determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information. The method also includes generating an updated integrated circuit layout based at least in part on the individual contribution.

An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

The invention discloses a graphene interconnection atomic layer deposition method based on a self-assembled monomolecular layer, which comprises the following steps: carrying out surface hydroxylation treatment on a substrate, preparing the self-assembled monomolecular layer on the surface of the substrate, then taking the substrate coated with the self-assembled monomolecular layer as an electrophoresis anode, carrying out electrophoretic deposition on the substrate and graphene oxide colloid, and carrying out annealing reduction to obtain the graphene interconnection atomic layer. The graphene film with the atomic-scale thickness is obtained. According to the method disclosed by the invention, the graphene with the atomic-scale thickness can form a film on the substrate in situ, and the graphene is prepared through the self-limiting reaction, so that the quality of the obtained graphene is not influenced by the shape, the size and other properties of the substrate, and therefore, the preparation method can be used for obtaining the large-area, low-roughness and high-quality graphene; the method is suitable for a graphene interconnection line or a graphene diffusion barrier layer in the field of integrated circuit interconnection.

The invention relates to an interconnect structure of an integrated circuit. A method of manufacturing an interconnect structure of an integrated circuit, which interconnect structure is intended to be encapsulated in an encapsulation resin in contact with a first surface of a protective layer. The protective layer is located on a first surface of the interconnect structure. The interconnect structure comprises a copper interconnect element, which extends at least partially through an insulating layer and is flush with the first surface of the interconnect structure. The manufacturing method comprises a structuring step of the protective layer or a step of forming the protective layer by structuring. The structuring step or the forming step is adapted to structure the first surface of the protective layer in the form of ridges and grooves alternating with each other.

The application discloses a kind of integrated circuit interconnection line parasitic capacitance extraction methods based on random matrix, belong to integrated circuit technical field, comprising: constructing conductor system geometric model;Constructing inside and outside sampling point sequence;Random matrix is constructed to the matrix to be solved urgently compressed;Batch construction final left and right end matrix to be solved;Solving compressed matrix equation;The result obtained by solving is fed back into the previous matrix construction step to construct new to-be-solved matrix;Repeatedly execute construction solving step until the solution obtained meets the convergence condition;Generate final capacitance matrix.The application can realize the efficient and accurate extraction of interconnection line coupling parasitic capacitance.

The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

Integrated circuit interconnect structures including an interconnect metallization feature comprising a sidewall reacted with a chalcogen into a low resistance liner. A portion of a backbone material or a metal seed layer may be advantageously converted into a metal chalcogenide, which can lower scattering resistance of an interconnect feature relative to alternative diffusion barrier materials, such a tantalum. Scattering resistance of such metal chalcogenide liner materials may be further reduced by actively cooling an IC, for example to cryogenic temperatures.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5 D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die emits a test pattern to the second circuit die via the interconnect layer. The second circuit die then determines, based on the test pattern, that a first interconnect has failed and generates a signature. Finally, the second circuit die uses a signature to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance / capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

An integrated cell and circuit interconnection for photovoltaic devices is disclosed. Interconnection componentry includes conductive material utilized to connect a negative terminal of a photovoltaic cell of a substring of a photovoltaic device to a positive terminal of a photovoltaic cell of another substring of the photovoltaic device to electrically connect the cells together. Certain interconnection componentry include extension portions that extend beyond the edge of the photovoltaic cells to which the interconnection componentry are connected. The extension portions are configured to connect to an electrical circuit of the photovoltaic device and connect the substrings to which the extension portions are attached to other substrings of the photovoltaic device. The interconnection componentry and extension portions facilitate bypass diode integration into the electrical circuit, while optimizing shade tolerance of the photovoltaic device and increasing roof fill with regard to a roof on which the photovoltaic device is secured.

This invention relates to the field of microelectronics and integrated circuit materials technology, specifically a method for rapidly preparing Mo-C-based interconnect thin film materials at room temperature. Addressing the problems of decreased conductivity and insufficient thermal stability caused by natural oxidation in traditional copper-based interconnect materials at technology nodes of 7 nm and below, this invention proposes molybdenum-based interconnect materials as an alternative. This invention achieves controllable and rapid preparation of high-quality molybdenum-carbon compound thin films on silicon substrates using magnetron sputtering technology. The key is the precise control of parameters such as sputtering power, carbon content, and working gas pressure, successfully preparing high-quality films with different phase structures (including MoC, Mo3C2, and Mo2C). Experimental results show that the optimized 60 nm thick Mo2C film can achieve a resistivity as low as 5.53 μΩ·cm at room temperature and maintains excellent electrical properties after high-temperature annealing at 400–600℃. This provides a key material solution for next-generation integrated circuit interconnect layers and has significant application prospects.

Systems, apparatus, and methods for optimizing conductive interconnects are described. One method includes receiving an integrated circuit layout comprising a plurality of terminals and interconnects, wherein the interconnects represent conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material properties of the plurality of terminals and interconnects. The method includes generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and layer information. The method includes using the three-dimensional representation and terminal information to determine the individual contribution of each individual component included in the three-dimensional representation to the resistance-capacitance (RC) value of the interconnects. The method also includes generating an updated integrated circuit layout based at least in part on the individual contributions.

Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.

To disclose systems, devices, and methods for optimization of conducting interconnects.SOLUTION: A method includes steps of: receiving an integrated circuit layout including a plurality of terminals and an interconnect, the interconnect representing a conductive coupling between the plurality of terminals; receiving terminal information describing operating parameters of the plurality of terminals; receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect; generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information; determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information; and generating an updated integrated circuit layout based at least in part on the individual contribution.SELECTED DRAWING: Figure 2

The invention discloses a novel integrated circuit interconnection packaging method, and belongs to the technical field of integrated circuits. According to the invention, the traditional method of realizing up-down interconnection through copper electroplating and the conventional lead bonding method are abandoned, the low-profile lead bonding routing technology is adopted, the copper wire is acted by virtue of a magnetic field in the packaging process, and meanwhile, the heating operation is carried out, so that the copper wire is softened to a free deformation state. And then cooling and carrying out plastic package molding treatment, removing the epoxy resin wrapping the copper wire through a grinding process to expose the copper wire, and finally successfully realizing stable and reliable electrical interconnection between the upper layer and the lower layer. According to the invention, the copper wire can be stretched and positioned to an ideal height, the packaging design requirement is perfectly met, the aspect ratio is greatly improved, the limitation of 1: 2 of electroplating copper and 1: 7 of traditional lead bonding is broken through, nearly unlimited proportion optimization is realized, the interconnection performance of an integrated circuit is comprehensively improved, and the production cost is reduced. And powerful technical support is provided for packaging and manufacturing of high-performance electronic products.

Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

The present invention belongs to the technical field related to integrated circuits, and particularly relates to a method for extracting parasitic capacitance of integrated circuit interconnections, including: constructing a set of sampling points on and inside the conductor surface; constructing a parasitic capacitance matrix with an initial value of zero for each pairwise interconnected capacitance; generating a set of ideal surface potential values corresponding to the surface sampling points of each conductor; constructing a neural network structure composed of an input layer, a single hidden layer, and an output layer, using the surface sampling points as the input, using the mean square error between the ideal surface potential value corresponding to the surface sampling points and the output of the neural network as the loss function, using the Green's function of the Poisson equation as the activation function of the hidden layer, and using all the equivalent point charge positions as the center coordinates of the activation function of the hidden layer; training the weight coefficients of each neuron in the hidden layer, corresponding to the equivalent charge values of each equivalent point charge, obtaining the equivalent charge values of all equivalent point charges of each conductor, and updating the parasitic capacitance matrix. The present invention can achieve the extraction of parasitic capacitance.

Systems, devices, and methods for optimization of conducting interconnects are described. A method includes receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect. The method includes generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information. The method includes determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information. The method also includes generating an updated integrated circuit layout based at least in part on the individual contribution.