23 results about "Integrated circuit interconnect" patented technology

This invention discloses a method for evaluating the performance impact of porosity in integrated circuit interconnect dielectric materials, comprising the following steps: S1: Testing the porosity, pore size, and pore distribution of the dielectric material in subsequent processes; S2: Establishing a molecular model of the dielectric material at the microscale and calculating the electrical, structural, mechanical, and thermal parameters related to porosity; S3: Performing finite element simulation calculations with coupled electro-thermal-solid multiphysics fields at the macroscale to simulate the electric field, temperature field, stress and deformation field, and the formation and evolution of macroscopic pores during the interconnect process in subsequent processes; S4: Analyzing the impact of porosity on electrical, structural, thermal, and mechanical properties and the manufacturing process based on the multi-scale simulation results. This invention establishes a quantitative relationship between dielectric material, porosity, process, and performance through multi-scale multiphysics field coupled simulation to evaluate the performance impact of porosity in integrated circuit interconnect dielectric materials and guide the design of dielectric materials and structures.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die transmits a test pattern to the second circuit die via the interconnect layer. Then, the second circuit die determines that a first interconnect has failed based on the test pattern and generates a signature. Finally, the second circuit die uses signatures to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

Systems, devices, and methods for optimization of conducting interconnects are described. A method includes receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect. The method includes generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information. The method includes determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information. The method also includes generating an updated integrated circuit layout based at least in part on the individual contribution.

The invention relates to an interconnect structure of an integrated circuit. A method of manufacturing an interconnect structure of an integrated circuit, which interconnect structure is intended to be encapsulated in an encapsulation resin in contact with a first surface of a protective layer. The protective layer is located on a first surface of the interconnect structure. The interconnect structure comprises a copper interconnect element, which extends at least partially through an insulating layer and is flush with the first surface of the interconnect structure. The manufacturing method comprises a structuring step of the protective layer or a step of forming the protective layer by structuring. The structuring step or the forming step is adapted to structure the first surface of the protective layer in the form of ridges and grooves alternating with each other.

The application discloses a kind of integrated circuit interconnection line parasitic capacitance extraction methods based on random matrix, belong to integrated circuit technical field, comprising: constructing conductor system geometric model;Constructing inside and outside sampling point sequence;Random matrix is constructed to the matrix to be solved urgently compressed;Batch construction final left and right end matrix to be solved;Solving compressed matrix equation;The result obtained by solving is fed back into the previous matrix construction step to construct new to-be-solved matrix;Repeatedly execute construction solving step until the solution obtained meets the convergence condition;Generate final capacitance matrix.The application can realize the efficient and accurate extraction of interconnection line coupling parasitic capacitance.

The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5 D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die emits a test pattern to the second circuit die via the interconnect layer. The second circuit die then determines, based on the test pattern, that a first interconnect has failed and generates a signature. Finally, the second circuit die uses a signature to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

This invention relates to the field of microelectronics and integrated circuit materials technology, specifically a method for rapidly preparing Mo-C-based interconnect thin film materials at room temperature. Addressing the problems of decreased conductivity and insufficient thermal stability caused by natural oxidation in traditional copper-based interconnect materials at technology nodes of 7 nm and below, this invention proposes molybdenum-based interconnect materials as an alternative. This invention achieves controllable and rapid preparation of high-quality molybdenum-carbon compound thin films on silicon substrates using magnetron sputtering technology. The key is the precise control of parameters such as sputtering power, carbon content, and working gas pressure, successfully preparing high-quality films with different phase structures (including MoC, Mo3C2, and Mo2C). Experimental results show that the optimized 60 nm thick Mo2C film can achieve a resistivity as low as 5.53 μΩ·cm at room temperature and maintains excellent electrical properties after high-temperature annealing at 400–600℃. This provides a key material solution for next-generation integrated circuit interconnect layers and has significant application prospects.

Systems, apparatus, and methods for optimizing conductive interconnects are described. One method includes receiving an integrated circuit layout comprising a plurality of terminals and interconnects, wherein the interconnects represent conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material properties of the plurality of terminals and interconnects. The method includes generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and layer information. The method includes using the three-dimensional representation and terminal information to determine the individual contribution of each individual component included in the three-dimensional representation to the resistance-capacitance (RC) value of the interconnects. The method also includes generating an updated integrated circuit layout based at least in part on the individual contributions.

Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.

Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Systems, devices, and methods for optimization of conducting interconnects are described. A method includes receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect. The method includes generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information. The method includes determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information. The method also includes generating an updated integrated circuit layout based at least in part on the individual contribution.

The integrated circuit includes a combination circuit (CMB) configured to generate a secret data string (SCRT) combining a first digital piece of information (NVM_entrpy_src) and a second digital piece of information (NVM_ant), all within the same memory plane (MEM_ARR): At least one first entropy cell (CEL1) is configured to provide the first digital piece of information (NVM_entrpy_src) determined by a non-clonable physical function of the first memory cell. At least one second memory cell (CEL2) is configured to provide the second digital piece of information (NVM_ant) determined by a charge contained non-volatilely in a floating gate (FG_ANT) of a state transistor, the floating gate (FG_ANT) of the state transistor being further connected to at least one metal trace (ANT) of an interconnect portion of the integrated circuit. Figure for the abstract: Fig 4

This disclosure provides a shared memory interconnect device, arbitration method, and arbitration circuit, relating to the field of integrated circuit interconnect technology. The implementation scheme is as follows: a hierarchical interconnect network includes an outer routing network and an inner switching network. The outer routing network includes a multi-level switching network composed of multiple butterfly switching units, used to route data stream packets from input ports to multiple subgroups of the inner switching network. The inner switching network includes multiple crossbar switching modules for performing local non-blocking switching. An arbitration module maintains the weights of each input port and determines the arbitration result based on the weights between conflicting ports. When arbitration fails, the weight of the corresponding port is incremented by a preset increment. When arbitration succeeds, the weight of the corresponding port is restored to its initial value. The arbitration result of each port is determined by cascading the arbitration status between conflicting ports, which can significantly reduce hardware area overhead while ensuring local bandwidth and low latency.

The application belongs to the technical field of hybrid integrated circuit electronic surface mounting, and particularly relates to a hybrid integrated circuit interconnection structure and a hybrid integrated circuit interconnection method. The hybrid integrated circuit interconnection structure comprises a structure body, a boss arranged above the structure body and forming a stepped structure with the structure body, and through holes penetrating through the structure body and the boss. The sidewall of the stepped structure is a rounded structure. The hybrid integrated circuit interconnection structure and the hybrid integrated circuit interconnection method can solve the problems in the prior art, improve the efficiency of structure preparation, reduce the material rejection rate of structure mounting, realize automatic mounting of the structure, and meet the demand of automatic production of hybrid integrated circuit products.

A seed layer for deep vias in glass and its preparation method are disclosed, belonging to the field of semiconductor packaging and 3D integrated circuit interconnect technology. The seed layer is a four-layer composite seed layer structure sequentially prepared on the wall of the deep via in a glass substrate and the substrate surface, consisting of a PVD-Ti adhesion layer, a chemically plated Ni transition buffer layer, a chemically plated Cu conformal conductive layer, and a PVD surface Cu reinforcing layer. This invention solves problems such as shadowing effect, weak interface bonding, high residual stress, and seed layer disconnection in high aspect ratio TGV deep vias by designing a composite seed layer, achieving void-free metallization of glass vias with an aspect ratio ≥15:1, improving the structural stability and conductivity of the seed layer, and adapting it to the 3D high-density interconnect manufacturing of next-generation glass interposers. Simultaneously, by controlling key PVD parameters, the PVD sputtering effect is significantly improved, allowing the sputtered portion to penetrate deeper into the hole structure, thereby effectively improving the film coverage uniformity and adhesion performance.

An integrated circuit includes a first die and a second die. The second die is embedded or otherwise contained in a layered interconnect structure of the first die. The second die can be an IC die or it can be an electrically inactive element, such as a heat spreader. A portion of the layered interconnect structure is laterally adjacent to the second die. A first part of the second die can be electrically connected to a second part of the second die via the interconnect structure of the first die. The second die can be operatively coupled to the first die using electrical connections between the second die and one or more interconnect layers above or below the second die, or to devices of the first die. A method of fabricating an interconnect structure with one or more embedded dies is also disclosed.

The invention belongs to the technical field of metal materials and composite processing thereof, and discloses a high-strength and high-conductivity Cu-Ag-Cr-HEA composite plate and a preparation method thereof. HEA powder is composed of four refractory elements of Mo, Nb, W and Ta according to the equal molar ratio, the HEA powder and Cr powder are mixed according to the mass ratio of 1: 3 and subjected to ball milling, and Cr-HEA composite powder is obtained; and then the HEA alloy is mixed with Cu powder and Ag powder in proportion, and the Cu-Ag-Cr-HEA alloy is prepared through induction melting at the temperature of 1200-1400 DEG C. And the obtained Cu-Ag-Cr-HEA plates and pure Cu plates are alternately stacked, so that a Cu / Cu-Ag-Cr-HEA layered structure which is periodically and alternately distributed is formed. The tensile strength of the composite material reaches 800 MPa or above, the conductivity is kept at 80% IACS or above, and the composite material is suitable for the fields of high-magnetic-field conductor materials, electrical materials, integrated circuit interconnection materials and high-heat-load electronic packaging materials.

An optoelectronic component may include a substrate, an electronic integrated circuit supported by the substrate, and a photonic integrated circuit supported by the substrate. The optoelectronic component may include a plurality of substrate interconnect connectors disposed on the substrate, a plurality of electronic integrated circuit interconnect connectors disposed on the electronic integrated circuit, and a plurality of photonic integrated circuit interconnect connectors disposed on the photonic integrated circuit. The optoelectronic component may include a first plurality of cable connectors, each cable connector connected to the substrate, the electronic integrated circuit, and the photonic integrated circuit via respective interconnect connectors. The first plurality of cable connectors may be configured to facilitate electrical communication between the substrate, the electronic integrated circuit, and the photonic integrated circuit. The first plurality of cable connectors may define a first layout, and an overall connectivity of the optoelectronic component may correspond to the first layout.

A system that includes improved integrated circuit interconnects integrated with interconnect capacitors that reduce noise and improve signal quality is disclosed. The system comprises a first circuit board layer including a contact region of a conductor trace. The system further comprises a second layer including an interconnect capacitor, wherein the interconnect capacitor comprises a first side coupled over at least a portion of the contact region of the first circuit board layer to form a contact pad on a second side of the interconnect capacitor configured to interface with an integrated circuit chip.

An integrated circuit includes a combining circuit configured to generate a secret data string combining first digital information and second digital information, and, in the same storage plane, at least one first entropy cell is configured to provide the first digital information determined by a physical unclonable function of the first entropy cell. The at least one second memory cell is configured to provide second digital information determined by a charge contained in a non-volatile manner in a floating gate of a state transistor, the floating gate of the state transistor further connected to the at least one metal track of the integrated circuit interconnect portion.

A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.