Nano-electrode-array for integrated circuit interconnects
Patent Information
- Authority / Receiving Office
- US ยท United States
- Patent Type
- Applications(United States)
- Current Assignee / Owner
- KLA TENCOR TECH CORP
- Publication Date
- 2007-12-13
- Estimated Expiration
- Not applicable ยท inactive patent
Smart Images

Figure 1 
Figure 2 
Figure 3
Abstract
Description
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This is a Divisional of co-pending application Ser. No. 10 / 990,273 filed Nov. 15, 2004, which is hereby incorporated by reference herein.TECHNICAL FIELD
[0002] The present invention relates generally to semiconductor technology and more specifically to integrated circuit interconnects. BACKGROUND ART
[0003] In integrated circuits, transistors are made on a semiconductor substrate and connected together using integrated circuit interconnects. This process is performed using a number of different photolithographic, deposition, and removal processes to create contacts to the transistors, trenches to the contacts, and vias interconnecting the trenches where there are more than one level of channels.
[0004] Generally, a device dielectric layer is deposited over the transistors, openings are formed through the device dielectric layer down to transistor junctions and gates, and the openings are filled with a conductive metal to form contacts...