111 results about "Gate capacitance" patented technology

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

Disclosed are compute-in-memory devices that perform charge-domain MAC operations in a NAND-style string of FeFETs. Memory cells are coupled to word lines and bit lines, each FeFET storing a computational weight as a non-volatile polarization state established by polarization switching of a ferroelectric layer, the polarization state altering channel conduction and modulating gate capacitance. A selected read cell receives an input signal on a bit line, and a neighboring memory cell provides a sense node at its word line formed by the neighboring cell's gate capacitance. A control circuit biases the read and neighboring cells so that application of the input signal to the read cell conditionally transfers charge to the neighboring cell's gate capacitance according to the combination of the input and the read cell's polarization-dependent conduction state. A readout circuit senses an electrical quantity to yield a MAC compute result in the charge domain.

A gate driver includes a switching circuit outputting a gate driving voltage to a gate of a semiconductor power switching device (IGBT) via a series gate resistor. The gate driver further includes an external controllable capacitor circuit that is coupled at the gate of the semiconductor power switching device to provide an adjustable external gate capacitance in parallel with a parasitic gate or input capacitance of the IGBT. The capacitor circuit may be controlled by one or more electrical signals to vary the external gate capacitance and thereby the characteristics of a switching operation.

A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.

According to the 3T1R memory array applied to memory calculation of the memristor, on the basis of a traditional 1T1R / 2T1R unit, a third transistor T0 is introduced to form a 3T1R memristor memory unit, a bit line BL load is simplified into a T0 grid capacitor, and dynamic charging and discharging energy consumption is remarkably reduced; all T0 drains are interconnected through a driving line DL, and LDO constant voltage source driving is combined, so that the problem that a traditional BL load is large, and a capacitor is slow in charging and discharging is solved, the response speed is increased, and the time sequence tolerance is relaxed; a compensation factor k is introduced into an output transistor T2 of the 3T1R memristor storage unit, and flexible switching between a high-precision mode and a low-power-consumption mode is achieved by adjusting the width-to-length ratio of the output transistor T2. According to the technical scheme, the contradiction of power consumption, time sequence and drive circuit design in a traditional storage and calculation integrated array architecture can be effectively solved, and the storage and calculation integrated array architecture has the characteristics of ultralow energy consumption, high calculation precision and quick response, and can be widely applied to AI acceleration chips, edge calculation equipment and high-density nonvolatile memories.

The invention provides a light-emitting pixel particle, a display panel and electronic equipment. Each light-emitting pixel grain comprises a substrate, a light-emitting diode chip, a thin film transistor and a shading layer. The orthographic projection of the thin film transistor on the substrate and the orthographic projection of the light emitting diode chip on the substrate at least partially coincide. The light-emitting diode chip is electrically connected with the thin film transistor so as to achieve the display control function of the light-emitting pixel particles. The thin film transistor comprises a first thin film transistor, the first thin film transistor comprises a first source electrode, a first drain electrode and a first grid electrode, the capacitor comprises a first polar plate and a second polar plate, and the first polar plate and the second polar plate are arranged at intervals in the direction perpendicular to the substrate to form the capacitor. The first pole plate is electrically connected with the first source electrode, and the second pole plate is electrically connected with the first grid electrode to improve the voltage stability of the first thin film transistor. The first polar plate is arranged on the buffer layer, and the orthographic projection of the capacitor on the substrate and the orthographic projection of the light-emitting diode chip on the substrate at least partially coincide, so that the volume of the light-emitting pixel particles can be reduced.

A driver system comprising a bridge driver section, a switch FET section comprising: a drive stage section, a device section, and a current limiting section, wherein the switch FET section electrically couples the bridge driver section to the device section, wherein the fast current clamp is electrically coupled to the device section. By using the drive-bridge configuration, the gate capacitance of the switch FET can be charged and discharged quickly enough to meet the edge rate requirements. The switch FET is driven into and out of saturation such that the current through the device section is either on or off.

Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. The capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. The insulative tiers comprise an insulative material that is vertically between immediately-vertically-adjacent of the memory-cell tiers. The insulative material extends laterally beyond the digitline side and the capacitor side of the gates of immediately-vertically-adjacent of the memory cells. The insulative material is vertically thinnest laterally outward of the digitline side of the gates than at the capacitor side of the gates. Methods are disclosed.

A charge recycling circuit in an integrated circuit DC-DC converter having two power MOSFETs, the charge recycling circuit comprising a single inductor and recycling MOSFET switches arranged and sized such that when one of the two power MOSFETs is turning off, its gate capacitance charges are transferred to the single inductor, stored in the single inductor and then transferred directly to the gate of the other power MOSFET to turn it on.

This invention relates to the field of power semiconductor technology, specifically to an IGBT device resistant to single-event radiation and its fabrication method. By setting a P-type buried layer region at the bottom of the second trench, the strong electric field at the bottom of the trench is effectively weakened. Simultaneously, the P-type buried layer provides additional hole pathways, accelerating the extraction process of transient electron-hole pairs generated after high-energy particle incident, thereby effectively reducing the risk of single-event burn-out and improving the reliability of the device under irradiation. Furthermore, by introducing an N-type buried layer region at the bottom of the first trench, the electron injection effect is enhanced, increasing the carrier concentration in the on-state and reducing the on-state voltage drop. This structure also helps suppress the accumulation of holes below the gate during single-event incident, weakening the transient high electric field below the gate and improving the device's single-event tolerance. By reducing the depth of the first trench, the gate capacitance of the device can be effectively reduced, increasing the switching speed and reducing switching losses. In summary, this invention maintains radiation resistance while also ensuring high-frequency electrical performance.

The invention belongs to the technical field of control circuits, and particularly relates to a threshold current control circuit for a PSI5 interface. According to the circuit, the positive input end of an operational amplifier is connected with the drain electrode of an NMOS tube M1 and one end of a resistor R2, the negative input end of the operational amplifier is connected with one end of a resistor R1, and the output end of the operational amplifier is connected with the grid electrode of the NMOS tube M1; the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, the grid electrode of the NMOS tube M2 and one end of the resistor R4, and the source electrode of the NMOS tube M2 is grounded; the other end of the resistor R4 is connected with one end of a capacitor C1 and a grid electrode of the NMOS tube M3, and the other end of the capacitor C1 is grounded; the drain electrode of the NMOS tube M3 is connected with one end of the resistor R3, and the source electrode of the NMOS tube M3 is grounded; the other ends of the resistors R1, R2 and R3 are connected with a power supply; according to the invention, the threshold current control of the PSI5 interface is realized without depending on the feedback control of a digital circuit.

Memory circuitry includes: an insulating material and a vertically alternating level of memory cells, the memory cells individually including: a transistor including first and second source / drain regions, a channel region, and a gate; capacitors including first and second capacitor electrodes and a capacitor insulator, the first capacitor electrodes coupled to the first and second source / drain regions, and the second capacitor electrodes of a plurality of the capacitors coupled to each other; digital lines extending vertically through the vertically alternating tiers, individual ones of the second source / drain regions of individual ones of the transistors being electrically coupled to individual ones of the digital lines; and word lines in individual ones of the memory cell levels, the word lines including the gates of a plurality of the individual transistors, the word lines in a lower one of the memory cell levels have a minimum width greater than a minimum width of the word lines in a higher one of the memory cell levels directly above the lower memory cell level.

To provide a semiconductor device capable of reducing gate capacitance.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, a second electrode, a semiconductor layer having a first surface and a second surface opposite to the second electrode, a gate electrode including a first portion and a second portion extending in a first direction in the semiconductor layer, a field plate electrode provided in the semiconductor layer between the gate electrode and the second surface and electrically connected to the first electrode, and a second portion provided between the first portion and the second portion in the semiconductor layer. A conductive layer electrically isolated from the first electrode, and a field plate insulating layer provided between the field plate electrode and the semiconductor layer, wherein a first distance in the first direction between an end portion in the first direction of a first surface of the field plate insulating layer and the conductive layer is smaller than a second distance in the first direction from the end portion to the gate electrode.SELECTED DRAWING: Figure 3

The application relates to the technical field of power semiconductors, and discloses a resonant driving circuit control method and device, electronic equipment and a storage medium. The method comprises the following steps: in response to a pulse width modulation signal for controlling the turn-on of a power switching device, a first switch is controlled to be turned on, so that a power supply charges a gate capacitor of the power switching device through a resonant inductor and a driving resistor; after the first switch is turned on for a first preset time, the first switch is controlled to be turned off, so that the resonant inductor and the gate capacitor form a series resonant loop through the driving resistor; after the first switch is turned off for a second preset time, a second switch is controlled to be turned on, so that the gate voltage of the power switching device is clamped to the power supply voltage. According to the application, the first switch is actively turned off after being turned on for the first preset time, so that the circuit enters a series resonant state, and the second switch is turned on for clamping after the second preset time, so that the gate voltage waveform is smoothed, the overshoot is significantly suppressed, and the damage risk of the power switching device is reduced.

NEDMOS FETs capable of withstanding high drain voltages while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures. Each architecture provides a P or P+ pathway between the body of a NEDMOS device and a device-wide P+ body tie. The P / P+ pathway enables collection and conveyance of holes over to the device-wide body ties, resulting in elimination or substantial mitigation of the floating body effect. Use of a body tie spanning the width of the gate conductive layer (e.g., polysilicon) provides a number of benefits without reducing the effective width of the gate structure or increasing the gate capacitance CGG. Thus, one aspect of the present invention encompasses a MOSFET including a pathway between a body of the MOSFET and a device-wide body tie, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie.

Providing a display device or the like with a novel configuration in which the gate capacitance of a transistor connected to a scanning line is reduced. Or, providing a display device or the like with a novel configuration in which the resistance of a scanning line is reduced. Or, providing a display device or the like with a novel configuration in which pixels can be arranged with high definition. Or, providing a display device or the like with a novel configuration in which an increase in manufacturing cost is suppressed. [Solution] In a transistor having a first gate electrode and a second gate electrode connected to a scanning line, the first gate electrode is formed of a low-resistance metal material, and the second gate electrode is formed of a metal oxide material capable of reducing the oxygen deficiency of an oxide semiconductor layer. The first gate electrode is connected to the scanning line, and the second gate electrode is connected to a wiring to which a constant potential is applied. ​

The utility model relates to the technical field of electronic circuits, in particular to a power tube junction capacitance test circuit and device. Comprising a test power supply, a drain-source capacitance switching branch, a grid capacitance switching branch, a first switching branch and a second switching branch, the drain-source capacitance switching branch comprises a first switch and a third capacitor which are connected in series, and the gate capacitance switching branch is used for selecting whether a second capacitor is connected in series to a circuit between the gate of the tested MOS tube and a first interface of an external testing device or not; the first switching branch comprises a third switch and a first capacitor which are connected in series; and the second switching branch is used for switching and controlling whether the second interface and the third interface of the external testing device are connected with the source electrode of the MOS tube to be tested or not. In the same test circuit, the circuit required for testing different junction capacitors of the power tube is realized through switching of the switch, the defect that in the prior art, a PCB (Printed Circuit Board) is required to realize the function is overcome, and the test circuit has the characteristics of low cost, high efficiency and short consumed time.

The present application provides an integrated circuit for switching a switching element while suppressing noise. The integrated circuit is an integrated circuit for switching a second switching element of a switching circuit including a first switching element on a power supply side and the second switching element on a ground side connected in series, a first backflow diode connected in parallel with the first switching element, and a second backflow diode connected in parallel with the second switching element, wherein the integrated circuit includes a detection circuit that detects a load current flowing through a load of the switching circuit, and a drive circuit that controls the size of a current for charging a gate capacitance of the second switching element according to the size of the load current when a drive signal is one logic level, and causes the second switching element to be turned off when the drive signal is another logic level.

The invention relates to the technical field of semiconductors, and particularly discloses an MOSFET device with low grid charge and a preparation method of the MOSFET device. A LOCOS isolation layer; a P-type electric field regulation and control layer is shallowly buried under the channel; a transverse doping gradient channel; a gate dielectric layer; a main gate; a shield grid structure; the source side doping concentration of the asymmetric LDD region is 1 * 10 < 18 > cm <-3 >, the width is 0.1 mu m, and the depth is 50nm; the doping concentration of the drain side is 5 * 10 < 17 > cm <-3 >, the width is 0.15 mu m, and the depth is 50nm; a drain region is provided with a two-stage stepped groove; a source-drain heavily doped region; and the metal electrode comprises a source electrode, a main grid electrode, a shielding grid and a drain electrode. Through the synergistic effect of the shallow-buried P-type electric field regulation and control layer under the channel, the shield gate, the drain region two-stage stepped groove and the composite gate dielectric, the gate-drain coupling capacitance and the gate capacitance are reduced in principle, the Miller effect is inhibited, the ultra-thin gate and the NiSi silicide are combined to reduce the gate driving loss, meanwhile, sub-threshold electric leakage is inhibited, static and dynamic power consumption is doubly reduced, and the reliability of the device is improved. And the sensor endurance is prolonged.

Providing a display device or the like with a novel configuration in which the gate capacitance of a transistor connected to a scanning line is reduced. Or, providing a display device or the like with a novel configuration in which the resistance of a scanning line is reduced. Or, providing a display device or the like with a novel configuration in which pixels can be arranged with high definition. Or, providing a display device or the like with a novel configuration in which an increase in manufacturing cost is suppressed. 【Solution means】In a transistor having a first gate electrode and a second gate electrode connected to a scanning line, the first gate electrode is formed of a low-resistance metal material, and the second gate electrode is formed of a metal oxide material capable of reducing oxygen deficiency in an oxide semiconductor layer. The first gate electrode is connected to the scanning line, and the second gate electrode is connected to a wiring to which a fixed potential is applied. ​​​​​​​​

The application discloses a superconducting quantum capacity detector with large saturated power, which comprises a reference ground, a coplanar waveguide transmission line, a superconducting microwave resonator based on a tantalum film and a single Cooper pair box based on aluminum, the superconducting microwave resonator comprises a double helix inductor and an interdigital capacitor, the single Cooper pair box is connected to the interdigital capacitor through aluminum metal wires, the single Cooper pair box and the double helix inductor are located on the same side of the interdigital capacitor, and the single Cooper pair box is located above the double helix inductor, so that the detector unit is more compact, the space utilization is increased, and the number of pixels of a multi-pixel focal plane detector array is increased; the gate capacitor is designed in the shape of a tuning fork, compared with an existing parallel wire structure, double capacitance values can be obtained without increasing the volume of a superconducting island, the smaller the volume of the superconducting island is, the more significant the quantum capacity effect of the detector is, and the more obvious the response is, the larger the gate capacitor is, and the larger the saturated power of the detector is, so that the saturated power can be increased without losing sensitivity.

This disclosure relates to display devices, display modules, and electronic devices. A novel display device with a small gate capacitance of a transistor connected to a scan line is provided. A novel display device with low resistance of the scan line is provided, etc. A novel display device capable of configuring pixels with high resolution is provided, etc. A novel display device capable of being manufactured without increasing costs is provided, etc. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is made of a low-resistance metal material, and the second gate electrode is made of a metal oxide material capable of reducing oxygen defects in an oxide semiconductor layer. The first gate electrode is connected to a scan line, and the second gate electrode is connected to a wiring supplied with a constant potential.

The utility model relates to the field of power electronic testing, in particular to a switching tube driving circuit with adjustable gate capacitance and a load circuit, the switching tube driving circuit is connected with a switching tube and comprises a driving chip, an output end of the driving chip is connected with a gate electrode of the switching tube, and an acquisition end of the driving chip is connected with a collector electrode and an emitter electrode of the switching tube. Acquiring a voltage waveform to obtain a voltage change rate of the switching tube; the first end of the gate capacitor is connected with the gate electrode of the switching tube, the second end of the gate capacitor is connected with the emitting electrode of the switching tube, the driving chip outputs a capacitance control signal based on the voltage change rate, and the gate capacitor is controllably adjusted to a capacitance value corresponding to the capacitance control signal. According to the utility model, a fixed gate pole capacitor is changed into a gate pole capacitor with an adjustable capacitance value, so that the adjustable gate pole capacitor can be dynamically adjusted according to the numerical value of the voltage change rate under different working conditions, the switching loss and temperature rise are reduced, and the performance of a switching tube is improved.

This gate drive device supplies a gate voltage to a power semiconductor element. The gate drive device comprises: a parallel circuit that is provided in a current path for charging and discharging the gate capacitance of the power semiconductor element and has a diode, the forward direction of which is a direction in which a charge / discharge current flows, and a switching element connected in parallel with the diode; and a control unit that controls the switching element to be in an off state at the start of a turn-on operation or a turn-off operation of the power semiconductor element and controls the switching element to be in an on state after the start of the turn-on operation or the turn-off operation.

The invention belongs to the technical field of semiconductors, and particularly relates to a gallium nitride junction field effect transistor device with a high-K dielectric buried layer. According to the gallium nitride junction field effect transistor device with the high-K dielectric buried layer, reverse electric leakage can be reduced, most of electric displacement lines generated by a depletion drift region under reverse bias pass through the buffer layer filled with the high-K material, so that a longitudinal electric field is dispersed, and the breakdown voltage of the device is improved; the high-K dielectric buried layer can generate a polarization charge shielding effect, the grid-control threshold voltage (Vth) is increased by more than 0.5 V, and the grid capacitance is reduced. Compared with a traditional MOSFET, the high doping concentration can be adopted in the drift region under the same breakdown voltage, the on-resistance is reduced, the reliability problem of a GaN device in practical application is solved, and the application range of the GaN device in the field of power switches is widened.

The invention discloses an electronic device, a working method, a power amplifier and communication equipment, relates to the technical field of communication, and is used for improving efficiency and linearity. The electronic device comprises a first HEMT device, a second HEMT device, a first grid electrode, a second grid electrode, a source electrode and a drain electrode, the first grid electrode is connected with the grid electrode of the first HEMT device and the source electrode of the second HEMT device, the source electrode of the electronic device is connected with the source electrode of the first HEMT device, the drain electrode of the electronic device is connected with the drain electrode of the first HEMT device, and the second grid electrode is connected with the grid electrode of the second HEMT device. The drain of the second HEMT device is electrically floating, and the gate-source capacitance of the first HEMT device can be compensated through the source-gate capacitance of the second HEMT device, so that the sum of the capacitance values of the source-gate capacitance of the second HEMT device and the gate-source capacitance of the first HEMT device is kept unchanged along with the change of the voltage of the first gate, and the efficiency and the linearity are improved.

A gate driver for slew rate control includes a buffer controller that switches and outputs a power supply voltage by a high or low level control signal; a buffer unit that delays and outputs the voltage output by the buffer controller; an output switch unit that is turned on or off according to a voltage level applied through the buffer unit and outputs a driving voltage by including an output transistor, wherein an input terminal of the buffer unit is connected to a gate terminal of the output transistor; a capacitor electrically connected between the input terminal of the buffer unit and a drain terminal of the output transistor; and a current source that is connected to the power supply voltage terminal and generates a current that is charged in the capacitor, wherein the capacitor adjusts a slope of a gate voltage of the output transistor during a rising or falling transition, and the output transistor may adjust a slope of the driving voltage output to the drain terminal during a falling or rising transition by the capacity of the capacitor.

Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.

The invention discloses a method for testing electrostatic shock resistance of a grid electrode of a metal oxide semiconductor field effect transistor, which comprises the following steps of: firstly, testing a maximum voltage value which can be borne between the grid electrode of a device and other electrodes under transient pulse by utilizing a transmission line pulse tester; the maximum voltage value capable of being borne by the device grid and the capacitance of the device grid are substituted into corresponding formulas, and the anti-static impact capacity of the device in the human body mode and the machine mode is calculated respectively. According to the method, only one testing device of the transmission line pulse generator is needed, the grid anti-static impact capacity of the device in the two modes can be obtained through one-time sample testing, the number of needed samples is small, the testing time is short, the testing precision is high, and the defects of a traditional testing method are overcome.

The present application relates to the technical field of integrated circuits, in particular to a combined power tube driving circuit and method, and a power supply device adopting the combined power tube driving circuit or method. The combined power tube driving circuit is applied to drive a combined power tube module with a high-side power tube and a low-side power tube connected in series, and has a power supply capacitor with a second end electrically connected to ground. The combined power tube driving circuit comprises a high-side driving module and a low-side driving module. A switch control signal passes through the combined power tube driving circuit to control the combined power tube module to turn on and off. The combined power tube driving circuit proposed in the present application charges the high-side power tube gate capacitor by using a controlled current, and uses the channel of a MOS tube to turn off the discharge current of the high-side power tube gate capacitor, thereby realizing a control mode of slow turn-on and fast turn-off of the high-side power tube, overcoming the influence of mis-triggering of the latc-up caused by the non-ideal forward conduction current of the diode, and improving the reliability of the system.