149 results about "Gate capacitance" patented technology

Methods and apparatus for filtering a signal using a current mode filter circuit that enables source degradation. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor including a drain coupled with the input node; a second transistor including a drain coupled with the output node and including a gate coupled with a gate of the first transistor; a capacitive element coupled between a drain of the first transistor and the power supply node; a first resistive element coupled between the drain electrode and the gate electrode of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

Disclosed are compute-in-memory devices that perform charge-domain MAC operations in a NAND-style string of FeFETs. Memory cells are coupled to word lines and bit lines, each FeFET storing a computational weight as a non-volatile polarization state established by polarization switching of a ferroelectric layer, the polarization state altering channel conduction and modulating gate capacitance. A selected read cell receives an input signal on a bit line, and a neighboring memory cell provides a sense node at its word line formed by the neighboring cell's gate capacitance. A control circuit biases the read and neighboring cells so that application of the input signal to the read cell conditionally transfers charge to the neighboring cell's gate capacitance according to the combination of the input and the read cell's polarization-dependent conduction state. A readout circuit senses an electrical quantity to yield a MAC compute result in the charge domain.

A semiconductor device is provided which is a trench MOSFET with a vertical channel fin structure, capable of improving short-circuit tolerance and reducing gate capacitance while maintaining high channel density.A semiconductor 1 is configured so that a channel current flows in the vertical direction, and comprises: a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction in plan view, the plurality of trenches being arranged in the second direction; a first source region 3 of a first conductivity type; a second source region 4 of the first conductivity type and including a region having a fin structure at least partially partitioned by the plurality of trenches 2; a channel region 5 of a second conductivity type and having a fin structure partitioned by the plurality of trenches 2; a gate insulating film and gate electrodes disposed in the trenches 2; and a JFET region 8 of the first conductivity type and a body region 9 of the second conductivity type.The second source region 4 has a shallower depth from a surface than the first source region 3.

A gate driver includes a switching circuit outputting a gate driving voltage to a gate of a semiconductor power switching device (IGBT) via a series gate resistor. The gate driver further includes an external controllable capacitor circuit that is coupled at the gate of the semiconductor power switching device to provide an adjustable external gate capacitance in parallel with a parasitic gate or input capacitance of the IGBT. The capacitor circuit may be controlled by one or more electrical signals to vary the external gate capacitance and thereby the characteristics of a switching operation.

The invention discloses a discontinuous current type variable duty ratio output resonant gate drive circuit, and belongs to the field of power electronics. The resonant gate drive circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube, two NMOS (N-channel Metal Oxide Semiconductor) tubes, an inductor L and a voltage stabilizing capacitor, the on-off states of the PMOS tube and the NMOS tubes are controlled by controlling the time sequence of gate drive signals of the PMOS tube and the NMOS tubes, and inductive current flowing through the inductor is in a discontinuous state. The resonant state of the inductor and the gate capacitor of the driven circuit and the duty ratio of the driving output voltage are further controlled. The inductive current of the circuit is discontinuous, the conduction loss of the circuit is greatly reduced, the grid driving energy recovery ratio is improved, and the duty ratio conversion of the driving signal can be realized by controlling the duty ratio of the driving signal. Therefore, the technical problems that the energy recovery rate is low, the number of control signals is large, signal matching is difficult, the occupied area is large, miniaturization is not facilitated, and the duty ratio cannot be adjusted in the driving technology are solved.

A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.

According to the 3T1R memory array applied to memory calculation of the memristor, on the basis of a traditional 1T1R / 2T1R unit, a third transistor T0 is introduced to form a 3T1R memristor memory unit, a bit line BL load is simplified into a T0 grid capacitor, and dynamic charging and discharging energy consumption is remarkably reduced; all T0 drains are interconnected through a driving line DL, and LDO constant voltage source driving is combined, so that the problem that a traditional BL load is large, and a capacitor is slow in charging and discharging is solved, the response speed is increased, and the time sequence tolerance is relaxed; a compensation factor k is introduced into an output transistor T2 of the 3T1R memristor storage unit, and flexible switching between a high-precision mode and a low-power-consumption mode is achieved by adjusting the width-to-length ratio of the output transistor T2. According to the technical scheme, the contradiction of power consumption, time sequence and drive circuit design in a traditional storage and calculation integrated array architecture can be effectively solved, and the storage and calculation integrated array architecture has the characteristics of ultralow energy consumption, high calculation precision and quick response, and can be widely applied to AI acceleration chips, edge calculation equipment and high-density nonvolatile memories.

A method for operating a semiconductor switching device having a gate capacitance to switch the device from a starting steady state to an ending steady comprises: applying a first voltage pulse to a gate of the device when the device is in the starting steady state; and applying a second voltage pulse to the gate after applying the first gate driving pulse. The second voltage pulse is applied during a transition of the device between the starting steady state and the ending steady state.

The invention provides a light-emitting pixel particle, a display panel and electronic equipment. Each light-emitting pixel grain comprises a substrate, a light-emitting diode chip, a thin film transistor and a shading layer. The orthographic projection of the thin film transistor on the substrate and the orthographic projection of the light emitting diode chip on the substrate at least partially coincide. The light-emitting diode chip is electrically connected with the thin film transistor so as to achieve the display control function of the light-emitting pixel particles. The thin film transistor comprises a first thin film transistor, the first thin film transistor comprises a first source electrode, a first drain electrode and a first grid electrode, the capacitor comprises a first polar plate and a second polar plate, and the first polar plate and the second polar plate are arranged at intervals in the direction perpendicular to the substrate to form the capacitor. The first pole plate is electrically connected with the first source electrode, and the second pole plate is electrically connected with the first grid electrode to improve the voltage stability of the first thin film transistor. The first polar plate is arranged on the buffer layer, and the orthographic projection of the capacitor on the substrate and the orthographic projection of the light-emitting diode chip on the substrate at least partially coincide, so that the volume of the light-emitting pixel particles can be reduced.

A driver system comprising a bridge driver section, a switch FET section comprising: a drive stage section, a device section, and a current limiting section, wherein the switch FET section electrically couples the bridge driver section to the device section, wherein the fast current clamp is electrically coupled to the device section. By using the drive-bridge configuration, the gate capacitance of the switch FET can be charged and discharged quickly enough to meet the edge rate requirements. The switch FET is driven into and out of saturation such that the current through the device section is either on or off.

To reduce the number of elements in a pixel circuit for providing a specific function.SOLUTION: A light-emitting device comprises a light-emitting element, a drive transistor and a switching transistor respectively arranged on a route through which current for causing the light-emitting element to emit light flows, a writing transistor arranged on a route connecting a signal line through which pixel signals are supplied and a gate of the drive transistor, and a capacitive transistor for maintaining the gate-source voltage of the drive transistor. A gate of the capacitive transistor is connected with the gate of the drive transistor. A source and a drain of the capacitive transistor are respectively connected with a source of the drive transistor. The capacitive transistor and the switching transistor are formed in the same impurity region. The conductivity type of the capacitive transistor is the same as the conductivity type of the drive transistor.SELECTED DRAWING: Figure 2

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT device with a split gate structure and a preparation method of the super-junction IGBT device. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction P column, a P-type buried layer, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, the cell width is reduced, meanwhile, the parasitic PMOS introduced by only adding one photoetching plate acts, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current of the device is reduced, and the control capability of the gate of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. The capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. The insulative tiers comprise an insulative material that is vertically between immediately-vertically-adjacent of the memory-cell tiers. The insulative material extends laterally beyond the digitline side and the capacitor side of the gates of immediately-vertically-adjacent of the memory cells. The insulative material is vertically thinnest laterally outward of the digitline side of the gates than at the capacitor side of the gates. Methods are disclosed.

The invention discloses a high-precision quick-response POR circuit which comprises a starting sub-circuit, a reference sub-circuit connected to the starting sub-circuit and a comparison sub-circuit connected to the reference sub-circuit, the comparison sub-circuit comprises a constant current source module and a POR comparison module, the constant current source module is connected to the reference sub-circuit, and the POR comparison module is connected to the reference sub-circuit. A constant current source is provided for the POR comparison module; the POR comparison module comprises an eighth NMOS tube, a ninth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth resistor and a comparator, and receives a reference voltage and a sampling voltage through source electrodes of the thirteenth PMOS tube and the fourteenth PMOS tube respectively, so that the influence of parasitic gate capacitance is reduced, the response speed is greatly improved, when a system is quickly powered down, detection and feedback can be performed in time, and the system is prevented from being damaged. The detection threshold precision of the existing POR circuit is greatly improved, and the purpose of protecting the circuit and the system is achieved.

A charge recycling circuit in an integrated circuit DC-DC converter having two power MOSFETs, the charge recycling circuit comprising a single inductor and recycling MOSFET switches arranged and sized such that when one of the two power MOSFETs is turning off, its gate capacitance charges are transferred to the single inductor, stored in the single inductor and then transferred directly to the gate of the other power MOSFET to turn it on.

This invention relates to the field of power semiconductor technology, specifically to an IGBT device resistant to single-event radiation and its fabrication method. By setting a P-type buried layer region at the bottom of the second trench, the strong electric field at the bottom of the trench is effectively weakened. Simultaneously, the P-type buried layer provides additional hole pathways, accelerating the extraction process of transient electron-hole pairs generated after high-energy particle incident, thereby effectively reducing the risk of single-event burn-out and improving the reliability of the device under irradiation. Furthermore, by introducing an N-type buried layer region at the bottom of the first trench, the electron injection effect is enhanced, increasing the carrier concentration in the on-state and reducing the on-state voltage drop. This structure also helps suppress the accumulation of holes below the gate during single-event incident, weakening the transient high electric field below the gate and improving the device's single-event tolerance. By reducing the depth of the first trench, the gate capacitance of the device can be effectively reduced, increasing the switching speed and reducing switching losses. In summary, this invention maintains radiation resistance while also ensuring high-frequency electrical performance.

A circuit 200 includes one or more tri-state inverters 202A...202N, wherein each enabled tri-state inverter provides a respective delay adjustment of a signal waveform. The delay adjustment may be les

The invention belongs to the technical field of control circuits, and particularly relates to a threshold current control circuit for a PSI5 interface. According to the circuit, the positive input end of an operational amplifier is connected with the drain electrode of an NMOS tube M1 and one end of a resistor R2, the negative input end of the operational amplifier is connected with one end of a resistor R1, and the output end of the operational amplifier is connected with the grid electrode of the NMOS tube M1; the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, the grid electrode of the NMOS tube M2 and one end of the resistor R4, and the source electrode of the NMOS tube M2 is grounded; the other end of the resistor R4 is connected with one end of a capacitor C1 and a grid electrode of the NMOS tube M3, and the other end of the capacitor C1 is grounded; the drain electrode of the NMOS tube M3 is connected with one end of the resistor R3, and the source electrode of the NMOS tube M3 is grounded; the other ends of the resistors R1, R2 and R3 are connected with a power supply; according to the invention, the threshold current control of the PSI5 interface is realized without depending on the feedback control of a digital circuit.

Memory circuitry includes: an insulating material and a vertically alternating level of memory cells, the memory cells individually including: a transistor including first and second source / drain regions, a channel region, and a gate; capacitors including first and second capacitor electrodes and a capacitor insulator, the first capacitor electrodes coupled to the first and second source / drain regions, and the second capacitor electrodes of a plurality of the capacitors coupled to each other; digital lines extending vertically through the vertically alternating tiers, individual ones of the second source / drain regions of individual ones of the transistors being electrically coupled to individual ones of the digital lines; and word lines in individual ones of the memory cell levels, the word lines including the gates of a plurality of the individual transistors, the word lines in a lower one of the memory cell levels have a minimum width greater than a minimum width of the word lines in a higher one of the memory cell levels directly above the lower memory cell level.

The invention discloses a complementary type inverse F-class voltage-controlled oscillator and a nested type voltage-controlled oscillator thereof, and mainly solves the problem that an existing oscillator is large in occupied area or high in cost. The oscillator is composed of two same active cores A1 and A2, each active core internally comprises a pair of complementary NMOS (N-channel Metal Oxide Semiconductor) tube and PMOS (P-channel Metal Oxide Semiconductor) tube, a drain capacitor CD is connected between the drain of the NMOS tube and the drain of the PMOS tube, a grid capacitor CG is connected between the grid of the NMOS tube and the grid of the PMOS tube, and the two active cores are mutually connected through four transformers. According to the complementary type inverse F-type voltage-controlled oscillator, broadband coverage, high performance and low phase noise under high frequency are achieved, inductance nesting is carried out through the basic units, the problem that the occupied area of a multi-core oscillator is too large is greatly solved, the requirements for small size and low cost of a chip are met, and the complementary type inverse F-type voltage-controlled oscillator is suitable for large-scale popularization and application. And in addition, good performance consistency is achieved under the broadband condition.

A p layer is a semiconductor base material. An n+ layer is disposed on one extension side of the layer. An n+ layer is disposed on the opposite side in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in electrical separation from the layer. Memory operation is performed by applying voltage to each of the layers. In this case, the gate capacitance of a MOS structure constituted by the layers per unit area is smaller than that of a MOS structure constituted by the layers.

The invention relates to a high-power-supply-rejection-ratio low-dropout linear voltage regulator based on gate capacitance offset. The high-power-supply-rejection-ratio low-dropout linear voltage regulator comprises an error amplifier, a power tube MP, feedback networks R1 and R2, a load capacitor CL, a frequency compensation capacitor CM and a gate capacitance offset circuit. The output end of the error amplifier, the output end of the grid capacitance offset circuit and the grid of the power tube MP are connected with one end of the frequency compensation capacitor CM; the other end of the frequency compensation capacitor CM, the drain electrode of the power tube MP, one end of the resistor R1 and one end of the load capacitor CL are connected with a VOUT end; the source electrode of the power tube MP is connected with the VIN end; the other end of the load capacitor CL and one end of the resistor R2 are connected with a grounding end GND; the other end of the resistor R1 and the other end of the resistor R2 are connected with the in-phase input end VFB of the error amplifier. The gate capacitance offset circuit is introduced to the output of the error amplifier, so that the equivalent capacitance of the node is changed, the gain from input to output is reduced, and the power supply suppression capability is improved.

To provide a semiconductor device capable of reducing gate capacitance.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, a second electrode, a semiconductor layer having a first surface and a second surface opposite to the second electrode, a gate electrode including a first portion and a second portion extending in a first direction in the semiconductor layer, a field plate electrode provided in the semiconductor layer between the gate electrode and the second surface and electrically connected to the first electrode, and a second portion provided between the first portion and the second portion in the semiconductor layer. A conductive layer electrically isolated from the first electrode, and a field plate insulating layer provided between the field plate electrode and the semiconductor layer, wherein a first distance in the first direction between an end portion in the first direction of a first surface of the field plate insulating layer and the conductive layer is smaller than a second distance in the first direction from the end portion to the gate electrode.SELECTED DRAWING: Figure 3

The application relates to the technical field of power semiconductors, and discloses a resonant driving circuit control method and device, electronic equipment and a storage medium. The method comprises the following steps: in response to a pulse width modulation signal for controlling the turn-on of a power switching device, a first switch is controlled to be turned on, so that a power supply charges a gate capacitor of the power switching device through a resonant inductor and a driving resistor; after the first switch is turned on for a first preset time, the first switch is controlled to be turned off, so that the resonant inductor and the gate capacitor form a series resonant loop through the driving resistor; after the first switch is turned off for a second preset time, a second switch is controlled to be turned on, so that the gate voltage of the power switching device is clamped to the power supply voltage. According to the application, the first switch is actively turned off after being turned on for the first preset time, so that the circuit enters a series resonant state, and the second switch is turned on for clamping after the second preset time, so that the gate voltage waveform is smoothed, the overshoot is significantly suppressed, and the damage risk of the power switching device is reduced.

NEDMOS FETs capable of withstanding high drain voltages while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures. Each architecture provides a P or P+ pathway between the body of a NEDMOS device and a device-wide P+ body tie. The P / P+ pathway enables collection and conveyance of holes over to the device-wide body ties, resulting in elimination or substantial mitigation of the floating body effect. Use of a body tie spanning the width of the gate conductive layer (e.g., polysilicon) provides a number of benefits without reducing the effective width of the gate structure or increasing the gate capacitance CGG. Thus, one aspect of the present invention encompasses a MOSFET including a pathway between a body of the MOSFET and a device-wide body tie, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie.

The embodiment of the invention provides a slow opening circuit and a battery control circuit, and belongs to the technical field of batteries. According to the scheme, in a battery power supply scene, when a first control signal is changed from low to high, power supply voltage is not directly applied to a control end of a power switch, but a grid capacitor of the power switch is charged through a resistor in a slow opening circuit; in addition, the charging time can accurately control the on or off of each MOS tube in the slow opening circuit through the first control signal and the second control signal, so as to accurately control the time when the gate-source voltage of the power switch rises from 0 to the threshold voltage, and further accurately control the time consumed by the power switch from the off to the on. The voltage of the battery port changes slowly and is not lower than the voltage of the chip, and the phenomenon that the normal function is influenced by restarting of the chip due to too low voltage is avoided, so that the reliability of the battery control circuit is improved.

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT (Insulated Gate Bipolar Translator) with a split gate structure and a manufacturing method thereof. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction N column contact, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, a P-type doped region is injected into the bottom of a trench gate, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, cells are reduced, meanwhile, the P columns and the N columns act on a parasitic PMOS, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current is reduced, and the control capability of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

Providing a display device or the like with a novel configuration in which the gate capacitance of a transistor connected to a scanning line is reduced. Or, providing a display device or the like with a novel configuration in which the resistance of a scanning line is reduced. Or, providing a display device or the like with a novel configuration in which pixels can be arranged with high definition. Or, providing a display device or the like with a novel configuration in which an increase in manufacturing cost is suppressed. [Solution] In a transistor having a first gate electrode and a second gate electrode connected to a scanning line, the first gate electrode is formed of a low-resistance metal material, and the second gate electrode is formed of a metal oxide material capable of reducing the oxygen deficiency of an oxide semiconductor layer. The first gate electrode is connected to the scanning line, and the second gate electrode is connected to a wiring to which a constant potential is applied. ​

The utility model relates to the technical field of electronic circuits, in particular to a power tube junction capacitance test circuit and device. Comprising a test power supply, a drain-source capacitance switching branch, a grid capacitance switching branch, a first switching branch and a second switching branch, the drain-source capacitance switching branch comprises a first switch and a third capacitor which are connected in series, and the gate capacitance switching branch is used for selecting whether a second capacitor is connected in series to a circuit between the gate of the tested MOS tube and a first interface of an external testing device or not; the first switching branch comprises a third switch and a first capacitor which are connected in series; and the second switching branch is used for switching and controlling whether the second interface and the third interface of the external testing device are connected with the source electrode of the MOS tube to be tested or not. In the same test circuit, the circuit required for testing different junction capacitors of the power tube is realized through switching of the switch, the defect that in the prior art, a PCB (Printed Circuit Board) is required to realize the function is overcome, and the test circuit has the characteristics of low cost, high efficiency and short consumed time.