Flip-flop circuit

Abstract

To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a mater latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This Nonprovisional application claims priority under 35 U.S.C. §119 (a) on Patent Application No. 2004-179954 filed in Japan on Jun. 17, 2004, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION [0002] The present invention mainly relates to flip-flop circuits constituted by transistors formed as semiconductor integrated circuits (LSIs). [0003] Performances required of recent LSIs have been rapidly enhanced in recent years, and LSI manufacturers have competed to achieve higher functionality and higher operation speed. LSI circuits for use in synchronous digital signal processing, for example, are designed to use flip-flop circuits as necessary components. Therefore, to achieve faster LSI circuits, every manufacturer has to increase the speed of flip-flop circuits. [0004] In view of this, various configurations of flip-flop circuits for high speed operation have been proposed to date. For exampl...

AI Technical Summary

Benefits of technology

[0017] With this configuration, a signal input immediately before a timing signal changes from a first state to a second state is output with a short delay and, in addition, input capacitance and / or driving capability are / is constant irrespective of the state of the timing signal. Accordingly, the input capacitance and the driving capability are easily extracted as those of a standard cell and circuit design is completed in a short period.

[0020] If a tri-state inverter or an inverter is used as the tri-state element or the driver described above, a signal at a desired level is easily held and output without the use of additional inverter.

Problems solved by technology

Therefore, the flip-flop circuit has a drawback in which it is difficult to design and develop a circuit including such a flip-flop circuit in a short period.

However, in the case where physical characteristics at the input and output vary depending on the state of a clock signal as described above, it is difficult to extract physical characteristics that are to be registered in a library as those of standard cells.

If physical characteristics associated with the respective states of the clock signal are extracted and registered in the library, different operations are needed for the respective states of the clock signal during a timing verification of a circuit using such cells, so that processing becomes very complicated.

Therefore, a circuit design using the cell-base design as described above is difficult in reality.

In these circumstances, it has been impossible to design and develop circuits including flip-flop circuits in short periods.

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