212 results about "Gate resistance" patented technology

The invention provides a device for inhibiting drain-source overvoltage and overcurrent through active gate drive of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), aiming at solving the problem of voltage or current overshoot caused by circuit parasitic parameters in a high-speed switching process of the SiC MOSFET and simultaneously considering the switching speed and energy loss balance. According to the device, drain-source voltage vdc and direct-current bus voltage of the SiC MOSFET are collected to serve as feedback signals, and gate driving voltage and equivalent gate resistance are dynamically adjusted; in a key stage (a Miller plateau switching-on period and a voltage rising period switching-off period) of a switch transient state, a gate resistance network is switched through a logic control circuit, and suppression of drain current overshoot and drain-source voltage overshoot is realized. Simulation verification shows that the device can reduce voltage overshoot by 20%-30% and current overshoot by 25%-60%, only a single voltage feedback channel is needed, the cost is obviously lower than that of a traditional multi-signal acquisition active gate driving scheme, and the device is suitable for a high-efficiency SiC MOSFET power converter.

The utility model provides an insulated gate bipolar transistor driving circuit with adjustable positive and negative voltages, comprising a magnetic isolation module, the input end of which is connected with a driving signal and outputs an isolation driving signal; the input end of the first voltage regulating module is connected with the first positive voltage and outputs a second positive voltage within a first preset range; the input end of the second voltage regulating module is connected with the first negative voltage and outputs a second negative voltage within a second preset range; the push-pull output module is connected between the second positive voltage and the second negative voltage, the control end of the push-pull output module is connected with an isolation driving signal, and the output end of the push-pull output module is connected with the gate pole of the to-be-tested insulated gate bipolar transistor through a gate resistor; and the protection module is controllably connected between the output end of the push-pull output module and the second voltage regulation module under the action of the control signal. The driving circuit has the beneficial effects that the positive and negative voltage output capability can be flexibly adjusted according to debugging requirements, the working condition requirements of different clients are met, and the flexibility and adaptability of the driving circuit are improved.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a radio frequency switch chip, and the circuit structure of the radio frequency switch chip comprises a transformer type differential inductor T-L1, a transformer type differential inductor T-L2, a capacitor C1, an NMOS transistor M1, an NMOS transistor M2, a gate resistor RG1, and a gate resistor RG2. The radio frequency switch chip provided by the invention adopts a differential structure, so that the parasitic inductance effect of a grounding key and a wire during packaging and testing can be eliminated, and the insertion loss and the isolation performance are improved; compared with a single-end port, the lower impedance of the differential port is more beneficial to improving the power capacity of the switch; the differential structure allows the transformer type differential inductor to use differential signal characteristics, the equivalent quality factor of the inductor is improved, and the circuit performance is improved; the differential structure can improve the linearity of the circuit, especially the second-order intermodulation effect; the differential structure can be compatible with a modern silicon-based CMOS radio frequency system, and an additional balun is not needed for signal conversion.

The invention relates to the technical field of overvoltage control, and particularly discloses an overvoltage control method and device for an IGBT module, and the method comprises the steps: carrying out the time sequence correlation analysis of collector current time sequence data through employing a deep learning algorithm after receiving a turn-off instruction, extracting the short-time fluctuation characteristics of collector current, and obtaining the short-time fluctuation characteristics of the collector current; and the initial gate resistance value is combined to dynamically predict the collector-emitter voltage peak amplitude possibly generated in the turn-off process. And based on comparison between the predicted voltage spike amplitude and a preset threshold value, an initial gate driving strategy is generated to guide the turn-off operation. In the turn-off execution stage, collector-emitter voltage data flow is monitored in real time and dynamically compared with a safety threshold value, and therefore closed-loop optimization adjustment is conducted on a driving strategy. According to the method, prospective evaluation and self-adaptive control of the overvoltage risk are realized through intelligent prediction of the turn-off transient voltage spike, the switching loss can be optimized while the overvoltage is suppressed, and the limitation of traditional fixed parameter control is broken through.

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

The application discloses a switch tube off negative voltage determination method and device and a switch tube driving control circuit. The switch tube off negative voltage determination method comprises the following steps: determining a first off negative voltage model and a second off negative voltage model; inputting the obtained off gate resistance, on gate resistance, bus voltage and minimum on voltage of the switch tube into the first off negative voltage model to obtain an upper limit absolute value of the off negative voltage of the switch tube; inputting the obtained off gate resistance, on gate resistance, bus voltage and maximum bearable negative voltage absolute value of the switch tube into the second off negative voltage model to obtain a lower limit absolute value of the off negative voltage of the switch tube; and determining the off negative voltage interval of the switch tube according to the upper limit absolute value and the lower limit absolute value. When the off negative voltage interval is used for negative voltage off control of the switch tube, the switch tube can be effectively prevented from being mis-opened, the switch tube can be protected, and the service life of the switch tube is prolonged.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

The invention relates to a novel semiconductor power device with a built-in gate resistor structure and a preparation method of the novel semiconductor power device. The active region of the semiconductor substrate is provided with a grid electrode electrolyte layer, the grid electrode electrolyte layer is provided with a polycrystalline silicon layer, the polycrystalline silicon layer is provided with first through holes, each first through hole is provided with a temperature coefficient thermistor, the temperature coefficient thermistors extend out of the first through holes, the polycrystalline silicon layer and the temperature coefficient thermistors are provided with interlayer dielectric layers, and the interlayer dielectric layers are arranged between the polycrystalline silicon layer and the temperature coefficient thermistors. The interlayer dielectric layer is provided with a second through hole and a third through hole, the second through hole is filled with a first metal layer, the third through hole is filled with a second metal layer, the interlayer dielectric layer is provided with a grid electrode bonding pad and a grid electrode flow channel, and the grid electrode bonding pad, the grid electrode flow channel and the interlayer dielectric layer are provided with passivation layers. The novel semiconductor power device with the built-in gate resistor structure is designed to solve the technical problem that an existing semiconductor power device with the built-in gate resistor structure is high in loss at a high temperature.

The invention discloses a SiC MOSFET junction temperature on-line acquisition circuit which is connected with a to-be-measured SiC MOSFET for junction temperature acquisition, an independent grid peak current acquisition circuit is additionally arranged, and a low-frequency intermittent sampling strategy is adopted, so that a sampling resistor is in a non-working state in most of time, temperature rise is inhibited, the stability of the resistance value of the sampling resistor is ensured, and the reliability of the sampling resistor is improved. Accuracy of grid peak current acquisition and junction temperature prediction precision are substantially improved. The invention also discloses a SiC MOSFET junction temperature on-line acquisition method. According to the SiC MOSFET junction temperature on-line acquisition circuit and method provided by the invention, the grid resistance network and the grid peak current acquisition circuit are constructed, so that the self-heating problem of the sampling resistor under a high-frequency switch is solved.

A gate driver includes a switching circuit outputting a gate driving voltage to a gate of a semiconductor power switching device (IGBT) via a series gate resistor. The gate driver further includes an external controllable capacitor circuit that is coupled at the gate of the semiconductor power switching device to provide an adjustable external gate capacitance in parallel with a parasitic gate or input capacitance of the IGBT. The capacitor circuit may be controlled by one or more electrical signals to vary the external gate capacitance and thereby the characteristics of a switching operation.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

A semiconductor device includes: a substrate; an epitaxial structure located on a side of the substrate; a gate electrode located on the side, facing away from the substrate, of the epitaxial structure. The gate electrode extends in a first direction parallel to a plane of the substrate and the gate electrode is in Schottky contact with the epitaxial structure; a gate connecting structure comprising a first gate connecting section and a second gate connecting section connected with each other, wherein the second gate connection section is electrically connected to at least part of the gate electrode. According to the semiconductor device, by providing a gate connecting structure, effect of resistance of a gate may be reduced, thereby increasing switching speed and improving a gain.

The present application relates to the technical field of MOS semiconductor, and discloses a MOSFET structure with gate nanosheet and a manufacturing process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, and the gate comprising a gate cover layer and a gate nanosheet; the gate nanosheet in a single MOS cell has a plurality of gate nanosheets, and the plurality of gate nanosheets are horizontally matrix distributed, and the gate nanosheet extends to the inside of the gate cover layer and directly contacts with the gate cover layer. The present application realizes higher current driving density and better switching characteristics by the three-dimensional embedded contact of the horizontally matrix distributed nanosheet gate and the high-conductivity cover layer, significantly enhances the channel electrostatic control ability, and reduces the gate resistance, thereby breaking through the physical limitation of the traditional planar device.

An object of the present disclosure is to suppress reduction of noise resistance and parasitic oscillation in a semiconductor device. A semiconductor device includes: a plurality of semiconductor chips parallelly connected to each other; a source electrode; a first source pattern connected to the source electrode; a source sensing terminal; and a second source pattern connected to the source sensing terminal, wherein a surface of each of the semiconductor chips is connected to the first source pattern, a surface of a reference chip is connected to the second source pattern, a surface of at least one non-reference chip as the semiconductor chip other than the reference chip is not connected to the second source pattern, and a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

The invention belongs to the technical field of power electronics, and particularly relates to a parallel drive circuit of a silicon carbide power device and a motor drive system.The parallel drive circuit comprises a drive power source, a drive chip, a power switch unit and a plurality of drive shunt units, the current sharing resistor is connected with the auxiliary source electrode of the silicon carbide power device and the common power source electrode node. The problem of current imbalance when a plurality of silicon carbide power devices are used in parallel can be solved, the driving consistency and the system reliability are improved, meanwhile, an overcurrent protection function is provided, and the device is suitable for large-power application scenes such as new energy automobile electric control.

A switching module comprising: a GaN-FET mounted on a substrate; a driver circuit connected to a gate electrode of the GaN-FET via a gate resistor; and a driver power supply for supplying a drive voltage to the driver circuit. The driver circuit is configured such that a plurality of logic integrated circuits are connected in parallel.

The present invention relates to the technical field of SiC power devices, and more specifically, to a multi-layer circuit protection structure for SiC power devices. The structure comprises at least two SiC power devices, each of which is connected in parallel; and a drive circuit, wherein each gate of each SiC power device is connected to a turn-on path and a turn-off path. By improving the drive circuit, the present invention achieves a structure in which the drive circuit differentially adjusts the gate resistance of each device to offset the switching time difference caused by Vgs-th differences, thereby reducing or compensating for the turn-on and turn-off time differences caused by Vgs-th differences, and solving the problem of thermal runaway caused by large Vgs-th differences.

The invention discloses a molten salt energy storage device and method based on nitrate, and the device comprises a plurality of resistors, a plurality of MOS tubes, a plurality of operational amplifiers, a plurality of diodes, a triode, a capacitor, a solid-state relay, a potentiometer, and a counter. The output end of an operational amplifier U7 in the plurality of operational amplifiers is connected with five pins of the potentiometer U2, and the anti-phase end inputs a temperature parameter signal IN1; the in-phase end is connected with eight pins of the potentiometer U2 and one end of the resistor R5; the six pins of the potentiometer U2 are connected with one end of a resistor R16 and the drain electrode of a PMOS tube Q2; the grid electrode of the PMOS transistor Q2 is connected with the output end of the operational amplifier U8, and the source electrode is connected with a power supply and meets the positive voltage requirement; the inverting end of the operational amplifier U8 is connected with a reference signal, and the in-phase end of the operational amplifier U8 is connected with the grid electrode of the NMOS tube Q1, one end of the resistor R4 and the collector electrode of the NMOS tube Q1; a base electrode of the triode U1 is connected with one end of the resistor R6; the drain electrode of the NMOS tube Q1 is connected with the other end of the resistor R6, one end of a resistor R7 and four pins of the solid-state relay U3; the other end of the resistor R7 is connected with one end of the capacitor C1.

This invention discloses a wideband, high-isolation single-pole five-throw switch chip, comprising six ports, two power ports, five control ports, twenty microstrip lines, one capacitor C1, twenty-five switching transistors, twenty-five gate resistors, and five voltage control modules. The six ports are port 1, port 2, port 3, port 4, port 5, and port 6; port 1 is the RF input port; ports 2, 3, 4, 5, and 6 are output ports. The RF input and output ports are connected via the two power ports, five control ports, twenty microstrip lines, one capacitor C1, twenty-five switching transistors, twenty-five gate resistors, and five voltage control modules. Compared to existing single-pole five-throw switches, this invention is integrated on a single chip, offering the advantage of small size. The use of voltage control modules significantly reduces the number of power supply modules, facilitating application.

An IC device design system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs, the storage medium and the code being configured to, with the processor, cause the system to receive an IC device layout diagram including a gate region having a width extending at least from a first edge of an active region to a second edge of the active region and a gate via at a location within the active region and along the width, receive a first gate resistance value corresponding to the gate region, retrieve a second gate resistance value from a resistance value reference based on the location and the width, and based on the second gate resistance value being greater than the first gate resistance value, add a gate terminal node and a resistor to a netlist corresponding to the gate region.

To provide a device capable of reducing gate resistance. [Solution] The semiconductor device includes first to fourth electrodes, a semiconductor layer, a first contact, and a first conductive layer. The second electrode is located above the first electrode. The semiconductor layer is provided between the first electrode and the second electrode. The semiconductor layer includes first to third semiconductor regions. Multiple third electrodes are provided side by side in a cell region. The third electrode faces the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode includes a first extending portion and a wide portion. The fourth electrode faces the second semiconductor region via a second insulating portion. The first contact is located above the fourth electrode and is connected to the wide portion of the fourth electrode. The first conductive layer is located above the fourth electrode and is connected to the fourth electrode by the first contact.

The invention belongs to the technical field of power module control, and discloses a power module control system and control method.A TEC radiator is integrated in a power module, a heat dissipation substrate dissipates heat outwards through the lower surface, meanwhile, the TEC radiator dissipates heat outwards through the upper surface, and the heat dissipation efficiency is improved; more importantly, the MCU module is used for controlling the TEC radiator to be started earlier than each MOS chip, so that a thermal suppression effect is formed at the moment when the MOS chips are started; according to the design, the problem of local high temperature generated when the MOSFET is switched on instantly in the high-frequency switching process in the prior art is effectively solved, and the defect that the high-frequency response capability of the MOSFET is sacrificed due to the fact that the current change rate is reduced by increasing the gate resistance traditionally is overcome.

The utility model discloses a protection circuit of a semiconductor laser diode. The protection circuit comprises an active control loop circuit and a passive current limiting circuit. The active control loop circuit comprises an operational amplifier U1, an operational amplifier U2 and an MOS tube Q1, the in-phase input end of the operational amplifier U1 is connected with a laser diode current setting signal Vcset, the reverse input end of the operational amplifier U1 is connected with the source electrode of the MOS tube Q1, and the output end of the operational amplifier U1 is connected with the grid electrode of the MOS tube Q1. One end of the resistor R1 is connected with the source electrode of the MOS tube Q1, the other end of the resistor R1 is grounded, the non-inverting input end of the operational amplifier U2 is connected with the source electrode of the MOS tube Q1, the inverting input end of the operational amplifier U2 is connected with the output end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected with a current monitoring signal Vcm of the laser diode; whether the current value of the laser diode is abnormal or not is detected through the operational amplifier, active control is achieved, the passive current limiting circuit is additionally arranged, double insurance is formed, and the protection reliability of the laser diode is remarkably improved.

The invention provides a gallium nitride power device. The gallium nitride power device comprises an epitaxial structure, a device layer formed above the epitaxial structure and a first metal layer formed above the device layer, the device layer comprises a plurality of device units, and each device unit comprises a grid electrode strip, a source electrode strip and a drain electrode strip; the first metal layer comprises a plurality of first metal units, and each first metal unit comprises a gate connecting line, a source connecting line and a drain connecting line. According to the embodiment of the invention, the number of the grid connecting lines can be set as required, so that the number of the grid connecting lines and the interval between the grid connecting lines can be adjusted according to the total resistance of the grid electrode. The grid connecting line can shorten the distance entering each grid strip, so that the total resistance of the grid can be set to be a lower value. The total resistance of the grid electrode can be controlled at a small value, so that an active region does not need to be broken, the Gate Bus does not occupy the area of a chip, the effective area of the chip is remarkably increased, and Ron and sp are reduced while Rg is reduced.

Provided is a semiconductor device including: a transistor portion; a current sensing portion which detects a current flowing through the transistor portion; a gate pad which is provided above a semiconductor substrate; and a resistance adjustment portion which is electrically connected to the gate pad and adjusts gate resistances of the transistor portion and the current sensing portion, in which the resistance adjustment portion includes a main adjustment portion which is electrically connected to a gate conductive portion of the transistor portion, and a sense adjustment portion which is electrically connected to a gate conductive portion of the current sensing portion, and each of the main adjustment portion and the sense adjustment portion includes a diode element portion including a plurality of diodes provided in anti-parallel and a resistance portion which is connected to the diode element portion.

Provided is a semiconductor device that makes it possible to suppress loss while controlling a jump-up voltage at turn-off and turn-on under all conditions for an output electric current and a temperature within a use range.　The semiconductor device comprises an IGBT and a driving circuit that drives a gate of the IGBT. The driving circuit includes four MOSFETs and four resistors constituting a bridge circuit, a driver for driving each of the four MOSFETs, an electric current detection circuit for detecting an output electric current of the IGBT, a temperature detection circuit for detecting the temperature of the IGBT, and a determination circuit for controlling driving of the driver on the basis of detection values from the electric current detection circuit and the temperature detection circuit. When the output electric current detected by the electric current detection circuit is greater than a prescribed electric current threshold value, the determination circuit increases an OFF gate resistance of the IGBT. When the temperature detected by the temperature detection circuit is lower than a prescribed temperature threshold value, the determination circuit increases an ON gate resistance of the IGBT.

The invention relates to the technical field of transistor driving, in particular to an adaptive variable resistance transistor driving system, which comprises a data acquisition module; the driving analysis module is used for determining whether grid resistance driving needs to be carried out on the current opening process according to the abnormal reference value, and carrying out staged driving or overall driving on the grid resistance according to the Miller plateau time and the change rate fluctuation value when the grid resistance driving is carried out on the current opening process; the stage division module is used for determining whether to perform secondary division on each stage according to the stage comparison value corresponding to each stage; the stage driving module is used for determining grid resistance adjustment aiming at the characteristic pre-adjustment sections or all the pre-adjustment sections according to the number of the pre-adjustment sections and adjusting the grid resistance according to the abnormal degree of section change; and the integral driving module is used for adjusting the grid resistance according to the turn-on stage characterization value. According to the invention, the conduction loss of the transistor can be reduced.

The present invention provides a semiconductor device capable of reducing gate resistance and a method for manufacturing the same. [Solution] According to the embodiment, the semiconductor device includes first to fourth electrodes, a semiconductor layer, and wiring. The second electrode is located above the first electrode. The semiconductor layer is provided between the first and second electrodes and includes first to third semiconductor regions. A plurality of third electrodes are provided side by side in the cell region where the second electrodes are provided. The third electrodes face the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode faces the second semiconductor region via a second insulating portion. The first insulating layer is provided on top of the semiconductor layer. The wiring is provided in the cell region within the first insulating layer, extends above and along the fourth electrode, is thinner than the fourth electrode, and is electrically connected to the fourth electrode.

The invention discloses a vertical JFET (Junction Field Effect Transistor) power device for enhancing gate end driving capability by ohmic contact and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. In order to solve the problem of poor switching performance caused by high electrical resistivity of a grid active region and serious attenuation of a driving signal in the existing vertical JFET, the invention provides a metal ohmic contact layer (such as nickel) formed on the surface of the grid active region. And the low-resistance metal layer is connected in parallel with the grid electrode P region, and an efficient current path from the grid electrode contact end to each grid junction in the chip is constructed, so that the grid electrode resistance is greatly reduced, and the grid end driving capability is enhanced. According to the manufacturing method, an ohmic contact preparation step in the prior art is utilized, introduction of non-compatible materials such as polycrystalline silicon and complex procedures is not needed, and gate source short circuit is reliably prevented through the design of selectively reserving an insulating layer above a gate region. According to the invention, the switching speed and reliability of the device are improved, and excellent process compatibility and cost advantages are maintained.