366 results about "Gate resistance" patented technology

The invention provides a device for inhibiting drain-source overvoltage and overcurrent through active gate drive of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), aiming at solving the problem of voltage or current overshoot caused by circuit parasitic parameters in a high-speed switching process of the SiC MOSFET and simultaneously considering the switching speed and energy loss balance. According to the device, drain-source voltage vdc and direct-current bus voltage of the SiC MOSFET are collected to serve as feedback signals, and gate driving voltage and equivalent gate resistance are dynamically adjusted; in a key stage (a Miller plateau switching-on period and a voltage rising period switching-off period) of a switch transient state, a gate resistance network is switched through a logic control circuit, and suppression of drain current overshoot and drain-source voltage overshoot is realized. Simulation verification shows that the device can reduce voltage overshoot by 20%-30% and current overshoot by 25%-60%, only a single voltage feedback channel is needed, the cost is obviously lower than that of a traditional multi-signal acquisition active gate driving scheme, and the device is suitable for a high-efficiency SiC MOSFET power converter.

The utility model provides an insulated gate bipolar transistor driving circuit with adjustable positive and negative voltages, comprising a magnetic isolation module, the input end of which is connected with a driving signal and outputs an isolation driving signal; the input end of the first voltage regulating module is connected with the first positive voltage and outputs a second positive voltage within a first preset range; the input end of the second voltage regulating module is connected with the first negative voltage and outputs a second negative voltage within a second preset range; the push-pull output module is connected between the second positive voltage and the second negative voltage, the control end of the push-pull output module is connected with an isolation driving signal, and the output end of the push-pull output module is connected with the gate pole of the to-be-tested insulated gate bipolar transistor through a gate resistor; and the protection module is controllably connected between the output end of the push-pull output module and the second voltage regulation module under the action of the control signal. The driving circuit has the beneficial effects that the positive and negative voltage output capability can be flexibly adjusted according to debugging requirements, the working condition requirements of different clients are met, and the flexibility and adaptability of the driving circuit are improved.

The invention relates to the technical field of semiconductors, in particular to an active current sharing strategy for master-slave cooperative control. According to the technical scheme, the system comprises an S < iC > device dynamic current sampling unit, a dynamic current information conversion unit, a dynamic current information processing unit and a variable grid resistance driving circuit, wherein the S < iC > device dynamic current sampling unit is used for collecting real-time current information of the S < iC > device in the turn-on transient process. The method can effectively solve the problem of current imbalance caused by parameter difference of multi-device parallel connection, is especially suitable for parallel connection of three or more modules, guarantees the current sharing effect through fine active current sharing control, adopts a master-slave cooperative control strategy, solves the problem of single-point fault of a main module in traditional master-slave control, and improves the robustness of the system. The device is prevented from being damaged due to excessive current and voltage stress caused by current imbalance, stable operation of the system is guaranteed, current distribution can be effectively adjusted in the load switching process, and stable operation of the system is guaranteed.

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a radio frequency switch chip, and the circuit structure of the radio frequency switch chip comprises a transformer type differential inductor T-L1, a transformer type differential inductor T-L2, a capacitor C1, an NMOS transistor M1, an NMOS transistor M2, a gate resistor RG1, and a gate resistor RG2. The radio frequency switch chip provided by the invention adopts a differential structure, so that the parasitic inductance effect of a grounding key and a wire during packaging and testing can be eliminated, and the insertion loss and the isolation performance are improved; compared with a single-end port, the lower impedance of the differential port is more beneficial to improving the power capacity of the switch; the differential structure allows the transformer type differential inductor to use differential signal characteristics, the equivalent quality factor of the inductor is improved, and the circuit performance is improved; the differential structure can improve the linearity of the circuit, especially the second-order intermodulation effect; the differential structure can be compatible with a modern silicon-based CMOS radio frequency system, and an additional balun is not needed for signal conversion.

The invention discloses a manufacturing method of a memory device and the memory device, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a substrate and a hard mask layer on the substrate; a plurality of first grooves are formed in the active area of the substrate from the hard mask layer, one part of the first grooves are located in the storage area, the other part of the first grooves are located in the leading-out area, and the parts, in the substrate, of the first grooves are defined as base body grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the groove of the substrate; one part of the semi-floating gate is in contact with the substrate, and the other part of the semi-floating gate is isolated from the substrate through a gate insulating layer; and forming an inter-gate dielectric layer and a first gate layer in the first groove, forming a control gate of the memory unit in the first groove of the memory region, and forming a lead-out wire of the memory unit in the first groove of the lead-out region, namely, enabling the lead-out region to be in contact with the outside, and solving the problem of voltage drop caused by large buried gate resistance.

Disclosed is a device that decouples switching speed and gate delay time using an improved voltage-source gate driver. A shunt capacitor and a shunt resistor are connected in series to parallel across gate resistors of a voltage-source gate driver. The shunt capacitor and shunt resistor allow the gate delay and switching speed effect of the gate resistors to be decoupled. The shunt capacitor provides an initial high charge voltage and discharge gate current to reduce gate delay time. The shunt resistor modifies the effective gate resistance, which affects the gate current and the resulting switching speed. Shunt capacitor and shunt resistor values are determined to achieve the desired switching speed control with minimum gate delay time. When multiple power devices are paralleled, a common gate resistor, a shunt resistor and a capacitor combination is used. Each power device is also provided a respective split-gate resistor.

The invention relates to the technical field of overvoltage control, and particularly discloses an overvoltage control method and device for an IGBT module, and the method comprises the steps: carrying out the time sequence correlation analysis of collector current time sequence data through employing a deep learning algorithm after receiving a turn-off instruction, extracting the short-time fluctuation characteristics of collector current, and obtaining the short-time fluctuation characteristics of the collector current; and the initial gate resistance value is combined to dynamically predict the collector-emitter voltage peak amplitude possibly generated in the turn-off process. And based on comparison between the predicted voltage spike amplitude and a preset threshold value, an initial gate driving strategy is generated to guide the turn-off operation. In the turn-off execution stage, collector-emitter voltage data flow is monitored in real time and dynamically compared with a safety threshold value, and therefore closed-loop optimization adjustment is conducted on a driving strategy. According to the method, prospective evaluation and self-adaptive control of the overvoltage risk are realized through intelligent prediction of the turn-off transient voltage spike, the switching loss can be optimized while the overvoltage is suppressed, and the limitation of traditional fixed parameter control is broken through.

A degradation diagnosis system includes a semiconductor element including a gate, a first main terminal that is a source or an emitter, and a second main terminal that is a drain or a collector. The degradation diagnosis system includes a push-pull circuit, a gate resistance provided in the push-pull circuit or between the push-pull circuit and the gate, and a capacitor coupled in parallel with the gate resistance. The degradation diagnosis system includes a degradation diagnosis device configured to diagnose degradation of the semiconductor element based on a capacitor voltage that is generated across the capacitor.

Embodiments of the present invention advantageously provide a method of manufacturing a semiconductor device having multiple threshold voltage capability in a scaled space between nanosheets in an advanced GAA node. One or more embodiments provide an integration scheme to advantageously reduce gate resistance by incorporating n- / p-dipoles with an intermediate bandgap metal with low resistance to achieve a desired work function and low resistance metal gate. In one or more embodiments, the intermediate bandgap metal is used to fill the nanosheets and as a liner for subsequent filling with the low resistance metal. After dipole processing, instead of filling surrounding gate nanosheets with conventional n or p metals, in one or more embodiments, the nanosheets are advantageously filled with a single work function intermediate energy gap metal to achieve n and p work functions. If the work function is shifted in either of the band edges of the P-dipole or the N-dipole after dipole processing, the intermediate bandgap material may also shift the band edges in the opposite manner.

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

The application discloses a switch tube off negative voltage determination method and device and a switch tube driving control circuit. The switch tube off negative voltage determination method comprises the following steps: determining a first off negative voltage model and a second off negative voltage model; inputting the obtained off gate resistance, on gate resistance, bus voltage and minimum on voltage of the switch tube into the first off negative voltage model to obtain an upper limit absolute value of the off negative voltage of the switch tube; inputting the obtained off gate resistance, on gate resistance, bus voltage and maximum bearable negative voltage absolute value of the switch tube into the second off negative voltage model to obtain a lower limit absolute value of the off negative voltage of the switch tube; and determining the off negative voltage interval of the switch tube according to the upper limit absolute value and the lower limit absolute value. When the off negative voltage interval is used for negative voltage off control of the switch tube, the switch tube can be effectively prevented from being mis-opened, the switch tube can be protected, and the service life of the switch tube is prolonged.

The invention discloses a power device driving circuit of a motor controller, a control method and a vehicle. The power device driving circuit comprises a gate resistance control module which selectively switches gate resistors of a power device according to a control signal, and switching speeds of the power device are different when the gate resistors are switched to different gate resistors; the detection processing circuit collects the phase current of the motor controller, generates a control signal according to the phase current and a preset voltage reference signal, and sends the control signal to the gate resistance control module; and the isolation driving module is used for sending a driving signal to the power device so as to drive the power device to be switched on and switched off at the corresponding switching speed. According to the invention, the method can effectively improve the efficiency of small current output, can effectively protect the peak and oscillation of a power device during large current output, achieves the real-time switching, is higher in response speed, enables the switching operation to be decomposed into each current period, and is more effective for reducing the loss and protecting the device.

The invention discloses a parallel IGBT junction temperature balancing method and system based on thermal resistance and grid resistance compensation, belongs to the technical field of power electronics, and solves the technical problems that in the prior art, when the temperature difference of parallel IGBTs is caused by the thermal resistance parameter mismatching condition, the parameter matching mode is single, a real object needs to be designed for iterative measurement for matching, and the cost is high. According to the method, circuit parasitic parameters and IGBT static parameters are obtained by using ANSYS software simulation and related measurement equipment, a thermal resistance network model and an electrical loss model are coupled to establish a steady-state junction temperature equalization model, and the grid resistance is dynamically adjusted to compensate thermal resistance mismatch, so that the steady-state junction temperature difference of the parallel IGBTs is reduced, and the stability of the parallel IGBTs is improved. The optimal design enabling the steady-state junction temperature difference of the parallel IGBTs to be the minimum is sought through iterative design and calculation, a real object does not need to be designed for iterative measurement matching, time cost and material cost are greatly saved, and the method has the advantages of being clear, easy and convenient to calculate and low in cost.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

The invention relates to the technical field of MOS semiconductors, and discloses a SiCVD MOSFET structure with high-temperature reliability, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, a P well layer I, a heavily doped P layer and an N well layer are arranged in the semiconductor epitaxial layer, a second P-well layer and a first heavily doped N layer are arranged on one side of the N-well layer and close to the grid electrode, and the second P-well layer is located between the N-well layer and the first heavily doped N layer. The section contour of the grid electrode is in a T shape, the first heavily-doped N layer further comprises a third heavily-doped N layer, and the third heavily-doped N layer is in contact with the N drift layer. Through the T-shaped gate structure, heat in a gate region can be more uniformly distributed, the heat is prevented from being concentrated at a certain point, and device faults or degradation caused by local high temperature is reduced; moreover, the T-shaped gate structure can optimize the gate resistance and reduce the current required by gate driving.

The semiconductor drive device includes a third turn-off gate resistor that is electrically connected to the third gate electrode of each of the first semiconductor device and the second semiconductor device, and that is inserted into a third turn-off interconnect configured to apply a potential for turning off the third gate electrode. AndRCGsoff≤Vth⁢3min⁡(CCGsgc)⁢dvdt(1)where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the third gate electrode being Vth3, a resistance value of the third turn-off gate resistor being RCGsoff, a minimum value of a capacitance between the third gate electrode and the collector electrode in a voltage dependence characteristic being min (CCGsgc), and a time displacement of a voltage at a time of turning on being dv / dt.

A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.

The invention relates to a novel semiconductor power device with a built-in gate resistor structure and a preparation method of the novel semiconductor power device. The active region of the semiconductor substrate is provided with a grid electrode electrolyte layer, the grid electrode electrolyte layer is provided with a polycrystalline silicon layer, the polycrystalline silicon layer is provided with first through holes, each first through hole is provided with a temperature coefficient thermistor, the temperature coefficient thermistors extend out of the first through holes, the polycrystalline silicon layer and the temperature coefficient thermistors are provided with interlayer dielectric layers, and the interlayer dielectric layers are arranged between the polycrystalline silicon layer and the temperature coefficient thermistors. The interlayer dielectric layer is provided with a second through hole and a third through hole, the second through hole is filled with a first metal layer, the third through hole is filled with a second metal layer, the interlayer dielectric layer is provided with a grid electrode bonding pad and a grid electrode flow channel, and the grid electrode bonding pad, the grid electrode flow channel and the interlayer dielectric layer are provided with passivation layers. The novel semiconductor power device with the built-in gate resistor structure is designed to solve the technical problem that an existing semiconductor power device with the built-in gate resistor structure is high in loss at a high temperature.

The invention discloses a SiC MOSFET junction temperature on-line acquisition circuit which is connected with a to-be-measured SiC MOSFET for junction temperature acquisition, an independent grid peak current acquisition circuit is additionally arranged, and a low-frequency intermittent sampling strategy is adopted, so that a sampling resistor is in a non-working state in most of time, temperature rise is inhibited, the stability of the resistance value of the sampling resistor is ensured, and the reliability of the sampling resistor is improved. Accuracy of grid peak current acquisition and junction temperature prediction precision are substantially improved. The invention also discloses a SiC MOSFET junction temperature on-line acquisition method. According to the SiC MOSFET junction temperature on-line acquisition circuit and method provided by the invention, the grid resistance network and the grid peak current acquisition circuit are constructed, so that the self-heating problem of the sampling resistor under a high-frequency switch is solved.

A gate driver includes a switching circuit outputting a gate driving voltage to a gate of a semiconductor power switching device (IGBT) via a series gate resistor. The gate driver further includes an external controllable capacitor circuit that is coupled at the gate of the semiconductor power switching device to provide an adjustable external gate capacitance in parallel with a parasitic gate or input capacitance of the IGBT. The capacitor circuit may be controlled by one or more electrical signals to vary the external gate capacitance and thereby the characteristics of a switching operation.

A method and an apparatus for determining a turn-off negative voltage of a switching transistor are provided. The method includes: determining first and second turn-off negative voltage models; inputting acquired turn-off and turn-on gate resistances of the switching transistor, an acquired bus voltage, and an acquired minimum turn-on voltage of the switching transistor into the first model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor; inputting the acquired turn-off and turn-on gate resistances of the switching transistor, the acquired bus voltage, and an acquired maximum bearable negative voltage absolute value of the switching transistor into the second model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor; and determining a turn-off negative voltage interval of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

A semiconductor device includes: a substrate; an epitaxial structure located on a side of the substrate; a gate electrode located on the side, facing away from the substrate, of the epitaxial structure. The gate electrode extends in a first direction parallel to a plane of the substrate and the gate electrode is in Schottky contact with the epitaxial structure; a gate connecting structure comprising a first gate connecting section and a second gate connecting section connected with each other, wherein the second gate connection section is electrically connected to at least part of the gate electrode. According to the semiconductor device, by providing a gate connecting structure, effect of resistance of a gate may be reduced, thereby increasing switching speed and improving a gain.

The invention discloses a shield gate field effect transistor for eliminating voltage clamping and a preparation method thereof, the shield gate field effect transistor comprises a shield gate, a control gate and source electrode metal, the shield gate and the control gate are located in a groove, the shield gate comprises a gate body part and an extension part, the gate body part is located below the control gate, the extension part extends upwards from the gate body part, and the source electrode metal is located in the groove. The extension part is led out from two sides of the control gate to the top of the groove, or the extension part is led out from one side of the control gate to the top of the groove; the top of the extension portion is in direct contact with the source metal by configuring a contact hole structure. Compared with an up-and-down structure of a shield grid and a control grid in a traditional SGT, a whole contact hole can be formed in the top of the extending part of the extended shield grid to be in direct contact with source electrode metal, shield grid resistance is eliminated, shield grid current and voltage are avoided, the voltage clamping problem introduced by shielding is eliminated, and the stability of the SGT is improved. Meanwhile, the charge balance effect and electric field distribution of the whole chip are improved, and current concentration is reduced.

The present application relates to the technical field of MOS semiconductor, and discloses a MOSFET structure with gate nanosheet and a manufacturing process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, and the gate comprising a gate cover layer and a gate nanosheet; the gate nanosheet in a single MOS cell has a plurality of gate nanosheets, and the plurality of gate nanosheets are horizontally matrix distributed, and the gate nanosheet extends to the inside of the gate cover layer and directly contacts with the gate cover layer. The present application realizes higher current driving density and better switching characteristics by the three-dimensional embedded contact of the horizontally matrix distributed nanosheet gate and the high-conductivity cover layer, significantly enhances the channel electrostatic control ability, and reduces the gate resistance, thereby breaking through the physical limitation of the traditional planar device.

An object of the present disclosure is to suppress reduction of noise resistance and parasitic oscillation in a semiconductor device. A semiconductor device includes: a plurality of semiconductor chips parallelly connected to each other; a source electrode; a first source pattern connected to the source electrode; a source sensing terminal; and a second source pattern connected to the source sensing terminal, wherein a surface of each of the semiconductor chips is connected to the first source pattern, a surface of a reference chip is connected to the second source pattern, a surface of at least one non-reference chip as the semiconductor chip other than the reference chip is not connected to the second source pattern, and a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

The invention belongs to the technical field of power electronics, and particularly relates to a parallel drive circuit of a silicon carbide power device and a motor drive system.The parallel drive circuit comprises a drive power source, a drive chip, a power switch unit and a plurality of drive shunt units, the current sharing resistor is connected with the auxiliary source electrode of the silicon carbide power device and the common power source electrode node. The problem of current imbalance when a plurality of silicon carbide power devices are used in parallel can be solved, the driving consistency and the system reliability are improved, meanwhile, an overcurrent protection function is provided, and the device is suitable for large-power application scenes such as new energy automobile electric control.

A switching module comprising: a GaN-FET mounted on a substrate; a driver circuit connected to a gate electrode of the GaN-FET via a gate resistor; and a driver power supply for supplying a drive voltage to the driver circuit. The driver circuit is configured such that a plurality of logic integrated circuits are connected in parallel.