134 results about "Gate resistance" patented technology

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

The application discloses a switch tube off negative voltage determination method and device and a switch tube driving control circuit. The switch tube off negative voltage determination method comprises the following steps: determining a first off negative voltage model and a second off negative voltage model; inputting the obtained off gate resistance, on gate resistance, bus voltage and minimum on voltage of the switch tube into the first off negative voltage model to obtain an upper limit absolute value of the off negative voltage of the switch tube; inputting the obtained off gate resistance, on gate resistance, bus voltage and maximum bearable negative voltage absolute value of the switch tube into the second off negative voltage model to obtain a lower limit absolute value of the off negative voltage of the switch tube; and determining the off negative voltage interval of the switch tube according to the upper limit absolute value and the lower limit absolute value. When the off negative voltage interval is used for negative voltage off control of the switch tube, the switch tube can be effectively prevented from being mis-opened, the switch tube can be protected, and the service life of the switch tube is prolonged.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

The invention relates to a novel semiconductor power device with a built-in gate resistor structure and a preparation method of the novel semiconductor power device. The active region of the semiconductor substrate is provided with a grid electrode electrolyte layer, the grid electrode electrolyte layer is provided with a polycrystalline silicon layer, the polycrystalline silicon layer is provided with first through holes, each first through hole is provided with a temperature coefficient thermistor, the temperature coefficient thermistors extend out of the first through holes, the polycrystalline silicon layer and the temperature coefficient thermistors are provided with interlayer dielectric layers, and the interlayer dielectric layers are arranged between the polycrystalline silicon layer and the temperature coefficient thermistors. The interlayer dielectric layer is provided with a second through hole and a third through hole, the second through hole is filled with a first metal layer, the third through hole is filled with a second metal layer, the interlayer dielectric layer is provided with a grid electrode bonding pad and a grid electrode flow channel, and the grid electrode bonding pad, the grid electrode flow channel and the interlayer dielectric layer are provided with passivation layers. The novel semiconductor power device with the built-in gate resistor structure is designed to solve the technical problem that an existing semiconductor power device with the built-in gate resistor structure is high in loss at a high temperature.

The invention discloses a SiC MOSFET junction temperature on-line acquisition circuit which is connected with a to-be-measured SiC MOSFET for junction temperature acquisition, an independent grid peak current acquisition circuit is additionally arranged, and a low-frequency intermittent sampling strategy is adopted, so that a sampling resistor is in a non-working state in most of time, temperature rise is inhibited, the stability of the resistance value of the sampling resistor is ensured, and the reliability of the sampling resistor is improved. Accuracy of grid peak current acquisition and junction temperature prediction precision are substantially improved. The invention also discloses a SiC MOSFET junction temperature on-line acquisition method. According to the SiC MOSFET junction temperature on-line acquisition circuit and method provided by the invention, the grid resistance network and the grid peak current acquisition circuit are constructed, so that the self-heating problem of the sampling resistor under a high-frequency switch is solved.

A gate driver includes a switching circuit outputting a gate driving voltage to a gate of a semiconductor power switching device (IGBT) via a series gate resistor. The gate driver further includes an external controllable capacitor circuit that is coupled at the gate of the semiconductor power switching device to provide an adjustable external gate capacitance in parallel with a parasitic gate or input capacitance of the IGBT. The capacitor circuit may be controlled by one or more electrical signals to vary the external gate capacitance and thereby the characteristics of a switching operation.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

The present application relates to the technical field of MOS semiconductor, and discloses a MOSFET structure with gate nanosheet and a manufacturing process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, and the gate comprising a gate cover layer and a gate nanosheet; the gate nanosheet in a single MOS cell has a plurality of gate nanosheets, and the plurality of gate nanosheets are horizontally matrix distributed, and the gate nanosheet extends to the inside of the gate cover layer and directly contacts with the gate cover layer. The present application realizes higher current driving density and better switching characteristics by the three-dimensional embedded contact of the horizontally matrix distributed nanosheet gate and the high-conductivity cover layer, significantly enhances the channel electrostatic control ability, and reduces the gate resistance, thereby breaking through the physical limitation of the traditional planar device.

An object of the present disclosure is to suppress reduction of noise resistance and parasitic oscillation in a semiconductor device. A semiconductor device includes: a plurality of semiconductor chips parallelly connected to each other; a source electrode; a first source pattern connected to the source electrode; a source sensing terminal; and a second source pattern connected to the source sensing terminal, wherein a surface of each of the semiconductor chips is connected to the first source pattern, a surface of a reference chip is connected to the second source pattern, a surface of at least one non-reference chip as the semiconductor chip other than the reference chip is not connected to the second source pattern, and a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

The invention belongs to the technical field of power electronics, and particularly relates to a parallel drive circuit of a silicon carbide power device and a motor drive system.The parallel drive circuit comprises a drive power source, a drive chip, a power switch unit and a plurality of drive shunt units, the current sharing resistor is connected with the auxiliary source electrode of the silicon carbide power device and the common power source electrode node. The problem of current imbalance when a plurality of silicon carbide power devices are used in parallel can be solved, the driving consistency and the system reliability are improved, meanwhile, an overcurrent protection function is provided, and the device is suitable for large-power application scenes such as new energy automobile electric control.

This invention discloses a wideband, high-isolation single-pole five-throw switch chip, comprising six ports, two power ports, five control ports, twenty microstrip lines, one capacitor C1, twenty-five switching transistors, twenty-five gate resistors, and five voltage control modules. The six ports are port 1, port 2, port 3, port 4, port 5, and port 6; port 1 is the RF input port; ports 2, 3, 4, 5, and 6 are output ports. The RF input and output ports are connected via the two power ports, five control ports, twenty microstrip lines, one capacitor C1, twenty-five switching transistors, twenty-five gate resistors, and five voltage control modules. Compared to existing single-pole five-throw switches, this invention is integrated on a single chip, offering the advantage of small size. The use of voltage control modules significantly reduces the number of power supply modules, facilitating application.

To provide a device capable of reducing gate resistance. [Solution] The semiconductor device includes first to fourth electrodes, a semiconductor layer, a first contact, and a first conductive layer. The second electrode is located above the first electrode. The semiconductor layer is provided between the first electrode and the second electrode. The semiconductor layer includes first to third semiconductor regions. Multiple third electrodes are provided side by side in a cell region. The third electrode faces the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode includes a first extending portion and a wide portion. The fourth electrode faces the second semiconductor region via a second insulating portion. The first contact is located above the fourth electrode and is connected to the wide portion of the fourth electrode. The first conductive layer is located above the fourth electrode and is connected to the fourth electrode by the first contact.

The invention belongs to the technical field of power module control, and discloses a power module control system and control method.A TEC radiator is integrated in a power module, a heat dissipation substrate dissipates heat outwards through the lower surface, meanwhile, the TEC radiator dissipates heat outwards through the upper surface, and the heat dissipation efficiency is improved; more importantly, the MCU module is used for controlling the TEC radiator to be started earlier than each MOS chip, so that a thermal suppression effect is formed at the moment when the MOS chips are started; according to the design, the problem of local high temperature generated when the MOSFET is switched on instantly in the high-frequency switching process in the prior art is effectively solved, and the defect that the high-frequency response capability of the MOSFET is sacrificed due to the fact that the current change rate is reduced by increasing the gate resistance traditionally is overcome.

The invention provides a gallium nitride power device. The gallium nitride power device comprises an epitaxial structure, a device layer formed above the epitaxial structure and a first metal layer formed above the device layer, the device layer comprises a plurality of device units, and each device unit comprises a grid electrode strip, a source electrode strip and a drain electrode strip; the first metal layer comprises a plurality of first metal units, and each first metal unit comprises a gate connecting line, a source connecting line and a drain connecting line. According to the embodiment of the invention, the number of the grid connecting lines can be set as required, so that the number of the grid connecting lines and the interval between the grid connecting lines can be adjusted according to the total resistance of the grid electrode. The grid connecting line can shorten the distance entering each grid strip, so that the total resistance of the grid can be set to be a lower value. The total resistance of the grid electrode can be controlled at a small value, so that an active region does not need to be broken, the Gate Bus does not occupy the area of a chip, the effective area of the chip is remarkably increased, and Ron and sp are reduced while Rg is reduced.

The present invention provides a semiconductor device capable of reducing gate resistance and a method for manufacturing the same. [Solution] According to the embodiment, the semiconductor device includes first to fourth electrodes, a semiconductor layer, and wiring. The second electrode is located above the first electrode. The semiconductor layer is provided between the first and second electrodes and includes first to third semiconductor regions. A plurality of third electrodes are provided side by side in the cell region where the second electrodes are provided. The third electrodes face the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode faces the second semiconductor region via a second insulating portion. The first insulating layer is provided on top of the semiconductor layer. The wiring is provided in the cell region within the first insulating layer, extends above and along the fourth electrode, is thinner than the fourth electrode, and is electrically connected to the fourth electrode.

The invention discloses a vertical JFET (Junction Field Effect Transistor) power device for enhancing gate end driving capability by ohmic contact and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. In order to solve the problem of poor switching performance caused by high electrical resistivity of a grid active region and serious attenuation of a driving signal in the existing vertical JFET, the invention provides a metal ohmic contact layer (such as nickel) formed on the surface of the grid active region. And the low-resistance metal layer is connected in parallel with the grid electrode P region, and an efficient current path from the grid electrode contact end to each grid junction in the chip is constructed, so that the grid electrode resistance is greatly reduced, and the grid end driving capability is enhanced. According to the manufacturing method, an ohmic contact preparation step in the prior art is utilized, introduction of non-compatible materials such as polycrystalline silicon and complex procedures is not needed, and gate source short circuit is reliably prevented through the design of selectively reserving an insulating layer above a gate region. According to the invention, the switching speed and reliability of the device are improved, and excellent process compatibility and cost advantages are maintained.

The invention relates to a cascaded SiC power device, and relates to the field of semiconductor power devices. According to the technical scheme, through the innovative structure that the first capacitor is arranged between the gate and the drain of the Si MOS tube and the second capacitor is arranged between the gate and the source, the switching speed of the cascaded SiC power device can be accurately regulated and controlled. Specifically, compared with a traditional scheme of increasing switch delay by adjusting grid resistance and introducing extra loss by adding an external RC buffer circuit, the scheme can avoid extra energy loss and realize consideration of performance and energy efficiency while ensuring low switch delay; moreover, the scheme can effectively suppress the undesirable phenomena of voltage overshoot, ringing, electromagnetic interference and the like, remarkably reduces the voltage stress of the power device, improves the working stability of the device, prolongs the service life of the device, and enhances the overall reliability of a power electronic system. In addition, according to the scheme, the implementation mode of switching speed regulation and control is simplified, convenience is provided for designers to carry out device type selection and circuit design, and the design efficiency of a power electronic system is improved.

The invention discloses a series electronic water gauge circuit based on PMOS (P-channel Metal Oxide Semiconductor) tubes. The series electronic water gauge circuit is characterized by comprising a plurality of cascaded water level monitoring sub-circuits which are arranged in series at equal intervals and a voltage division circuit. The water level monitoring sub-circuit cascade arranged in series at equal intervals comprises n stages of sub-circuits, n is greater than 1, and the structures of the sub-circuits of each stage are the same; the first-stage water level monitoring sub-circuit comprises an electronic switch M1, resistors S1 and R1, a monitoring electrode X1 and a water body resistor W1; the electronic switch is a PMOS (P-channel Metal Oxide Semiconductor) tube M1, a monitoring electrode X1 is simultaneously connected with a resistor R1 and a grid electrode of the PMOS tube M1, the other end of the resistor R1 is connected with a power supply VCC and a source electrode of the PMOS tube M1, one end of the resistor S1 is connected with a drain electrode of the PMOS tube M1, and the other end of the resistor S1 is connected to the voltage division circuit S0 to output a water level monitoring signal Vo. Compared with the prior art, the series type electronic water gauge circuit based on the PMOS tubes has the advantages that the electronic water gauge circuit based on the PMOS tubes is provided, and the electronic water gauge circuit of high-speed collection of a simple combination logic circuit is provided.

The present application relates to the technical fields of dynamic reverse bias test, and relates to a circuit and a method for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, the circuit comprises a circuit for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, including a gate resistor, a half-bridge topology circuit, a Schottky barrier diode, a differential amplifier and a direct current power supply, the half-bridge topology circuit comprises an upper bridge auxiliary measurement silicon carbide power device, a lower bridge measured sample and a lower bridge sampling resistor, the gate of the auxiliary measurement silicon carbide power device and the gate of the measured sample are respectively connected with a gate drive input signal through the gate resistor; a plurality of Schottky barrier diodes are connected in parallel with the lower bridge sampling resistor to form an active low-pass filter, the non-inverting input and the inverting input of the differential amplifier are respectively connected with the anode and the cathode of the Schottky barrier diode; the present application can effectively filter out current spikes, solve the problem of related high dV / dt current spikes, and ensure the high precision of the leakage current monitoring signal.

A radio frequency (RF) device is described. The RF device includes a switch field effect transistor (FET) having a source region, a drain region, a body region, and a gate region. The RF device also includes a dynamic bias control circuit. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor and to the gate region of the switch FET by the gate resistor.

This invention provides an electromagnetic noise analysis apparatus and method that achieves both reduced analysis time and improved analysis accuracy. [Solution] The electromagnetic noise analysis device 1 includes: a noise spectrum analysis unit that performs frequency-axis noise analysis on any observation point of a power conversion circuit in which at least two switches are connected between power supplies, representing each switch as a voltage source or current source on the frequency axis; a voltage source / current source noise source parameter generation unit that generates a parameter table for representing switching operation as a voltage source or current source on the frequency axis according to operating conditions including power supply voltage, gate resistance of each switch, or current; a worst-case condition extraction unit that extracts phase relationships and current amounts in which the noise amount can become the worst-case condition in the time-axis operation of each switch based on control; and a worst-case condition noise source model generation unit that sets the worst-case condition noise source parameters using the extraction results by the worst-case condition extraction unit.

The invention provides an intelligent driving management method, system and device for a power electronic converter, and the method comprises the steps: receiving a control instruction, and generating a PWM modulation strategy matched with the topology of the converter based on a preset multi-topology PWM modulation algorithm library; electric heating parameters of the power device are collected, and the junction temperature of the power device is calculated based on a preset junction temperature model; based on the PWM modulation strategy and the life loss model, iteratively adjusting the gate resistance, and outputting the optimal gate resistance; generating a PWM driving signal and predicting the service life of the converter based on the optimal gate resistance, the PWM modulation strategy and the junction temperature; according to the method and the device, direct calling can be realized, the cross-platform transplantation cost is reduced, the modulation and control of the life constraint of each power device are realized, the whole life cycle cost of each power device is reduced, and the balance between the total power loss minimization and the safety maximization is realized.

Provided is an active control in which the setting of the resistance value of a resistor connected in series with a control terminal is easier. A driving device (10) for a switching element is provided with a driver (11), a gate resistor (R1), and a resistor (R2). The driver (11) generates a drive signal (S2) that changes between a low level and a high level and is generated on the basis of the control signal (S1), and outputs the drive signal (S2) from the output terminal (To) to the gate (G) of the switching element (Q2), thereby switching the switching element (Q2) between energization and de-energization. A gate resistor (R1) connects an output terminal (To) to a gate (G). The resistor (R2) connects the gate (G) and the source (S). A driving device (10) for a switching element performs active control by bringing a driver (11) into a high impedance state during a transition period of a switching operation of a switching element (Q2). The high impedance state is a state in which the drive signal (S2) is not input to the gate (G).

The utility model belongs to the technical field of detection circuits, and discloses a battery voltage detection circuit, which comprises a port MCU control, the port MCU control is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a resistor R2 and a base electrode of a triode Q1, the other end of the resistor R2 is connected with a port GND, an emitter electrode of the triode Q1 is connected with the port GND, a collector electrode of the triode Q1 is connected with one end of a resistor R4, and the other end of the resistor R4 is connected with the base electrode of the triode Q1. The other end of the resistor R4 is connected with one end of the resistor R3 and the grid electrode of the MOS tube Q2, the other end of the resistor R3 is connected with the source electrode of the Q2 and the port VBAT, the drain electrode of the Q2 is connected with one end of the resistor R5, the other end of the R5 is connected with one end of the R6, one end of the C1 and the port ADC, and the other end of the R6 is connected with the other end of the C1 and the port GND. The battery voltage detection circuit has the beneficial effects that the on-off of the PMOS tube is accurately controlled through the triode, the accurate detection of the battery voltage is realized, and the extremely low static power consumption is kept at the same time.

The invention discloses a power semiconductor device with an external gate resistor, and relates to the field of semiconductor devices, the power semiconductor device with the external gate resistor comprises a semiconductor substrate, and a gate bus, a first gate connection region and a second gate connection region which are arranged on the front surface of the semiconductor substrate, the second gate connection region is electrically connected with a gate bus; and providing an external gate resistor, one end of the external gate resistor being electrically connected with the first gate connection region, and the other end of the external gate resistor being electrically connected with the second gate connection region. Through the structural design, the external chip resistor is used for replacing a traditional grid built-in resistor RGint made of polycrystalline silicon, the repeated tape-out verification period caused by the improper built-in resistor can be avoided, meanwhile, due to the flexibility of the external chip resistor, the grid resistance value requirements of different application scenes can be met, and the effects of reducing cost and increasing efficiency are achieved.

A method for measuring degradation of a thermal resistance between a power semiconductor and a heat sink of a power module assembly where the power semiconductor has an internal gate resistance, including measuring a first initial parameter related to the power semiconductor junction temperature, and heating the internal gate resistance and measuring a second initial parameter, related to the junction temperature after the heating, after discrete time intervals during the lifetime of the power module assembly measuring a first subsequent parameter related to the power semiconductor junction temperature heating the internal gate resistance and measuring a second subsequent parameter, related to the junction temperature after the heating, and calculating a thermal resistance degradation, ΔRTh with the subsequent parameters related to junction temperature and the initial parameters and raising a fault flag in case ΔRTh is above a limit value.

The invention discloses a super junction device. Gate unit structures of device unit structures in an active region form a two-dimensional mesh gate structure. The two-dimensional mesh gate structure comprises a plurality of first gate strips which extend in a first direction and are arranged in parallel, a plurality of second gate segments and grid regions located among the second gate segments are formed in first gate spacer regions among the first gate strips, and a forming region of each device unit structure comprises a corresponding grid region; and each second grid section is also connected with the first grid strips on the two sides, and grid connection nodes are formed at the connection positions. In the first direction and the second direction which are perpendicular to each other, the strip-shaped first grid electrode and the second grid electrode section on the outermost side extend into the transition area, corresponding grid leading-out structures are formed in the transition area, and the grid leading-out structures are connected to the grid electrode composed of the front face metal layer. The gate resistance can be reduced, signal synchronization can be realized, the effective area of the active region can be increased, and the power density can be improved.

A reference current generator includes two transistors, a resistor and a mirroring circuit. The first transistor includes a source receiving a supply voltage, a drain connected with a first node, and a gate connected with a second node. The second transistor includes a source receiving the supply voltage, and a drain and a gate connected with a third node. The resistor is connected between the second node and the third node. The mirroring circuit includes an input terminal receiving an input current, a first mirrored terminal connected with the second node and a second mirrored terminal connected with the first node. The first mirrored terminal and the second mirrored terminal generate a first mirroring current and a second mirroring current respectively. The first transistor generates a saturation current. A reference current is equal to the saturation current minus the second mirroring current.

The utility model provides an MOSFET layout and an MOSFET device. A first resistance adjusting region is arranged at the junction of a first source electrode metal region and a source electrode metal connecting region; and a second resistance adjusting region is arranged at the junction of the second source electrode metal region and the source electrode metal connecting region. According to the invention, through layout adjustment, a resistance adjusting area is added in a fixed area, and a series loop of a source-grid resistor and a source-drain capacitor is formed to absorb Vds oscillation voltage caused by reverse recovery of an MOSFET body diode.

The present invention provides a semiconductor device that can avoid the effects of variations in the gate resistance of multiple gate structures without incurring losses. [Solution] The semiconductor device 1 includes a chip 2 having a first main surface 3 including an active region 6, an n-type drift region 9 formed on the chip 2, a p-type body region 41 formed on the surface of the drift region 9, an n-type source region 42 formed on the surface of the body region 41, a plurality of gate structures 45 formed opposite the body region 41 and forming channels in the body region 41, an interlayer film 13 covering the plurality of gate structures 45, gate wiring 25 formed on the interlayer film 13, and a plurality of resistive film portions 81 embedded in the interlayer film 13. The resistive film portions 81 are connected to both the gate structures 45 and the gate wiring 25.