15results about How to "Improve interconnect density" patented technology

The invention provides an integrated structure of a hybrid heterogeneous integrated circuit and a preparation method thereof, and the method comprises the steps: S1, preparing a GaN HEMT device which comprises a first substrate, a buffer layer, a GaN channel, a first grid electrode, a first source electrode, a first drain electrode and a barrier layer; s2, preparing a SiC JFET device, wherein the SiC JFET device comprises a second substrate, a SiC channel, an n-EPI layer, a second source electrode and a second drain electrode; s3, the first drain electrode and the first source electrode of the GaN HEMT device are correspondingly connected with the second drain electrode and the second source electrode of the SiC JFET device in a bonding mode, and the integrated structure of the hybrid heterogeneous integrated circuit is obtained. According to the invention, the pitch is reduced, and the connection density of the integrated circuit is improved.

The invention provides a hybrid bonding structure and bonding method based on an interlocking structure, and the structure comprises a first chip to be bonded, which is provided with a silicon oxide layer and a first connecting piece protruding out of the silicon oxide layer; the second chip to be bonded is provided with a polyimide layer, a recess arranged in the polyimide layer and a second connecting piece arranged at the bottom of the recess, the surface of the second connecting piece is provided with a first adhesion layer, and the first connecting piece and the second connecting piece are made of copper and / or aluminum; the first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first connecting piece protruding out of the oxide layer is greater than the height difference of the top surface of the first adhesion layer and the top surface of the silicon oxide layer; the silicon oxide layer is connected with the polyimide layer, and the first connecting piece extends into the recess and is connected with the second connecting piece through the first adhesion layer to form an interlocking structure. The method is used for optimizing the performance of the hybrid bonding process and the bonding structure.

The invention discloses a longitudinal electric connecting piece based on a printed circuit board. The longitudinal electric connecting piece comprises a layered insulation structure and a metal connecting piece arranged in the layered insulation structure. At least one end of the metal connecting piece is provided with an easy-to-deform part exposed out of the layered insulation structure, and the easy-to-deform part is exposed out by etching the layered insulation structure on the printed circuit board. On the other hand, the invention discloses application of the longitudinal electric connecting piece based on the printed circuit board. The longitudinal electric connecting piece is applied to a power module. When the structure is assembled to a power module and the like, press fit and leveling of an assembly structure are facilitated, and the flatness of an assembly body can be effectively improved; in addition, the welding area can be effectively increased, a welding exhaust channel is provided, a welding spot crack propagation path is blocked and the like, the connection reliability can be effectively improved, and due to the existence of the easily-deformed part, the service reliability in severe environments such as high vibration and high temperature change range can be improved.

The invention discloses a longitudinal electric connecting piece based on a printed circuit board. The longitudinal electric connecting piece comprises a layered insulation structure and a layered metal connecting piece arranged in the layered insulation structure. At least one end of the layered metal connecting piece is provided with an end bonding pad exposed out of the layered insulating structure, and the surface of the end bonding pad is in a wave shape. On the other hand, the invention discloses application of the longitudinal electric connecting piece based on the printed circuit board. The longitudinal electric connecting piece is applied to a power module. According to the invention, the width, spacing and the like of the end pads can be greatly reduced, the number of fan-out pins is effectively increased, the interconnection density is improved, the welding area can be effectively increased, a welding exhaust channel is provided, a welding spot crack propagation path is blocked and the like, and the connection reliability can be effectively improved.

A packaging structure and a manufacturing method thereof, the packaging structure comprising: a first substrate, a second substrate, a first chip, a second chip, a heat sink and an inter-board connecting structure, wherein the second substrate has a first opening window penetrating through upper and lower surfaces of the second substrate; the first chip is attached to an upper surface of the first substrate, and the first chip is electrically connected to the first substrate; the second substrate is attached to the upper surface of the first substrate, the inter-board connecting structure is located between the lower surface of the second substrate and the upper surface of the first substrate, the second substrate is electrically connected to the first substrate through the inter-board connecting structure, and the first opening window in the second substrate exposes at least part of a back surface of the first chip; the second chip is attached to an upper surface of the second substrate; and the heat sink is attached to the back surface of the first chip through the first opening window. Heat dissipation of the first chip located in the lower layer of the packaging structure is improved.

This invention provides a hybrid bonding structure and bonding method based on an interlocking structure. The hybrid bonding structure includes: a first chip to be bonded, having a silicon oxide layer and a first connector protruding from the silicon oxide layer; and a second chip to be bonded, having a polyimide layer, a recess within the polyimide layer, and a second connector at the bottom of the recess. The surface of the second connector is provided with a first adhesive layer. The materials of the first and second connectors include copper and / or aluminum. The first and second chips to be bonded are configured such that: before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer and the polyimide layer are connected, and the first connector extends into the recess and is connected to the second connector using the first adhesive layer, thus forming an interlocking structure. This invention is used to optimize the performance of the hybrid bonding process and bonding structure.

The invention discloses a semiconductor device and a preparation method thereof, a chip and an electronic device, the semiconductor device comprises a first DRAM layer and a second DRAM layer which are adjacent to each other, the first DRAM layer comprises a first substrate layer, a first back bonding layer and a first DRAM unit layer, a first substrate interconnection structure is formed in the first substrate layer, and a second substrate interconnection structure is formed in the second substrate layer; the first back bonding layer comprises a first back bonding dielectric layer and a first back interconnection structure, and the first back interconnection structure comprises a first back bonding conductive layer; the second DRAM layer comprises a second substrate layer, a second DRAM unit layer and a second front bonding layer, the second front bonding layer comprises a second front bonding dielectric layer and a second front interconnection structure, and the second front interconnection structure comprises a second front bonding conductive layer; and the first back bonding dielectric layer is connected with the second front bonding dielectric layer, and the first back bonding conductive layer is connected with the second front bonding conductive layer, so that mixed bonding from the front side to the back side is adopted among a plurality of DRAM layers, and the interconnection density of the chip is improved.

The invention discloses a gold bump preparation method for thermal ultrasonic spherical gold wire bonding, a flip-chip bonding structure and a chip, and relates to the field of chips. According to the mass fraction, the method comprises the following steps that a plurality of gold protruding points are formed on a flip-chip bonding pad through hot ultrasonic spherical gold wire bonding, and the width of the flip-chip bonding pad is larger than or equal to 150 micrometers. A plurality of gold bumps are formed through thermal ultrasonic spherical gold wire bonding, so that the plurality of gold bumps can support a flip-chip bonding pad with the width greater than or equal to 150 [mu] m for a large-size chip. Based on the specific requirements of gold wires with different diameters and the sizes of the bonding pads, combined preparation of various gold bumps is performed, the contact area of the bonding pads on the flip chip and the bonding pads on the substrate is increased, electrical signal interconnection between the bonding pads is completed, the gold bump process replaces micro gold bumps and copper columns which are high in cost and complex in process, the cost can be reduced, and the production efficiency is improved. The efficiency is improved.

The invention relates to the technical field of chip packaging, in particular to a chip stacking packaging structure adopting flexible RDL and a packaging method. Comprising one or more chip sets, each chip set comprises a flexible RDL, a first chip, a second chip and first bumps, dielectric layers and first metal layers are arranged in the flexible RDL, the dielectric layers are provided with oppositely arranged side faces, the first metal layers are located on the oppositely arranged side faces, and the oppositely arranged first metal layers are connected with the first chip and the second chip through the first bumps respectively. The surface, connected with the outside, of the dielectric layer is provided with a second metal layer, and the dielectric layer is connected with other chip sets or second salient points through the second metal layer. Compared with the prior art, the cost is low, the interconnection density is high, the productivity is greatly improved, and the total thickness after final bending and stacking is greatly reduced. And the bending and stacking adopt a hot pressing mode, so that the molding compound is cured and adhered again, the glue film adhesion between the chips is replaced, and the production cost is reduced.

The utility model provides a radio frequency module comprising a middle plastic package structure, the middle plastic package structure comprises a first electronic component, and the first electronic component comprises a filter chip and a non-filter chip or / and a passive component; the first plastic packaging layer at least covers the back surface and the side wall of the first electronic component; the retaining walls are positioned on two sides of the front surface of the filter chip; the isolation layer covers the retaining wall and forms a cavity with the retaining wall and the front surface of the filter chip; the isolation layer also covers at least part of the front surface of the non-filter chip or / and the passive element; the at least one rewiring layer comprises a plurality of metal circuit layers and a dielectric layer for isolating the plurality of metal circuit layers, and the metal circuit layers are electrically connected with the front surface of the first electronic element; and the first bonding pad is electrically connected with the metal circuit layer. According to the utility model, at least one rewiring layer is adopted to replace a traditional substrate to provide interconnection, so that the interconnection density is greatly improved while the thickness is reduced.

This invention discloses a 2P2M wafer-level packaging structure based on a PI insulating layer, relating to the field of semiconductor technology. It includes a wafer substrate layer, the top surface of which is coated with a first polyimide insulating layer. A first UBM layer is formed on the top of the first polyimide insulating layer via physical vapor deposition. A first metal interconnect layer is formed on the top of the first UBM layer via electroplating. A second polyimide insulating layer is coated on the top surface of the first metal interconnect layer. A second UBM layer is formed on the top of the second polyimide insulating layer via physical vapor deposition. This invention, by employing a specially formulated photosensitive PI material, optimized interface processing technology, and an innovative stepped curing method, effectively solves the stress management and reliability problems of multilayer structures while increasing interconnect density. This technology is particularly suitable for advanced packaging applications requiring high I / O density, excellent high-frequency performance, and long-term thermal stability.

The invention provides a three-dimensional chip packaging structure and a manufacturing method, and relates to the technical field of integrated circuit manufacturing. Comprising a substrate; the chip stacking structure at least comprises a first chip, a second chip and a third chip, the second chip is located between the first chip and the third chip and is in the direction parallel to the substrate, the size of the second chip is smaller than that of the first chip and that of the third chip, and therefore a containing space is formed between the first chip and the third chip; at least one adapter plate, wherein interconnection wires are arranged in the adapter plate; the adapter plate is provided with at least two end parts, and one end part is arranged on the substrate and is electrically connected with the substrate; and the other end part at least partially extends into an accommodating space formed between the first chip and the third chip and is electrically connected with the first chip and / or the third chip. According to the invention, the power supply integrity and the signal integrity are obviously optimized, the surface space of the substrate is saved, and the integration level of the system is improved.

This invention discloses a small-size BGA SSD packaging structure and method based on TMV and vertical wire bonding. The invention relates to the field of semiconductor packaging technology and includes: a substrate; an RDL layer disposed parallel above the substrate, the distance between the RDL layer and the substrate not exceeding a first predetermined distance; multiple chips stacked alternately on the substrate, with gold wires soldered to the chips perpendicularly upwards to the RDL layer; and a first component with its pads facing upwards on the substrate, the pads connected to the RDL layer via vertically upward-facing copper pillars. This invention ensures that the gold wires are perpendicular to the substrate or chips, avoiding the problems of uneven or interlaced wire bonding caused by safety distances. Furthermore, the use of TMV technology allows multiple components to be stacked, contributing to higher packaging density and further reducing package size.

The present disclosure provides a semiconductor device and a manufacturing method thereof, a packaging device and an electronic device. The semiconductor device includes an interposer and a plurality of chips, wherein the second surface of the chip is coupled to the first surface of the interposer through a connection structure; wherein the interposer is used to realize the interconnection of the plurality of chips; the connection structure includes a first dielectric layer formed on the first surface of the interposer and a first conductive pin formed on the first surface of the interposer and exposed from the first dielectric layer, and also includes a second dielectric layer formed on the second surface of the chip and a second conductive pin formed on the second surface of the chip and exposed from the second dielectric layer; and between the first dielectric layer and the second dielectric layer and between the first conductive pin and the second conductive pin, the respective van der Waals force-dependent bonding is realized through an annealing process after the first dielectric layer and the second dielectric layer are pre-bonded. The present disclosure realizes the connection between the chip and the interposer through a new connection structure, and the interconnection density per unit area of ​​the chip is increased.

The invention provides a three-dimensional packaging structure which is characterized in that the packaging structure comprises a plurality of single-layer chips which are vertically stacked and interconnected with one another; the plastic packaging material is used for carrying out coating and plastic packaging on the plurality of single-layer chips; the underfill material is filled in a connection gap between the adjacent chip layers; the single-layer chip comprises a plurality of TSV interconnection structures which comprise TSV silicon through holes and copper columns; the main chip comprises an I / O surface and a back surface opposite to the I / O surface; and a plastic packaging layer, wherein the main chip and the TSV interconnection structure are coated with the plastic packaging layer. The invention further provides a three-dimensional structure packaging method, compared with a traditional WB packaging mode, a substrate is omitted, and the packaging thickness is reduced; through the TSV silicon bridge, vertical stacking between the chips is realized. Through the RDL, I / O re-surface distribution is realized, the interconnection density is greatly improved, the interconnection distance is shortened, and the performance is better.