6results about How to "Improve interconnect density" patented technology

A packaging structure and a manufacturing method thereof, the packaging structure comprising: a first substrate, a second substrate, a first chip, a second chip, a heat sink and an inter-board connecting structure, wherein the second substrate has a first opening window penetrating through upper and lower surfaces of the second substrate; the first chip is attached to an upper surface of the first substrate, and the first chip is electrically connected to the first substrate; the second substrate is attached to the upper surface of the first substrate, the inter-board connecting structure is located between the lower surface of the second substrate and the upper surface of the first substrate, the second substrate is electrically connected to the first substrate through the inter-board connecting structure, and the first opening window in the second substrate exposes at least part of a back surface of the first chip; the second chip is attached to an upper surface of the second substrate; and the heat sink is attached to the back surface of the first chip through the first opening window. Heat dissipation of the first chip located in the lower layer of the packaging structure is improved.

This invention provides a hybrid bonding structure and bonding method based on an interlocking structure. The hybrid bonding structure includes: a first chip to be bonded, having a silicon oxide layer and a first connector protruding from the silicon oxide layer; and a second chip to be bonded, having a polyimide layer, a recess within the polyimide layer, and a second connector at the bottom of the recess. The surface of the second connector is provided with a first adhesive layer. The materials of the first and second connectors include copper and / or aluminum. The first and second chips to be bonded are configured such that: before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer and the polyimide layer are connected, and the first connector extends into the recess and is connected to the second connector using the first adhesive layer, thus forming an interlocking structure. This invention is used to optimize the performance of the hybrid bonding process and bonding structure.

The invention discloses a semiconductor device and a preparation method thereof, a chip and an electronic device, the semiconductor device comprises a first DRAM layer and a second DRAM layer which are adjacent to each other, the first DRAM layer comprises a first substrate layer, a first back bonding layer and a first DRAM unit layer, a first substrate interconnection structure is formed in the first substrate layer, and a second substrate interconnection structure is formed in the second substrate layer; the first back bonding layer comprises a first back bonding dielectric layer and a first back interconnection structure, and the first back interconnection structure comprises a first back bonding conductive layer; the second DRAM layer comprises a second substrate layer, a second DRAM unit layer and a second front bonding layer, the second front bonding layer comprises a second front bonding dielectric layer and a second front interconnection structure, and the second front interconnection structure comprises a second front bonding conductive layer; and the first back bonding dielectric layer is connected with the second front bonding dielectric layer, and the first back bonding conductive layer is connected with the second front bonding conductive layer, so that mixed bonding from the front side to the back side is adopted among a plurality of DRAM layers, and the interconnection density of the chip is improved.

This invention discloses a 2P2M wafer-level packaging structure based on a PI insulating layer, relating to the field of semiconductor technology. It includes a wafer substrate layer, the top surface of which is coated with a first polyimide insulating layer. A first UBM layer is formed on the top of the first polyimide insulating layer via physical vapor deposition. A first metal interconnect layer is formed on the top of the first UBM layer via electroplating. A second polyimide insulating layer is coated on the top surface of the first metal interconnect layer. A second UBM layer is formed on the top of the second polyimide insulating layer via physical vapor deposition. This invention, by employing a specially formulated photosensitive PI material, optimized interface processing technology, and an innovative stepped curing method, effectively solves the stress management and reliability problems of multilayer structures while increasing interconnect density. This technology is particularly suitable for advanced packaging applications requiring high I / O density, excellent high-frequency performance, and long-term thermal stability.

The invention provides a three-dimensional chip packaging structure and a manufacturing method, and relates to the technical field of integrated circuit manufacturing. Comprising a substrate; the chip stacking structure at least comprises a first chip, a second chip and a third chip, the second chip is located between the first chip and the third chip and is in the direction parallel to the substrate, the size of the second chip is smaller than that of the first chip and that of the third chip, and therefore a containing space is formed between the first chip and the third chip; at least one adapter plate, wherein interconnection wires are arranged in the adapter plate; the adapter plate is provided with at least two end parts, and one end part is arranged on the substrate and is electrically connected with the substrate; and the other end part at least partially extends into an accommodating space formed between the first chip and the third chip and is electrically connected with the first chip and / or the third chip. According to the invention, the power supply integrity and the signal integrity are obviously optimized, the surface space of the substrate is saved, and the integration level of the system is improved.

This invention discloses a small-size BGA SSD packaging structure and method based on TMV and vertical wire bonding. The invention relates to the field of semiconductor packaging technology and includes: a substrate; an RDL layer disposed parallel above the substrate, the distance between the RDL layer and the substrate not exceeding a first predetermined distance; multiple chips stacked alternately on the substrate, with gold wires soldered to the chips perpendicularly upwards to the RDL layer; and a first component with its pads facing upwards on the substrate, the pads connected to the RDL layer via vertically upward-facing copper pillars. This invention ensures that the gold wires are perpendicular to the substrate or chips, avoiding the problems of uneven or interlaced wire bonding caused by safety distances. Furthermore, the use of TMV technology allows multiple components to be stacked, contributing to higher packaging density and further reducing package size.