80results about How to "Improve interconnect density" patented technology

A backplane connector including a substrate and a backplane connector set attached to the substrate. The backplane connector set includes a plurality of interconnect elements each having a conductive trace, a first contact member, and a second contact members matched to the first contact member. The first and second contact members extend beyond perimeter edges of the substrate. A plurality of conductive tie bars retain the interconnect elements in a fixed relationship prior to attachment to the substrate. Additive printing processes can be used to form the conductive traces.

Data center network architectures, systems, and methods that can reduce the cost and complexity of data center networks. Such data center network architectures, systems, and methods employ physical optical ring network and multi-dimensional network topologies and optical nodes to efficiently allocate bandwidth within the data center networks, while reducing the physical interconnectivity requirements of the data center networks. The respective optical nodes can be configured to provide various switching topologies, including, but not limited to, chordal ring switching topologies and multi-dimensional chordal ring switching topologies.

An integrated circuit substrate having laser-exposed terminals provides a high-density and low cost mounting and interconnect structure for integrated circuits. The laser-exposed terminals can further provide a selective plating feature by using a dielectric layer of the substrate to prevent plating terminal conductors and subsequently exposing the terminals via laser ablation. A metal layer may be coated on one or both sides with a dielectric material, conductive material embedded within the dielectric to form conductive interconnects and then coating over the conductive material with a conformal protective coating. The protectant is then laser-ablated to expose the terminals. A dielectric film having a metal layer laminated on one side may be etched and plated. Terminals are then laser-exposed from the back side of the metal layer exposing unplated terminals.

A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.

A multilayer circuit includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by electroplating techniques. Substrates formed in this manner enable significant increases in circuit pattern miniaturization, circuit pattern reliability, interconnect density and significant reduction of over-all substrate thickness.

A method for making an integrated circuit substrate having laminated laser-embedded circuit layers provides a multi-layer high-density mounting and interconnect structure for integrated circuits. A prepared substrate, which may be a rigid double-sided dielectric or film dielectric with conductive patterns plated, etched or printed on one or both sides is laminated with a thin-film dielectric on one or both sides. The thin-film is laser-ablated to form channels and via apertures and conductive material is plated or paste screened into the channels and apertures, forming a conductive interconnect pattern that is isolated by the channel sides and vias through to the conductive patterns on the prepared substrate. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.

The invention discloses an optical fiber coupling module and relates to an optical component in an active optical cable. An active optical cable in the prior art has defects such as large module size, a limited number of transmitting and receiving ports, complex process and the like. According to the optical fiber coupling module, a 45-degree oblique end surface optical fiber array is coupled to a laser array; a flat end surface optical fiber array is coupled to an optical detector through a right-angle prism and a micro lens array; and a transmitting assembly and a receiving assembly are integrated in one module. The optical fiber coupling module has the advantages of compact structure, high density interconnect and simple process.

A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate.

The invention relates to a wafer-level chip size encapsulation technology for a GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor. The technology is characterized by comprising the following steps of: (1) firstly bonding a glass wafer and a GaAs wafer through a resin adhesive so as to protect the active surface of a chip and improve the strength of a chip wafer; (2) manufacturing a trapezoidal-slot structure by a wet corrosion or physical method so as to reduce the lining thickness of a chip interconnection area; (3) manufacturing vertical interconnected through holes by a dry etching technology so as to expose a pad on the active surface of the chip; (4) sputtering seed-layer metal and electroplating, and manufacturing a hole metalizing and RDL layer to realize circuit interconnection from the active surface to the back surface of the chip; (5) manufacturing a passivation layer, a UBM layer and raised points; and (6) finally scribing to form an independent encapsulation chip. As the trapezoidal-slot structure on the back realizes thickness reduction only in the area with the pad, the cost is effectively lowered; and through the interconnection of the vertical through holes, the encapsulation interconnection density can be improved, and the signal transmission path is shortened.

The invention provides a wafer level packaging method and packaging structure for an image sensor. The packaging method comprises the steps that a first passivation layer is formed on the active face of a sensing wafer; at least one metal fan-out electrode is deposited on the first passivation layer; the active face of the sensing wafer and a transparent substrate are bonded; a second passivation layer is deposited on the back face of the sensing wafer, and a grooving mark is carved on the second passivation layer; grooves are formed in the grooving mark; a third passivation layer is manufactured on the back face of the sensing wafer; through holes penetrating through the metal fan-out electrodes are formed in the bottoms of the grooves; metal interconnecting wires are manufactured to guide the metal fan-out electrodes out to the back face of the third passivation layer through the through holes; a fourth passivation layer completely covering the metal interconnecting wires is manufactured; an opening is etched in the fourth passivation layer to expose one ends of the metal interconnecting wires; a UBM layer and soldering tin protrusions are manufactured on the fourth passivation layer. The wafer level packaging method and packaging structure are high in reliability, low in cost, small in signal delay and high in interconnecting density.

Disclosed is an electroless plating solution exhibiting a good plating metal filling performance even for larger trenches or vias of several to one hundred and tens of μm, in a manner free from voids or seams, and allowing maintenance of stabilized performance for prolonged time.

The electroless plating solution contains at least a water-soluble metal salt, a reducing agent for reducing metal ions derived from the water-soluble metal salt, and a chelating agent. In addition, the electroless plating solution contains a sulfur-based organic compound as a leveler having at least one aliphatic cyclic group or aromatic cyclic group to which may be linked at least one optional substituent. The aliphatic cyclic group or the aromatic cyclic group contains optional numbers of carbon atoms, oxygen atoms, phosphorus atoms, sulfur atoms and nitrogen atoms.

A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.

The invention relates to a packaging technology of a power converter, in which all components are electrically connected to a multilayer circuit board. A subpackage having at least one power dissipating chip with an exposed upward facing top thermal block electrically connected to the board by a plurality of symmetrical pins. A heat spreading element is directly attached to the exposed top thermal block of the subpackage, the top surface of the planar magnetic part and other components with thermally conductive insulators. Heat dissipated by the subpackage is transferred from the exposed top thermal block to the attached heat spreader element and further to the ambient. This assembly features a compact and inexpensive power converter package with improved electrical performance and improved thermal management.

A substrate pad in a semiconductor package having a geometry and structure that facilitates providing a solder joint to the pad that has enhanced structural integrity and resistance to mechanical impact. The pad may include a plated metal stud that anchors the solder to the pad interface, providing a more compliant solder joint, even when lead-free solder is used.

The invention discloses a radio frequency module three-dimensional stacking structure and a manufacturing method thereof. The radio frequency module three-dimensional stacking structure comprises a glass cap layer, a glass carrier layer, a glass transfer frame layer, a silicon-based carrier layer, a ceramic packaging layer and radio frequency chips. The glass carrier layer, the glass transfer frame layer and the silicon-based carrier layer are all provided with through holes and interconnection lines; the glass cap layer, the glass carrier layer, the glass transfer frame layer, the silicon-based carrier layer and the ceramic packaging layer are stacked and interconnected in sequence from top to bottom; and the radio frequency chips are located on the upper surface of the silicon-based carrier layer and the upper surface of the glass carrier layer, and are connected with circuit bonding pads on the carrier layer through lead structures. Through combination and stacking of high-density substrates made of various materials, the radio frequency module is better in performance and higher in density, and the integration process is simple, flexible, better in reliability and the like.

The invention discloses an aluminum-substrate-based three-dimensional lamination chip packaging structure and a preparation method thereof. The structure comprises at least two layers of functionalized aluminum substrates, chips, aluminum-based dams, epoxy resin base bodies, a side metalized interconnection layer, and a signal leading-out layer. The functionalized aluminum substrates arranged in parallel have two opposite first surfaces and second surfaces. Chips are pasted on the second surfaces. The aluminum-based dams are pasted on the first surfaces. The epoxy resin base bodies are arranged between the functionalized aluminum substrates and the aluminum-based dams. The side metalized interconnection layer and the signal leading-out layer are arranged at the outer sides of the packaging structure in an encircling mode. The functionalized aluminum substrates contain aluminum-buried interconnection layers and through holes; and the chips and the aluminum-buried interconnection layers are electrically connected. Besides, the method includes the steps of preparation of functionalized aluminum substrates, preparation of through holes of the functionalized aluminum substrates, packaging of a multi-chip module, preparation of a signal leading-out layer; packaging of a three-dimensional lamination layer, and preparation of a side metalized interconnection layer. According to the invention, the packaging efficiency and interaction density are improved; and the size of the three-dimensional lamination chip packaging is effectively reduced.

A multilayer interconnection structure of the present invention includes first interconnection, second interconnection belonging to an interconnection layer different from an interconnection layer to which the first layer belongs, and third interconnection for connecting the first and second interconnections, the third interconnection belonging to a different interconnection layer and including interconnection along a body diagonal for connecting two points in different planes belong to different interconnection layers. A method for producing the multilayer interconnection structure includes a step of forming the third interconnection, the step including a step of forming a through hole along the body diagonal, and a step of filling the through hole with a conductive material.