64 results about "Interconnection density" patented technology

A method and apparatus for rapid and selective heating of materials using variable frequency RF and microwaves. The apparatus uses variable frequency solid state electronics as a microwave power source, a novel microwave heating head to couple microwave energy to the target materials and a match-up network to tune the frequency and impedance match between the microwave source and the load. An electronic and computer measurement and control system is employed to monitor and control the microwave heating process. The method teaches the use of inductive microwave coupling for thin conductive materials such as metal film and impurity doped silicon wafers. The method also teaches the use of capacitive microwave coupling for dielectric material such as glass and ceramics. The method further teaches the use of rapid and selective heating of heterostructure for bonding and sealing of mems and integrated circuits. The method and apparatus can provide ultra-high heating speed along with ultra-high heating temperatures for rapid thermal processing of semiconductors and other materials. It also allows the use of bonding materials with high melting temperature for strong bonding and sealing of mems and IC devices. The apparatus further provides for high interconnection density of integrated circuits as connections are made without the use of solder bumps.

An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.

The invention relates to a wafer-level chip size encapsulation technology for a GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor. The technology is characterized by comprising the following steps of: (1) firstly bonding a glass wafer and a GaAs wafer through a resin adhesive so as to protect the active surface of a chip and improve the strength of a chip wafer; (2) manufacturing a trapezoidal-slot structure by a wet corrosion or physical method so as to reduce the lining thickness of a chip interconnection area; (3) manufacturing vertical interconnected through holes by a dry etching technology so as to expose a pad on the active surface of the chip; (4) sputtering seed-layer metal and electroplating, and manufacturing a hole metalizing and RDL layer to realize circuit interconnection from the active surface to the back surface of the chip; (5) manufacturing a passivation layer, a UBM layer and raised points; and (6) finally scribing to form an independent encapsulation chip. As the trapezoidal-slot structure on the back realizes thickness reduction only in the area with the pad, the cost is effectively lowered; and through the interconnection of the vertical through holes, the encapsulation interconnection density can be improved, and the signal transmission path is shortened.

The invention discloses a multi-layered printed circuit board and a design method thereof and a terminal product motherboard, which are invented for solving the problems that the space occupied by through holes can be saved, and the interconnection density can be improved. In the multilayered printed circuit board, the terminal pad center distance of the signal communication through holes between two different interlamination insulating layers at the position of replacing layers is larger than the terminal pad radius of any one of the signal communication through holes thereof, and less than the sum of the terminal pad radius of the two signal communication through holes. The terminal product motherboard adopts the multilayered printed circuit board; the design method of the multilayered printed circuit board comprises the steps that the terminal pad center distance of the two adjacent signal communication through holes is punched in a simulation model, the terminal pad center distance is larger than any one of the terminal pad radius thereof, and less than the replaced layer signal communication through hole of the sum of the terminal pad radius of the two signal communication through holes. The embodiment of the invention is applied in the manufacture and the design of the multilayered printed circuit board.

The invention provides a high-density optical waveguide structure, a printing circuit board and a preparation method thereof. The high-density optical waveguide structure successively comprises a lower coating layer, a core layer and an upper coating layer; and a plurality of grooves are formed in the lower coating layer at intervals, and are filled with an optical waveguide materials to form thecore layer. Optical waveguide is integrated into a PCB to implement optoelectronic interconnection; high parallel interconnection density can be realized well, good signal integrity is maintained, andsizes of devices and equipment are reduced; meanwhile, power consumption is low, heat dissipation is facilitated, simple physical architecture and design can be realized, wiring space of the printingcircuit board is increased to a maximum extent, and manufacturing of an ultra-fine wire circuit board is facilitated; and moreover, wiring density of an existing preparation method can be improved, and the reliability is improved.

The present invention discloses a vertical interconnection structure for three-dimensional package based on aluminum substrates and a preparation method thereof. The structure comprises at least two layers of functionalized aluminum substrates. Each of the aluminum substrates comprises an aluminum through column, an aluminum semi-through column, a grounded aluminum column, a chip embedded cavity, an aluminum buried grounded layer and an aluminum embedded interconnection line. The vertical interconnection structure comprises embedded chips which are embedded in the chip embedded cavities of the functionalized aluminum substrates, film interconnection lines whose two ends are connected to the embedded chips and the aluminum through columns, intermetallic compound vertical interconnect lines whose two ends are connected to the aluminum through columns of two adjacent layers of functionalized aluminum substrates, and dielectric layers which are arranged at the surfaces of the functionalized aluminum substrates. The method comprises the preparation of the functionalized aluminum plate, the surface mounting of the embedded chips, the preparation of the film interconnection lines, the preparation of the dielectric layers, the deposition of the intermetallic compound, and the 3D stacked vertical interconnection. According to the vertical interconnection structure and the preparation method, the package efficiency and interconnection density are raised, and the intermetallic compound vertical interconnection is used to achieve the effect of 'low temperature preparation and high temperature use'.

The invention relates to a wafer level packaging method and structure of an image sensor. The method comprises the following steps: an image sensor wafer (1) consisting of a plurality of chips is provided and bonded with a transparent substrate (5); back thinning is performed to the image sensor wafer (1); the punching is carried out at positions, corresponding to a bonding pad electrode (4), on the back of the image sensor wafer to form a plurality of first through holes; an insulation layers (8) is coated and solidified; inverted trapezoidal second through holes are further formed in the insulation layers in the first through holes to expose the bonding pad electrode (4), wherein the first through holes and the second through holes are coaxial; a metal seeding layer (10) is sputtered and a metal interconnection layer (11) is formed through electroplating sequentially; and a second passivation layer (12) and a solder ball bump (13) are prepared sequentially. According to the invention, the whole technological process is completed on wafer level, the interconnection density is relatively high on the basis of reducing the packaging cost, and meanwhile, the interconnection structure prepared has higher reliability.

The invention discloses a base plate for stacked packaging. The surface of the base plate comprises more than one concave cavity. According to the base plate for stacked packaging provided by the invention, concave cavities are arranged on one side or both sides of the base plate, and the cavities are used for assembling chips. A certain difference in heights of the interior of each cavity and the edge of the base plate exists, interconnection solder balls are arranged on the edge of the base plate, and the interconnection solder balls with narrow pitches and small diameters can be allowed to be adopted, so that the interconnection density between two layers of packaging units can be improved.

The invention discloses a chip packaging structure and a packaging method thereof. Plastic packaging is carried out in a first opening corresponding to a bonding pad of a chip and on the back surface of the chip by adoption of a plastic packaging material, so that warpage of a chip wafer is reduced. Punching and penetrating a plastic package are carried out through processes of laser ablation and the like to form a small-size second opening for exposing the bonding pad, so that a high-density interconnected package can be achieved; and when the wafer is cut into the single chip after being packaged, the cutting interface is wrapped by a plastic packaging material and the chip can be protected from being affected by the external environment. The plastic packaging material itself is an insulating material, so that the passivation manufacturing process before a metal circuit is laid on a chip substrate in a commonly known wafer level packaging process is saved. According to the chip packaging structure and a manufacturing method, the cost is low and the interconnection density is high.

The invention discloses a radio frequency and band-shaped wire interface assembly method, which is high in transmission efficiency, small in loss, reliable in performance and high in integration interconnection density. The radio frequency and band shape wire interface assembly method can be realized through steps of integrating a high frequency signal member and a low frequency member through a broadband microwave backboard to form a motherboard, and placing a high frequency connector and an LAM connector on a same plane of a same plane layer, expanding into a stack of layers of a three-dimensional circuit toward a z direction through interlayer vertical interconnection by the planar circuit printed with the circuit graphs, in a radio frequency portion, adopting signals between Rogers RO6002 core board layers and performing radio frequency connection through metalized hole interconnection structure between the stack layers of the core plates, realizing signal transmission between the radio frequency layers through the layer pressure, realizing electric communication by a high frequency connector 2 and a high frequency connector 5 through a surface welding disc of a broadband microwave backboard 1 and manufacturing a three-dimensional non-interfering high density circuit through a corresponding prepreg sheet lamination layer.

An electronic assembly comprising an electronic module provided with optical interconnection and heat removal means, the heat removal means comprising a soleplate dedicated to removing heat on which the module is mounted. The interconnection means is independent of the soleplate and preferably comprises a printed circuit and an optical fiber included in the printed circuit. The optical fiber has an end put accurately in register with an optical contact of the module by a BGA type mounting of the printed circuit on the module. A BGA type mounting consists in placing with precision firstly balls on the module and secondly areas on the circuit, and then in bringing the balls and areas face to face so that the balls center themselves automatically with the areas by capillarity.

The invention discloses a vertical transition connector for chip package, a substrate structure and a fabrication method, and relates to the technical field of chip package. The vertical transition connector comprises an insulation connection substrate, wherein at least one conductor hole is formed in the insulation connection substrate in a vertical direction, a solid conductor post is fixedly arranged in the conductor hole, an upper bonding pad is arranged on the upper surface of the solid conductor post, and a lower bonding pad is arranged on the lower surface of the solid conductor post. The vertical transition connector has the characteristics of small size, low cost and high interconnection density, the assembly efficiency can be improved, the transmission signal frequency can be increased, and the fabrication method is simple and convenient and is suitable for automatic and miniature production application at a large scale.

Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnectdensity between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

The invention relates to the technical field of electronic packaging and particularly relates to a structure with the realization of 3D interlayer vertical interconnection by using a flexible substrate and a manufacturing method thereof. The structure comprises a first printed circuit board, a second printed circuit board, a first device, a second device, a soldered ball and a lamination structure. The second device is installed above the second printed circuit board. The first printed circuit board is fixed above the second printed circuit board, and the second device is arranged in a groove. The first device is fixed above the first printed circuit board. The lamination layer covers the first printed circuit board, the second printed circuit board and the outer side of the first device. The soldered ball is arranged at the bottom of the second printed circuit board. The invention provides the structure with the realization of 3D interlayer vertical interconnection by using the flexible substrate and the manufacturing method, the discontinuity and impedance mismatching of signals can be reduced, thus the transmission rate of the signals is greatly improved, higher bandwidth is supported, and the interconnection density of the flexible substrate is higher.

The invention belongs to the technical field of integrated circuit package, and relates to a fabrication method of a 3D high-density interconnected PoP plastic package device. The fabrication method comprises the steps of performing device surface-mounting on a front surface of an MCM substrate, and completing plastic package; completing SMT device surface-mounting and copper post surface-mountingin one time by a mode that tin paste is printed on a back surface of the substrate, and completing secondary plastic package of the back surface of the substrate; and thinning a plastic package bodyon the back surface of the substrate, exposing the copper post, and completing ball implantation at an exposure end of the copper post. The 3D high-density interconnected PoP plastic package device isin a way that on the basis of a PoP plastic device form, a conventional tin paste printing and copper post implantation process is used for substituting a vertical module through hole process, the process difficulty and cost can be reduced, the front-stage equipment investment is not needed, 3D stacking between devices is achieved, and meanwhile, the 3D direction interconnection density is further improved.