31 results about "Interconnection density" patented technology

The invention discloses a vehicle gauge chip integrated packaging manufacturing process based on an etching technology. The vehicle gauge chip integrated packaging manufacturing process comprises the following steps: step 1, designing and preparing a substrate; step 2, preprocessing the chip; step 3, chip mounting and interconnection are carried out; step 4, plastic packaging and molding; 5, heat dissipation and reinforcement are carried out; step 6, image rotation correction and defect detection; step 7, performing post-working procedures and testing; high-density interconnection such as TSV (through silicon vias), RDL (redistribution layer) and micro bumps is realized by using an etching technology, the interconnection density is remarkably improved, the RDL wiring layer manufactured by using the etching technology has the line width less than 2 microns, high-density interconnection on the surface of a chip is realized, the integration level is further improved, the micro-channel is manufactured in the plastic package layer by using the etching technology, and the packaging efficiency is improved. And the copper radiating fins are embedded, so that the radiating efficiency is effectively improved, the problem of local heat accumulation caused by integration of the power chip and the logic chip is solved, a gap between the chip and the radiating cover plate is filled with a thermal interface material with high thermal conductivity, and the thermal resistance is reduced.

The present disclosure relates to ultra-high density, low profile edge card connectors. The present disclosure increases interconnect density by using a different technology approach than currently used in the industry (stamping and molding). By using a microelectromechanical system (MEMS) technology approach, better geometry and impedance control is achieved to reduce impedance discontinuities and feature sizes. In addition, the present disclosure also includes low connector insertion force, no contact wiping, and precise alignment mechanisms between the connector contacts and the connector contacts on the mating substrate.

The invention relates to a three-dimensional heterogeneous integrated interface structure based on hybrid bonding and a stress buffer layer, and belongs to the technical field of semiconductor packaging. The interface structure sequentially comprises a copper-copper bonding layer, a polymer micro bump array, a carbon nanotube vertical interconnection bundle, a bonding interface layer, a stress self-adaptive buffer layer, a topological optimization power grid and a substrate from top to bottom, wherein an embedded coaxial interconnection structure and a graphene electromagnetic isolation wall are arranged in the topological optimization power grid. Wherein the stress self-adaptive buffer layer is formed by manufacturing polymer micro-lattices on the surface of the bonding interface layer, filling the micro-lattices with a mixture of negative thermal expansion ceramic particles and epoxy resin, and embedding shape memory alloy micro-springs. And the chip is bonded with the interface structure through the copper-copper bonding layer. The device has the advantages of being high in interconnection density, good in mechanical reliability and excellent in signal integrity, and high-performance three-dimensional heterogeneous integration can be achieved.

The invention provides a three-dimensional chip packaging structure and a manufacturing method, and relates to the technical field of integrated circuit manufacturing. The display device at least comprises a first substrate; the second substrate is arranged on the first substrate, and an accommodating space is formed between the second substrate and the first substrate; and the chip stacking structure is arranged in the accommodating space between the first substrate and the second substrate, and the chip stacking structure is electrically connected with the second substrate and the first substrate. According to the invention, the integrated three-dimensional integration of multiple chips can be realized, the integration level of the transistor and the function unit is obviously improved, the interconnection density and the space utilization rate are optimized, the problems of insufficient interconnection density, bottleneck of electrical interconnection performance and the like of the traditional packaging are solved, and the packaging efficiency is improved. The chip size is reduced, the data transmission rate and the overall efficiency of the system are effectively improved, and high-speed and low-delay data interaction is achieved.

The invention provides a photoelectric co-packaging structure and a preparation method thereof, and the method comprises the steps: a device layer in a provided silicon optical wafer at least comprises a device region which is provided with an optical port and a first bonding pad; a leading-out column penetrating through a device area is formed, a first interconnection layer electrically connected with a first bonding pad and the leading-out column is formed on the face, away from a substrate layer, of a device layer, then an electric chip is bonded to the face, away from the device area, of the first interconnection layer, and a second bonding pad exposed out of the electric chip is electrically connected with the first interconnection layer. The substrate layer is removed to expose the leading-out columns and electrically connected with the second interconnection layer through the leading-out columns, the silicon optical wafer is divided to obtain a chip structure comprising a single device area and a light outlet exposed on the side wall, and after the face, away from the device area, of the second interconnection layer is electrically connected with the substrate, the optical fiber array is optically interconnected with the light outlet. The obtained photoelectric co-packaging structure is high in interconnection density, low in interconnection loss, small in size and high in reliability, the production efficiency is improved, and the production cost is effectively reduced.

The invention provides a packaging structure and a forming method thereof, a bridging chip in a wiring insertion layer is in bonding connection with a chip packaging assembly through a first organic interconnection layer and a second organic interconnection layer, and the first organic interconnection layer and the second organic interconnection layer are bonded to form an organic hybrid bonding structure. The bridging chip does not need to be connected with the chip packaging assembly through soldering tin, so that the reliability problem of the packaging structure caused by defects (cavities or cracks) of welding points does not exist, and the packaging structure provided by the invention has good reliability; moreover, the interconnection density of the bridging chip and the devices in the chip packaging assembly can be improved, the denser I / O interconnection is realized, the transmission density is improved, and the delay is reduced.

The invention discloses a multi-mode interference type on-chip waveguide crossing device, which comprises a central multi-mode interference part in a prism shape, the central multi-mode interference part comprises N connecting side surfaces and N interval side surfaces, one interval side surface is arranged between every two connecting side surfaces, and the N connecting side surfaces directly face each other in pairs; n waveguide parts, wherein each waveguide part is fused on a corresponding connection side surface; wherein N is an even number greater than or equal to 6. According to the invention, by increasing the number of ports of the crossed waveguide, flexible routing and exchange of more optical signals can be realized, and the interconnection density and the data throughput capacity of the on-chip waveguide crossing device are remarkably improved. Meanwhile, the high-order cross structure of the on-chip waveguide cross device is beneficial to reducing the total number of cross units required on a chip, reducing the overall insertion loss and crosstalk accumulation, and optimizing the layout area and the power consumption efficiency.

The utility model provides a three-dimensional stacked high-density packaging structure based on a multi-core particle local interconnection bridge, which at least comprises a substrate, a first chip layer, a second chip layer and an interconnection bridge, a plurality of solder balls are arranged on the substrate, a plurality of core particles of the first chip layer are bonded and packaged with the substrate through the solder balls, and the first chip layer and the second chip layer are bonded and packaged through the interconnection bridge. The second chip layer is arranged above the first chip layer, the interconnection bridge is arranged between the second chip layer and the first chip layer, core particles of the second chip layer and corresponding core particles of the first chip layer are packaged in a bonding mode through solder balls, meanwhile, high-density interconnection is formed through the interconnection bridge, and the line width / line distance of the interconnection layer is smaller than 10 microns / microns. According to the utility model, the interconnection density is effectively improved, the packaging size is obviously reduced, and compared with the prior art, the problem of mismatch of thermal expansion coefficients can be improved.

The embodiment of the invention provides a fan-out type system-in-package method and a fan-out type system-in-package structure. The fan-out type system-in-package method comprises the following steps: forming at least one rewiring layer on a temporary carrier; forming a plurality of conductive columns on the first surface of the rewiring layer; mounting a plurality of first chips on the first surface of the rewiring layer; forming a first plastic package layer wrapping the conductive columns and the first chip; cutting the first plastic package layer, and then removing the temporary carrier to form a plurality of independent intermediate package bodies; mounting a plurality of second chips on the second surface of the rewiring layer; forming a second plastic package layer wrapping the second chip; and thinning the first plastic packaging layer to expose the first chip and the conductive columns. According to the method, the rewiring layer is used for replacing a packaging substrate, so that the material cost is reduced, and the interconnection density is greatly improved; the signal transmission path is shortened, the signal loss is reduced, the packaging structure is more suitable for high-frequency application, and meanwhile, the packaging thickness is reduced after a packaging substrate is cancelled; the re-wiring layer is firstly formed and then the chip is mounted, so that the chip is not wasted and the cost is saved.

The embodiment of the invention discloses a chip packaging structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The chip packaging structure comprises a first substrate, a first chip electrically connected to the first substrate, a plurality of second chips stacked on the first chip, switching structures located on the plurality of second chips, lead bonding areas connected with the second chips and first leads of the first substrate, the second lead is connected with the lead bonding area of the second chip and the switching structure; and the third lead is connected with the first substrate and the switching structure. And along the thickness direction of the first substrate, the lead bonding areas of the two adjacent second chips are arranged in a staggered manner. By arranging the switching structure, the second lead and the third lead and adopting the leads (such as the first lead, the second lead and the third lead) to realize interconnection between the first chip and the second chip, the setting area of I / O in the second chip can be increased, the number of I / O in the second chip can be increased, the interconnection density is effectively improved, and the bandwidth performance is improved.

An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.

This invention belongs to the field of advanced packaging technology, specifically relating to a multi-chip optical interconnect architecture and manufacturing method. The manufacturing method includes the following steps: S1, depositing a hard mask on the substrate surface; S2, spin-coating photoresist on the hard mask, pre-baking, alignment exposure, development, and post-baking to transfer the lower layer pattern onto the hard mask, followed by photoresist removal and cleaning; S3, manufacturing a surface ion-exchange optical waveguide; S4, printing matrix electrodes and their circuitry on the substrate surface to achieve a controllable electric field and form the lower layer optical waveguide; S5, depositing, photolithography, and etching on the substrate surface to form the upper layer optical waveguide; S6, mounting a photonic integrated chip and an arrayed waveguide grating router on the substrate surface and aligning and coupling them with the upper and lower layer optical waveguides; S7, depositing a cladding layer on the substrate surface and polishing to expose the upper surface of the photonic integrated chip. This invention effectively reduces optical path crossings and increases interconnect density, thereby achieving high-bandwidth, low-loss optical interconnects between multiple chips on a single chip.

This application discloses a three-dimensional packaging structure and its formation method. The three-dimensional packaging structure includes: a substrate, the substrate having opposing first and second surfaces, an electronic component mounted on the first surface of the substrate and electrically connected to the substrate; a first molding compound layer located on the first surface of the substrate covering the electronic component; a semiconductor chip mounted on the second surface of the substrate and electrically connected to the substrate; an adapter plate having opposing third and fourth surfaces, the third surface of the adapter plate being mounted on the second surface of the substrate surrounding the semiconductor chip, and the adapter plate being electrically connected to the substrate; a second molding compound layer located on the second surface of the substrate covering the semiconductor chip and the adapter plate, the surface of the second molding compound layer away from the substrate exposing the fourth surface of the adapter plate; and a plurality of first solder bumps located on the fourth surface of the adapter plate being electrically connected to the adapter plate. Increasing the device interconnection density of the solder bumps effectively reduces the warpage of the three-dimensional packaging structure and improves the stability of the three-dimensional packaging structure.

The application belongs to the field of advanced packaging technology, and particularly relates to a multi-chip optical interconnection architecture and a manufacturing method. The manufacturing method comprises the following steps: S1, plating a hard mask on a substrate surface; S2, spin-coating a photoresist on the hard mask, pre-baking, aligning and exposing, developing, post-baking, transferring a lower layer circuit to the hard mask, and removing the photoresist and cleaning; S3, manufacturing a surface layer ion exchange optical waveguide; S4, printing a matrix electrode and a circuit on the substrate surface to form a controllable electric field and a lower layer optical waveguide; S5, plating a film on the substrate surface, photoetching, and etching to form an upper layer optical waveguide; S6, laying the photonic integrated chip and an arrayed waveguide grating router on the substrate surface, and aligning and coupling the photonic integrated chip and the arrayed waveguide grating router with the upper and lower layer optical waveguides; and S7, depositing a cladding layer on the substrate surface and polishing to expose the upper surface of the photonic integrated chip. The application can effectively reduce optical path intersection and improve interconnection density, thereby realizing large-bandwidth, low-loss optical interconnection between multi-chips on a chip.

The embodiment of the invention provides a support plate structure and a preparation method of the support plate structure. The carrier plate structure comprises a substrate, and the substrate comprises a first surface and a second surface which are opposite to each other in the thickness direction of the carrier plate structure; in the direction parallel to the plane where the substrate is located, at least two first open grooves are formed in the first surface at intervals, first open holes and second open grooves are formed in the second surface at intervals, and the first open grooves and the first open holes are at least partially overlapped in the thickness direction of the carrier plate structure; the at least two driving elements are respectively arranged in the first open grooves; and the conductive connecting part is arranged in the second open slot and is respectively connected with each driving element. According to the invention, while integration of multiple driving elements is realized by using the conductive connecting part, the interconnection density is increased, the interconnection path is reduced, the heat dissipation effect of the driving elements is improved, and the use performance of the driving elements is improved.

The invention discloses a semiconductor device and a preparation method thereof, a chip and an electronic device, the semiconductor device comprises a first DRAM layer and a second DRAM layer which are adjacent to each other, the first DRAM layer comprises a first substrate layer, a first back bonding layer and a first DRAM unit layer, a first substrate interconnection structure is formed in the first substrate layer, and a second substrate interconnection structure is formed in the second substrate layer; the first back bonding layer comprises a first back bonding dielectric layer and a first back interconnection structure, and the first back interconnection structure comprises a first back bonding conductive layer; the second DRAM layer comprises a second substrate layer, a second DRAM unit layer and a second front bonding layer, the second front bonding layer comprises a second front bonding dielectric layer and a second front interconnection structure, and the second front interconnection structure comprises a second front bonding conductive layer; and the first back bonding dielectric layer is connected with the second front bonding dielectric layer, and the first back bonding conductive layer is connected with the second front bonding conductive layer, so that mixed bonding from the front side to the back side is adopted among a plurality of DRAM layers, and the interconnection density of the chip is improved.

This application discloses a hybrid interposer and a method for forming the same. The method includes: providing a glass interposer, the glass interposer including a plurality of discrete functional regions and a cut-out region located between adjacent functional regions, the glass interposer including opposing first and second surfaces; forming a first bonding layer on the first surface of the glass interposer; providing a plurality of silicon interposers, each silicon interposer including opposing third and fourth surfaces, the third surface having a second bonding layer; bonding at least one silicon interposer to each functional region of the glass interposer, such that the second bonding layer and the first bonding layer are mixed-bonded; and forming a molding compound covering the silicon interposers on the first surface of the glass interposer, the molding compound exposing the fourth surface of the silicon interposers. This method improves the size and interconnect density of the interposer and reduces the warpage of the interposer.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The present application relates to the field of package-on-package. Provided are a chip package-on-package and a manufacturing method therefor, and an electronic device, which can shorten the packaging cycle time and maintain a higher interconnection density while improving the heat dissipation performance. The chip package-on-package comprises a redistribution layer, a first chip, a substrate, a second chip, a vertical connection structure, a first heat dissipation member and a welding joint, wherein the first chip is disposed on a surface of the redistribution layer and is electrically connected to the redistribution layer; the substrate is disposed on the side of the first chip away from the redistribution layer, and the substrate is provided with a hollowed-out region; the second chip is disposed on the side of the substrate away from the first chip, and is electrically connected to the substrate; the vertical connection structure is connected between the substrate and the redistribution layer; the first heat dissipation member is disposed on the surface of the first chip on the side close to the substrate and extends into the hollowed-out region; and the welding joint is disposed on the side of the redistribution layer away from the first chip, and is electrically connected to the redistribution layer.

The invention provides a low-delay deep interconnection interface management system based on bus mapping, which relates to the field of electric digital data processing, and comprises an interface control module, a bus mapping module, a delay optimization module and an interconnection management module, the bus mapping module is used for establishing a data path and completing address mapping, the delay optimization module is used for carrying out delay monitoring, modeling and dynamic optimization on the data path, and the interconnection management module is used for being responsible for establishment, dynamic configuration and redundancy fault tolerance of a global interconnection structure; the system has low time delay, high interconnection density and dynamic scheduling capability, and is suitable for core interconnection control of a large heterogeneous computing system, an intelligent hardware platform and a deep interconnection system architecture.

The invention relates to a semiconductor device and a forming method thereof. The method comprises the steps that a first wafer is formed, the first wafer comprises a first substrate, a first chip and a first bonding layer, the first chip is embedded in the first substrate, the first bonding layer is located on the surface of the first substrate and the surface of the first chip, the first bonding layer comprises a first conductive structure, and the first conductive structure is connected with the first chip; a second wafer is formed, the second wafer comprises a second substrate, a first device layer and a second bonding layer, the first device layer and the second bonding layer are located on the second substrate, and the second bonding layer comprises a second conductive structure; and bonding the first bonding layer with the second bonding layer, and connecting the first conductive structure with the second conductive structure. Thus, the wafer-level bonding process between the first wafer and the second wafer is utilized, the first conductive structure and the second conductive structure are connected, the interconnection density of the first conductive structure and the second conductive structure is large, and the interconnection density of interconnection routing among multiple chips is improved.

The invention discloses a nanowire adapter plate, a preparation method of the nanowire adapter plate and application of the nanowire adapter plate in electronic packaging, and belongs to the technical field of integrated circuit chip packaging. The problem that the interconnection density, the conduction capability, the high-frequency signal integrity and the like of an existing adapter plate need to be improved is solved. Porous anodic aluminum oxide is adopted as an adapter plate main body, different pore channel parameter areas can be designed according to the layout and electrical requirements of chips above by utilizing the adjustable pore channel density and pore diameter of the adapter plate main body, specifically, a high-power unit connecting area is located below a core computing unit or a high-power unit, and the high-power unit connecting area is located below the core computing unit or the high-power unit. The porous anodized aluminum oxide pore channels in the region have higher density and / or smaller pore diameter, so that the ultrahigh conduction area proportion of the local region is realized, and the porous anodized aluminum oxide pore channels are specially used for coping with high-current and high-density signal transmission. And the high-power unit interconnection region is positioned in other regions of the core computing unit or the high-power unit, and adopts a large-size porous anodic aluminum oxide pore channel to realize stable transmission of electric power.

The application discloses a wafer-level three-dimensional integrated MEMS device optical perforation packaging process based on OTEV technology, which has higher interconnection density, smaller pitch, smaller packaging size and thickness, better warping control, lower tool cost and natural integration advantage. The MEMS device product obtained by the process has high integration, the technology adopts a 3-in-1 wafer-level manufacturing method, and integrates the optical optical path part, the wire circuit and the packaging part of the product into one; the process can realize standardization and mass production, and has simple process steps and low cost; the whole MEMS device product obtained by the application has small size and low thickness; the whole MEMS device product is free of PCB and solder wire, so the structure is more compact and the performance is more stable; the several packaging materials used by the technology have consistent thermal expansion coefficients, the internal stress between the materials after packaging is low, and the product has high reliability and stability.

The embodiment of the invention provides a chip packaging structure and electronic equipment, and the packaging structure achieves the interconnection of clocks and signals of adjacent core particles through N interconnection metal layers located at one side of a core particle layer. The length of the signal lines can be greatly shortened, the number of the signal lines which can be arranged is effectively increased, the limitation of interconnection density and bandwidth bottleneck is relieved, and therefore the purpose of meeting the requirement for large-scale parallel communication between the core particles is achieved. Moreover, the number of the N interconnected metal layers is in negative correlation with the width of the perforated area, and the height of the N interconnected metal layers is in positive correlation with the N. Through the constraint, the width of the perforated area and the number of the interconnected metal layers can be reasonably designed on the basis of meeting the requirement for the distance between the interconnected metal layers and the distance between the signal lines. Signal crosstalk between the signal lines is shielded through the shielding lines, and normal transmission of data and clock signals is guaranteed.

Provided are a semiconductor package having a structure capable of improving thermal characteristics and enhancing interconnect density, and a manufacturing method thereof. The semiconductor package includes a first semiconductor chip having a first upper surface which is an active surface and a first lower surface opposite to the first upper surface, and having a through-electrode arranged in the first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having a second lower surface which is an active surface and a second upper surface opposite to the second lower surface and having a size larger than the first semiconductor chip in a horizontal direction, and an external through-electrode placed below the second semiconductor chip and adjacent to the first semiconductor chip, wherein the second semiconductor chip is stacked on the first semiconductor chip through hybrid copper bonding (HCB).

The utility model provides a high density interconnection bridge and packaging structure, the high density interconnection bridge comprises an interconnection bridge body, rewiring layers, silicon through holes / glass through holes and micro welding columns, the rewiring layers are arranged on the upper surface and the lower surface of the interconnection bridge body, the rewiring layers are used for transverse interconnection, and the micro welding columns are arranged on the upper surface and the lower surface of the interconnection bridge body. The silicon through hole / glass through hole is formed in the interconnection bridge body, the silicon through hole / glass through hole is used for longitudinal interconnection of the rewiring layers on the upper surface and the lower surface of the interconnection bridge body, and the micro welding columns are bonded with the rewiring layers. According to the utility model, the chips can be subjected to transverse high-density interconnection through the interconnection bridges, and the chips and the substrate can be subjected to longitudinal high-density interconnection through the interconnection bridges, so that the connection mode not only reduces the packaging area, improves the interconnection density in unit area, and realizes high integration of complex functions; the flexibility and the expandability of the system are improved, and meanwhile, the power consumption and the delay are reduced, so that the efficiency and the reliability of the whole system are improved.

Described herein are an integrated circuit (IC) device mounting board, and an IC device, both of which having one or more multi-conductor vias. Also described herein are methods for fabricating an IC device mounting board having multi-conductor vias, and methods for operating IC devices having multi-conductor vias. The multi-conductor vias include separate conductive segments formed within a single via that allow any one of data signal, power and ground to be conducted on any one of the segments. Additionally, any one or more or even all of the conductive segments may be floating. The multi-conductor vias enables fewer vias to be utilized for a given number of contact pads, allowing for increased interconnect density.

Design and construction of high interconnection density, minimal loss I / O channels comprising embedded passive networks that preserve signal integrity at signaling frequencies above 1 GHz, preferably above 10 GHz, to improve memory-processor bandwidths.

The invention provides a chip stack package and a manufacturing method thereof, and an electronic device, relates to the field of stack package, and can shorten a cycle time and maintain high interconnection density on the basis of improving heat dissipation performance. The chip stack package comprises a rewiring layer, a first chip, a substrate, a second chip, a vertical connection structure, a first heat dissipation piece and a welding spot. Wherein the first chip is arranged on the surface of the rewiring layer and is electrically connected with the rewiring layer. The substrate is arranged on the side, away from the rewiring layer, of the first chip, and a hollow area is arranged on the substrate. The second chip is arranged on the side, away from the first chip, of the substrate and electrically connected with the substrate. The vertical connection structure is connected between the substrate and the redistribution layer. The first heat dissipation piece is arranged on the surface of the side, close to the substrate, of the first chip and extends into the hollow area. And the welding spot is arranged on one side, far away from the first chip, of the rewiring layer and is electrically connected with the rewiring layer.