Chip packaging structure and packaging method thereof

Abstract

The invention discloses a chip packaging structure and a packaging method thereof. Plastic packaging is carried out in a first opening corresponding to a bonding pad of a chip and on the back surface of the chip by adoption of a plastic packaging material, so that warpage of a chip wafer is reduced. Punching and penetrating a plastic package are carried out through processes of laser ablation and the like to form a small-size second opening for exposing the bonding pad, so that a high-density interconnected package can be achieved; and when the wafer is cut into the single chip after being packaged, the cutting interface is wrapped by a plastic packaging material and the chip can be protected from being affected by the external environment. The plastic packaging material itself is an insulating material, so that the passivation manufacturing process before a metal circuit is laid on a chip substrate in a commonly known wafer level packaging process is saved. According to the chip packaging structure and a manufacturing method, the cost is low and the interconnection density is high.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a chip packaging structure and a packaging method thereof. Background technique [0002] Wafer Level Packaging (WLP) is a kind of IC packaging method. After the whole wafer is produced, the packaging test is directly carried out on the wafer, and then it is cut into a single IC. There is no need for wire bonding or glue filling, and the chip size after packaging is equal to the original size of the die, so it is also called Wafer Level Chip Scale Package (WLCSP). Since WLP has the advantages of smaller package size and better electrical performance, it is easier to assemble the process and reduce the overall production cost. At present, the TSV packaging method of wafer-level chip size is: make an opening on the back of the wafer substrate, the opening extends from the back of the wafer to the front of the wafer, and exposes the solder pads on the fro...

AI Technical Summary

Problems solved by technology

At present, the TSV packaging method of wafer-level chip size is: make an opening on the back of the wafer substrate, the opening extends from the back of the wafer to the front of the wafer, and exposes the solder pads on the front, and lays metal on the inner wall of the opening. Circuits lead the electrical properties of the pads to the back of the wafer. Usually, there is a passivation process before laying metal circuits on the chip substrate. When the chip wafer is thin, there will be warping problems, and the interconnection density and cost are still high. lots of room for improvement

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