Packaging structure with supporting protection structure

Abstract

The invention relates to a packaging structure with a supporting protection structure. The packaging structure at least comprises two layers of chips which are interconnected, external interfaces are led out in one layer of chip, the second layer of chip is stacked on the first layer of chip through a stacking structure, and a closed cavity is formed between the first layer of chip and the second layer of chip. The wafer-level stacked packaging of multiple layers of chips is achieved, reliability and stability of packaging are improved, multiple protection selections are added due to the closed cavity formed between the chips, the vertical connection shortens the wiring distance, a solution is provided for power chips and power management chips which are low in requirement for power consumption, the signal to noise ratio is reduced, the dimension of the multiple layers of chips is reduced, and higher space utilization rate and higher electric interconnection density are provided.

Description

technical field [0001] The invention belongs to the technical field of packaging in semiconductor packaging, and in particular relates to a packaging structure with a support and protection structure, that is, a support and protection structure corresponding to wafer-level packaging chip stacking, at least involving the stacking of two functional chips, in particular It involves metal support and protection structures, as well as a bridge-type conductive structure built by multi-layer wiring, and uses Copper pillar and TSV technologies to achieve docking and electrical interconnection, thereby obtaining a more integrated packaging module with higher reliability , lower stacking cost. Background technique [0002] The current packaging technology is still traditional packaging as the mainstream. Although after entering the 21st century, wafer-level packaging has been widely used in image sensors, flash memory, logic devices, power chips and other industries, and the market sh...

AI Technical Summary

Problems solved by technology

[0004] However, there are still reliability problems in packaging, and the main source of the problem is insufficient protection of the functional area of ​​the chip.

For example, in the current 3D stacked package, the two-layer chips are directly connected by solder ball joints or metal eutectic interconnection, and the structure in the interconnection area is directly suspended, resulting in direct contact between the functional area and the external environment, gradual aging or exposure to some external erosion, etc. Improper function will appear after injury, resulting in lack of reliability and stability

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