Vertical interconnection structure for three-dimensional package based on aluminum substrates and preparation method thereof

Abstract

The present invention discloses a vertical interconnection structure for three-dimensional package based on aluminum substrates and a preparation method thereof. The structure comprises at least two layers of functionalized aluminum substrates. Each of the aluminum substrates comprises an aluminum through column, an aluminum semi-through column, a grounded aluminum column, a chip embedded cavity, an aluminum buried grounded layer and an aluminum embedded interconnection line. The vertical interconnection structure comprises embedded chips which are embedded in the chip embedded cavities of the functionalized aluminum substrates, film interconnection lines whose two ends are connected to the embedded chips and the aluminum through columns, intermetallic compound vertical interconnect lines whose two ends are connected to the aluminum through columns of two adjacent layers of functionalized aluminum substrates, and dielectric layers which are arranged at the surfaces of the functionalized aluminum substrates. The method comprises the preparation of the functionalized aluminum plate, the surface mounting of the embedded chips, the preparation of the film interconnection lines, the preparation of the dielectric layers, the deposition of the intermetallic compound, and the 3D stacked vertical interconnection. According to the vertical interconnection structure and the preparation method, the package efficiency and interconnection density are raised, and the intermetallic compound vertical interconnection is used to achieve the effect of 'low temperature preparation and high temperature use'.

Description

technical field [0001] The invention relates to the field of microelectronic packaging, in particular to a vertical interconnection structure for three-dimensional packaging based on an aluminum substrate and a preparation method thereof. Background technique [0002] Driven by "Following Moore's Law" and "Beyond Moore's Law", microelectronic packaging is developing towards high integration density, high power density, high reliability and low cost. During the development of packaging form from single-chip packaging to three-dimensional packaging, higher requirements are put forward for the structural stress matching and high-temperature service performance of the packaging. The interconnection technology that can meet the requirements of high interconnection density, high power density, and low-temperature bonding for future three-dimensional packaging is attracting the attention of academia and industry. [0003] Three-dimensional integration technology is the key technol...

AI Technical Summary

Problems solved by technology

Due to the parasitic resistance and distributed inductance of the lead wires, the obvious electromagnetic coupling phenomenon in high-frequency applications will cause thermo-mechanical damage, signal mutual interference, and signal loss to the device; The performance difference of some intermetallic compounds limits its application in the field of high-density packaging, and at the same time, the solder bump interconnection will lead to the existence of residual stress inside the solder joint due to its high process temperature and low rheological rate; flexible substrate Can not meet the performance requirements of high temperature service

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