Wafer-level chip size encapsulation technology for GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor

A technology of chip size packaging and image sensor, which is applied in the process of producing decorative surface effects, decorative art, metal material coating process, etc., can solve the problems of low reliability and interconnection density, high process cost, etc., and achieve reduction Packaging cost and process difficulty, increasing interconnection density, and the effect of reliable packaging
CN102509718AActive Publication Date: 2012-06-20SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
Publication Date
2012-06-20

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Abstract

The invention relates to a wafer-level chip size encapsulation technology for a GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor. The technology is characterized by comprising the following steps of: (1) firstly bonding a glass wafer and a GaAs wafer through a resin adhesive so as to protect the active surface of a chip and improve the strength of a chip wafer; (2) manufacturing a trapezoidal-slot structure by a wet corrosion or physical method so as to reduce the lining thickness of a chip interconnection area; (3) manufacturing vertical interconnected through holes by a dry etching technology so as to expose a pad on the active surface of the chip; (4) sputtering seed-layer metal and electroplating, and manufacturing a hole metalizing and RDL layer to realize circuit interconnection from the active surface to the back surface of the chip; (5) manufacturing a passivation layer, a UBM layer and raised points; and (6) finally scribing to form an independent encapsulation chip. As the trapezoidal-slot structure on the back realizes thickness reduction only in the area with the pad, the cost is effectively lowered; and through the interconnection of the vertical through holes, the encapsulation interconnection density can be improved, and the signal transmission path is shortened.
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Description

technical field

[0001] The present invention relates to a GaAs CCD image sensor wafer-level chip size packaging process and structure, more precisely relates to a GaAs CCD image sensor wafer-level chip size packaging process realized by adopting trapezoidal groove structure and vertical through-hole interconnection technology, GaAs The CCD image sensor is a MEMS (MicroElectroMechanical System, Micro Electro Mechanical System) sensing device, and therefore belongs to the field of MEMS device packaging. Background technique

[0002] MEMS refers to a system made of micro-fabrication technology, integrating micro-sensors, micro-components, micro-actuators, signal processing, and control circuits. MEMS devices have very broad application prospects in many fields, and image sensors, as a kind of MEMS devices, are particularly widely used. The pixel structure of image sensors is extremely susceptible to contamination and damage, which affects its performance. Wafer-level chip size...

Claims

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