23 results about "Gold layer" patented technology

This provides an improvement to the rewiring line structure of die packaging. [Solution] This invention provides an improvement to the redistribution line structure of die packaging, which mainly consists of one die, multiple redistribution lines, and multiple nickel-gold layers. Each redistribution line is formed on the surface of the die by being stretched horizontally using a redistribution layer (RDL) process. Each nickel-gold layer is formed on the surface of each redistribution line by being plated using a chemical nickel-gold (ENIG) process. Each nickel-gold layer consists of a nickel (Ni) layer and a gold (Au) layer, with the gold layer positioned on top of the nickel layer. This structure effectively solves the problems of uneven thickness and process complexity that occur in conventional die packaging when nickel-gold layers are formed using an electroplating process, and the RDL process can improve the design space and reliability of the die packaging.

The application discloses a reflective terahertz metasurface sensor, a biochemical detection system and application, and the sensor comprises a resonance unit with a preset period length, and the resonance unit comprises, from top to bottom, a first gold layer, a first chromium layer, a polyimide material layer, a second gold layer, a second chromium layer and a silicon dioxide material layer; wherein the width and length of the first gold layer have a preset ratio, the first gold layer and the second gold layer have a first preset thickness, and the polyimide material layer has a second preset thickness, and the application has the advantages of improved detection precision, effective differential detection of trace biochemical samples and the like.

This application provides a method for fabricating an LED chip and the LED chip itself. The method includes: providing a substrate, forming an epitaxial structure on the substrate, and forming a P-electrode and an N-electrode on the epitaxial structure. Forming the P-electrode includes: forming a first gold layer at a first evaporation rate, forming a second gold layer at a second evaporation rate, and forming a third gold layer at a third evaporation rate. Forming the N-electrode includes: forming a fourth gold layer at a first evaporation rate, forming a fifth gold layer at a second evaporation rate, and forming a sixth gold layer at a third evaporation rate. The second evaporation rate is greater than or less than the first and third evaporation rates, so that the pores of adjacent gold layers in the P-electrode and N-electrode are staggered, thereby suppressing the presence of pores penetrating the entire gold layer in the gold layers of the P-electrode and N-electrode as much as possible, reducing the possibility of chloride ions entering the electrode interior in a salt spray environment, and improving the reliability of the LED chip in a salt spray environment.

This invention discloses a method for electroplating soft gold onto a circuit board, and also discloses the circuit board. The method includes the following steps: S1: Obtaining a circuit board with a copper layer on its surface; S2: Electroplating a nickel layer on the surface of the copper layer, wherein the surface of the nickel layer has gold bonding lines and non-gold bonding lines; S3: Forming multiple arrayed and spaced bump structures in the gold bonding lines, each bump structure including a nickel substrate and a gold surface layer disposed on the surface of the nickel substrate; S4: Electroplating the circuit board with gold to form a first gold layer on the gold bonding lines and a second gold layer on the non-gold bonding lines, wherein the thickness of the first gold layer is greater than the thickness of the second gold layer. In this way, selective thickening of the gold bonding lines is achieved during the gold plating process, ensuring that the gold bonding lines have a sufficiently thick gold layer to guarantee the reliability of the gold bonding lines, while the non-gold bonding lines maintain a relatively thin gold layer, which can reduce the amount of gold used and lower the production cost of the circuit board.

The application discloses an insulating circuit board, which comprises a bottom plate, a metal layer and a pre-plated solder layer arranged in sequence from inside to outside, the metal layer comprises a palladium layer and a gold layer, the palladium layer is arranged on the side close to the bottom plate, the gold layer is arranged on the side close to the pre-plated solder layer, the thickness of the palladium layer is 0.05-1 mu m, and the thickness of the gold layer is 0.05-2 mu m. The insulating circuit board provided by the application is favorable for reducing the risk of mutual migration of nickel elements and gold elements, avoiding the generation of 'black nickel' or 'black pad' in the insulating circuit board, and further improving the quality of the insulating circuit board. On the other hand, the application provides an insulating circuit board and an electronic device, which are favorable for reducing the production cost, enhancing the use stability and service life, increasing the economic benefits, and further widening the application scenarios of the insulating circuit board.

This invention discloses a fixture for arranging electrodes on both sides of a thin-film capacitor core, belonging to the field of fixtures and molds for gold spraying of thin-film capacitors. The fixture includes a square frame and multiple horizontal plates detachably connected to the square frame. Capacitor core bodies are arranged between the horizontal plates and between the horizontal plates and the upper and lower inner walls of the square frame. Each horizontal plate has multiple grooves. Multiple elastic limiting members are provided, with one elastic limiting member corresponding to each groove. An adjusting rod is slidably disposed on the horizontal plate. When the adjusting rod moves inward into the horizontal plate, it causes the elastic limiting members to abut against the capacitor core bodies. This invention can stably clamp the thin-film capacitor core, effectively preventing displacement or deflection of the core due to high-speed metal powder impact during gold spraying, ensuring uniform gold layer thickness at both ends and complete edge coverage, significantly improving the capacitor's voltage withstand performance and electrical connection reliability.

This invention relates to the field of circuit board processing technology, specifically to a method for manufacturing an electroplating substrate. The method includes: attaching a selective dry film to the surface of the substrate, designing the exposure area of ​​the selective dry film according to the area to be plated and the non-plated area; after exposure and development, exposing the area to be plated and covering the non-plated area; electroplating nickel-gold onto the exposed copper circuit to form a nickel-gold layer on its surface, while simultaneously depositing gold whiskers on the sides of the copper circuit near the edge within the selective film coverage area; after removing the selective dry film, attaching a back-etching dry film, designing the exposure area of ​​the back-etching dry film according to the area where the gold whiskers are located, and retaining a back-etching protection area corresponding to the local copper circuit on the side where the gold whiskers are located; performing back-etching to remove the uncovered copper circuit; and removing the back-etching dry film, allowing the gold whiskers to remain bonded to the remaining local copper circuit. This invention, through the design of two exposure areas—selective dry film and back-etching dry film—fixes the gold whiskers onto the copper circuit, preventing gold whisker drift and short circuits, thus improving product yield.

This invention provides a back-side metallization structure for a semiconductor device and its manufacturing method, comprising the following steps: forming a seed layer on the back side of a semiconductor substrate; forming an electroplated gold layer on the surface of the seed layer; forming a first photoresist pattern with an opening width of CD1 on the electroplated gold layer; using the first photoresist pattern as a mask to perform an etching process on the electroplated gold layer; removing the first photoresist pattern to form an electroplated gold pattern with a line spacing of CD2; forming a second photoresist pattern with an opening width of CD3 on the surface of the electroplated gold pattern, wherein CD3 < CD1; using the second photoresist pattern as a mask to perform an etching process on the seed layer; removing the second photoresist pattern to form a metallization structure. This invention, through a dual photolithography process, forms a unique inverted trapezoidal stepped metallization structure with a wide bottom and narrow top on the back side of the semiconductor substrate, significantly enhancing the adhesion between the metallization structure and the semiconductor substrate, and improving the device's shear force test value, electrical performance, and long-term operational reliability.

This invention relates to the field of printed circuit board manufacturing, and more specifically, to a method for manufacturing a printed circuit board integrating multiple surface treatments, and a printed circuit board thereof. The method includes: S100, manufacturing a multilayer board; S200, selectively exposing electroplated hard gold areas for the first time, and plating nickel and a gold-cobalt alloy to form a hard gold layer; S300, forming outer layer circuitry; S400, selectively exposing a thick gold plating area for the second time, and chemically plating nickel-gold to form a thick gold plating layer; S500, selectively exposing a nickel-palladium-gold plating area for the third time, and chemically plating nickel, palladium, and gold to form a nickel-palladium-gold layer; S600, forming and testing; S700, selectively exposing a silver plating area for the fourth time, and chemically plating silver to form a silver plating layer; S800, final inspection and shipment. Through four selective exposures, four surface treatments—electroplated hard gold, thick gold plating, nickel-palladium-gold plating, and silver plating—are systematically integrated onto the same printed circuit board, enabling it to simultaneously possess wear-resistant insertion and removal capabilities, gold wire bonding, fine-pitch soldering, and high-frequency signal transmission functions.

The utility model discloses an acid -proof palladium gold IC encapsulation bump structure relates to chip packaging technical field, including the silicon wafer carrier, aluminum pad conductive layer, insulating layer, sputtering UBM titanium tungsten layer, sputtering UBM gold layer, electroplating palladium layer, electroplating gold layer and chemical plating gold layer that set up from below to above, wherein, aluminum pad conductive layer is deposited to the silicon wafer carrier surface through metal sputtering technology, and the surface of silicon wafer carrier is provided with insulating layer at aluminum pad conductive layer both sides, sputtering UBM titanium tungsten layer is located the outside of insulating layer, and sputtering UBM titanium tungsten layer is located the inside of sputtering UBM gold layer, in palladium gold bump plus chemical plating a layer of gold as the protective layer, prevent palladium metal layer and reagent water contact and take place the reaction, thereby effectively avoided the increase of bump circuit resistance, short circuit or open circuit, the maintenance market can continue to use after IC is pickled and recovered.

A chip package with redistribution circuits is provided. The chip package includes a chip, a plurality of redistribution circuits, and a plurality of nickel immersion gold layers. The redistribution circuits are formed and horizontally extending on the surface of the chip by a redistribution layer (RDL) process. The nickel immersion gold layer is plated on a surface of the redistribution circuit by an electroless nickel immersion gold (ENIG) process. Each of the nickel immersion gold layers is formed by a nickel layer and a gold layer located over the nickel layer. Thereby problems of the chip package available now including uneven thickness of the nickel immersion gold layer caused by electroplating process and the complex manufacturing process can be solved. The design space and reliability of the chip package are effectively improved by the RDL process.

This invention discloses a method for fabricating a high aspect ratio X-ray grating and the X-ray grating itself, relating to the fields of micro / nano fabrication and X-ray optical device manufacturing technology. The method includes: using a highly doped, low-resistivity single-crystal silicon wafer as a substrate, cleaning it, and then depositing a silicon dioxide hard mask on its surface; transferring the grating pattern to the silicon dioxide hard mask, and etching it using an improved low-temperature Bosch process to create vertical deep trenches; removing the natural oxide layer on the back side, followed by depositing a metal layer and thermal annealing to construct a conductive back electrode; performing multi-stage cleaning; placing the substrate in a bismuth ion-assisted gold sulfite plating solution for electroplating, ensuring that the gold layer fills the vertical deep trenches from the bottom upwards without voids; removing the silicon dioxide hard mask, cleaning, and drying to obtain the X-ray grating. This invention alleviates the technical problems of uneven performance, poor reliability, high production costs, and low production efficiency and yield of X-ray gratings fabricated by existing technologies.

The application discloses a plating process of a metal packaging shell of a radio frequency interference filter, which comprises the following steps: S1, electroplating a nickel layer on the outer wall of the shell, the inner wall of a blind hole and a lead wire; S2, electroplating a gold layer one on the nickel layer, wherein the thickness of the gold layer one is 0.01-0.05 um; S3, electroplating a gold layer two on the gold layer one, wherein the thickness of the gold layer two is 0.09-0.15 um; S4, electroplating a gold layer three on the outer wall of the shell and the lead wire located outside the blind hole, wherein the gold layer three is deposited on the gold layer two, and the thickness of the gold layer three is 0.2-0.6 um; and S5, electroplating a gold layer four on the lead wire located outside the blind hole, wherein the gold layer four is deposited on the gold layer three, and the thickness of the gold layer four is 2.5-4.2 um. The gold layer is electroplated by multiple steps, so that the thickness of the gold layer electroplated on each part can better meet the requirements, and the thickness fluctuation is small.

This invention relates to a carboxyl-mercaptoundecylamine interconnected graphene film / gold-plated substrate structure for reducing interfacial thermal resistance, its preparation method, and its application. The structure is formed by hot pressing a functionalized gold-plated substrate and a graphene film. The functionalized gold-plated substrate includes a copper substrate and a self-assembled monomolecular film disposed on the surface of the copper substrate. The self-assembled monomolecular film consists of a gold layer and a covalent bond structure formed between the gold layer and organic molecules with thiol structures. The surface of the graphene film also includes active groups for connecting with the self-assembled monomolecular film to form an interfacial structure. Compared with existing technologies, using carboxyl-mercaptoundecylamine to construct the molecular interconnection structure between the graphene film and the gold-plated substrate effectively reduces interfacial thermal resistance while improving interfacial adhesion. It has the advantages of simple process, stable structure, and suitability for industrial scaling.

This invention discloses a double-sided gold spraying device for thin-film capacitor cores, belonging to the field of capacitor core gold spraying. The device includes two support plates forming a conveying channel, a fixed plate fixed to the outer wall of the support plates, a carrier plate capable of reciprocating up and down on the fixed plate, and a spraying support block slidably mounted on the carrier plate; a spraying pipe mounted on the spraying support block, with a material conveying pipe attached to the spraying pipe; an air jet pipe mounted on the spraying support block; and a spraying disc connected to the spraying pipe and the air jet pipe. This invention can quickly blow away and remove loose, unbonded metal dross and oxide impurities adhering to the end face of the thin-film capacitor core after gold spraying, leaving a dense and uniform gold layer on the end face. This avoids dross obstructing solder wetting and contact, thereby ensuring the firmness and reliability of subsequent soldering.

A base layer (3) and a gold layer (4) are formed in this order on a semiconductor substrate (1). A resist pattern (5) is formed on the gold layer (4). A plating film (6) is formed on the gold layer (4) not covered with the resist pattern (5). The gold layer (4) and the base layer (3) exposed by removing the resist pattern (5) are etched by ion milling to form a metal mask (8). The semiconductor substrate (1) is plasma-etched using the metal mask (8) to form a via (9). The base layer (3) is a metal layer of at least one layer of any one of Ti, Ta, W, Ni, Co, Nb or an alloy of two or more of them. The film thickness of the gold layer (4) is 20 nm or less and the film thickness of the base layer (3) is 100 nm or more.

The present application provides an improved re-distribution line structure of a wafer package, which includes a wafer, a plurality of re-distribution lines and a plurality of nickel-gold layers. Each of the re-distribution lines is horizontally formed on the surface of the wafer by a re-distribution layer process. Each of the nickel-gold layers is plated and formed on the surface of each of the re-distribution lines by a chemical nickel-gold process. Each of the nickel-gold layers is composed of a nickel layer and a gold layer, and the gold layer is located on the nickel layer. The present application solves the problem of uneven thickness of the nickel-gold layer and complicated process caused by using an electroplating process to form the nickel-gold layer in the prior art. In addition, each of the re-distribution lines can make the multiple pads on the wafer have the effect of XY plane electrical extension and interconnection, so that multiple pads can be formed around the wafer. Therefore, the design space and reliability of the wafer package can be effectively improved.

This invention relates to the field of testing technology, disclosing a GTA-MN biosensor, its preparation method, and its application. The method includes the following steps: etching Ti3AlC2 powder in a mixture of HF, HCl, and deionized water to synthesize multilayer MXene; exfoliating the multilayer MXene with LiCl in deionized water to obtain a few-layer Ti3C2Tx_MXene; depositing a gold layer on the surface of PMMA microneedles using 3D printing to obtain Au-MNs; sequentially dipping the Au-MNs into a Ti3C2Tx_MXene aqueous dispersion and drying them, then functionalizing them with a GOx solution to obtain a GTA-MNs array; assembling the GTA-MNs array, an Ag / AgCl reference electrode, a platinum counter electrode, and an integrated circuit board to form a GTA-MNs biosensor, which can be used for continuous monitoring of blood glucose. This invention, by integrating materials science and data analysis, promotes the development of sensitive, robust, and clinically reliable CGM systems, contributing to personalized diabetes management.

A method and system for electroplating “Golden” gold nanoparticles (Nano-Au25) are disclosed. The process employs sequential substrate preparation, nickel and gold strike deposition, followed by formation of a reduced-thickness gold layer and a nanoparticle layer produced from a gold phosphate electrolyte containing sodium borohydride. The deposition is carried out at a pH of 12-14 and a temperature of 140-160° F., achieving a rate of 3-4 μm / h under controlled current density. A feedback-controlled electroplating apparatus monitors pH, temperature, and current in real time to ensure uniform nanoparticle growth. The resulting dual-layer coating provides enhanced conductivity, durability, and material efficiency while maintaining compliance with industry gold-plating standards, rendering it suitable for high-performance electronic connectors and semiconductor applications.

The present application relates to the field of printed circuit board manufacturing, more particularly, to a printed circuit board manufacturing method integrating multiple surface treatments and a printed circuit board. The method comprises: S100, manufacturing a multi-layer board; S200, exposing a electroplated hard gold area through a first selective exposure, plating nickel and gold-cobalt alloy to form a hard gold layer; S300, forming an outer layer circuit; S400, exposing a thick gold plating area through a second selective exposure, chemically plating nickel and gold to form a thick gold plating layer; S500, exposing a nickel-palladium-gold plating area through a third selective exposure, chemically plating nickel, palladium and gold to form a nickel-palladium-gold plating layer; S600, forming and testing; S700, exposing a silver plating area through a fourth selective exposure, chemically plating silver to form a silver plating layer; S800, final inspection and delivery. Through four selective exposures, the electroplated hard gold, thick gold plating, nickel-palladium-gold plating and silver plating are sequentially integrated on the same printed circuit board, so that the printed circuit board has the functions of wear-resistant plugging, gold wire bonding, fine pitch soldering and high-frequency signal transmission.

The embodiment of the application discloses a gold finger plating method and a gold finger circuit board. The gold finger plating method comprises the following steps: providing a circuit board to be plated with gold, the circuit board comprising a gold finger unit, a solder pad and a ground layer, the gold finger unit and the solder pad being located on the same conductive layer and being arranged in different layers from the ground layer; the gold finger unit comprising a signal finger and a ground finger, the tail end of the signal finger being electrically connected with the first end of the solder pad, and the ground finger being electrically connected with the ground layer; the second end of the solder pad is electrically connected with the ground layer, so that the signal finger, the ground finger, the solder pad and the ground layer form a ground network; and power is supplied to the ground network to plate the gold finger unit to be plated with gold. By using the above method, the gold finger unit to be plated with gold and the ground layer form a ground network, so that the gold layer can be plated on the gold finger unit to be plated with gold, the four-side gold plating process of the gold finger is realized, and the uneven defects and oxidation corrosion of the plug end of the gold finger are avoided.

This invention discloses a gold-based gas diffusion electrode and its preparation method for the electrochemical synthesis of hydrogen peroxide, belonging to the field of electrochemical catalysis and synthesis technology. The gold-based gas diffusion electrode comprises a polyethylene film substrate and a gold catalyst layer supported on the substrate surface. The gold catalyst layer is formed in situ by magnetron sputtering and has a crystal structure with gold {200} crystal planes as the main exposed or predominantly oriented crystal planes. By controlling the sputtering deposition conditions, gold layer thickness, and interface structure, a gas diffusion electrode with low gold loading, high oxygen transport efficiency, and high two-electron oxygen reduction selectivity can be obtained. When used for the oxygen reduction electrosynthesis of hydrogen peroxide, this electrode can achieve high hydrogen peroxide selectivity, mass activity, and operational stability with relatively low amounts of noble metals. The preparation method of this invention is simple, requires no complex post-processing or additional binders, and is suitable for the electrochemical synthesis of hydrogen peroxide in acidic, neutral, or alkaline electrolyte systems.

The application discloses a processing method of a MEMS fused quartz resonant sensor, and comprises the following steps: fused quartz wafer cleaning, circularly polarized femtosecond Bessel laser-induced processing, wet etching, high-temperature flame spraying, high-temperature precision annealing, magnetron sputtering deposition of a chromium layer and a gold layer, negative photoresist spraying, negative photoresist mask electrode layer, photoresist development, gold layer and chromium layer etching patterning, cleaning and removing surface residual photoresist, activating the wafer surface by using a low-concentration alkaline solution, pretreating a quartz base, using high-temperature glue to bond the base and a lower magnetic cap, activating the base surface, aligning and adhering the base and a sensor wafer and performing vacuum static pressing, vacuum high-temperature hydrogen atmosphere annealing, and assembling a magnetic core and an upper magnetic cap. The processing method can effectively reduce the surface roughness of the resonator after processing, reduce thermal elastic damping and stress unevenness, and finally improve the quality factor of the sensor.