Method for low-temperature solid bonding of semiconductor device

A semiconductor and bonding technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of thermal damage to the device, difficult to completely remove the solder, etc., to avoid thermal damage, controllable interface reaction, simplification The effect of the process flow

Inactive Publication Date: 2012-07-25
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The purpose of the present invention is to provide a method for low-temperature solid-state bonding of semiconductor devices to solve the problem that the fusion bonding method in the prior art needs to heat the temperature above the melting point of the solder, which will cause thermal damage to the device and cause the solder in the fusion soldering to be damaged. Spreading makes complete solder removal difficult and technically problematic with excessive interfacial reaction

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  • Method for low-temperature solid bonding of semiconductor device
  • Method for low-temperature solid bonding of semiconductor device

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Embodiment 1

[0039] Formation of bumped under metal layer (UBM), copper pillar bumps, Ni barriers and bumps on bare die with I / O pads by standard photolithographic patterning, sputter deposition and electrochemical deposition For the Sn layer on the surface, the typical copper pillar bump size is 60 μm in diameter and 40 μm in height. A typical Ni barrier layer thickness is about 1 μm. A typical Sn layer thickness is 3 - 5 μm, with a height difference of less than 0.5 μm. Copper microneedle cones and surface oxidation-resistant Au layer are prepared by chemical deposition or electrochemical deposition on the pad area of ​​the flip-chip substrate. The height of the needle cones can be 1 μm-5 μm. In this example, the height of the needle cones is about 5 μm. The thickness of Au can be 5nm-50nm, in this example, the thickness of Au is about 10nm. This thickness of Au coating will not affect the needle cone morphology. Fix the chip and the substrate face-to-face on the flip-chip b...

Embodiment 2

[0041] The lower metal layer (UBM) and Sn layer with I / O pads on the front side and the I / O pads on the front side of the bare chip through the through-silicon via (TSV) to the device side are bumped, typically The thickness of the Sn layer is 2 - 5 μm, and the height difference is less than 0.5 μm. The chip is usually thinned to less than 100 μm, and the copper microneedle cone group and the anti-oxidation gold layer are prepared on the surface of the ground and exposed TSV filling metal. The height of the needle cone is about 3 - 5 μm, and the thickness of Au is about 10 nm. After using plasma to remove the surface oxide layer and contamination particles, two or more silicon wafers with this structure are stacked and fixed in the bonding machine, and the temperature is raised to a bonding temperature of 190 ° C. At the same time, the bonding machine applies 10 The equivalent static pressure of MPa is maintained for 3 minutes to complete the stacking bonding.

Embodiment 3

[0043]Prepare a copper microneedle cone layer and an anti-oxidation Au layer on the metal block of the pad area of ​​the printed circuit board (PCB) for ball grid array (BGA) surface mounting. The needle cone height is about 3 - 5μm, and the gold thickness is about 10nm. The BGA package planted with Sn alloy solder balls with a size of 300 - 800 μm is pickled to remove the oxide layer on the surface of the solder balls, and fixed and aligned with the PCB in the bonding machine, and the temperature is raised to a bonding temperature of 190 ° C. At the same time, an equivalent static pressure of 10 MPa is applied by the bonding machine and kept for 3 minutes to complete the stack bonding.

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Abstract

The invention discloses a method for the low-temperature solid bonding of a semiconductor device. The method comprises the following steps: 1) selecting at least two elements to be bonded of electric interconnection pads which are matched with each other; 2), forming copper microneedle cone groups on a plurality of pads of one element to be bonded; 3) forming salient points with at least the surfaces provided with low-hardness second metal points on a plurality of pads of the other element to be bonded; 4) contacting the salient points with the copper microneedle cone groups, heating the contact parts of the salient points and the copper microneedle cone groups to be a first temperature, and applying bonding pressure so as to electrically inter connect and bond the salient points and the copper microneedle cone groups. Compared with the prior art, the method has the advantages that in the technique process, the temperature does not need to be heated to be higher than the melting point of soldering flux so as to melt the soldering flux, so that thermal damage to the device can be avoided, and the interconnection density and the reliability of the product can be improved by the solid bonding, the interface reaction is controllable, and organic matters such as scaling powder and the like are not needed, so that the technique process is simplified.

Description

technical field [0001] The invention relates to the field of semiconductor chip packaging, in particular to a method for low-temperature solid-state bonding of semiconductor devices. Background technique [0002] The electrical interconnection technology of semiconductor chip packaging is the core technology of packaging. The innovation of electrical interconnection technology is the key to the development of microelectronics technology. The traditional fusion bonding is to make the metal at the bonding point melt and wet the bonding point through temperature control. On the side, the bonding point solidifies after cooling, resulting in a good weld. Traditional fusion bonding processes such as reflow soldering need to heat the temperature above the melting point of the solder. The high temperature environment will have a very bad impact on some chips and substrates, greatly reducing the reliability of the product. Alternative lead-free solders have not been able to achieve ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/603
CPCH01L24/83H01L2224/83365H01L2224/83897
Inventor 陆钦李明胡安民章文婧陈卓
Owner SHANGHAI JIAO TONG UNIV
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