2376 results about "Reliability (semiconductor)" patented technology

The invention relates to the technical field of semiconductor manufacturing, and discloses a semiconductor wafer etching method with a detection function. The method comprises the following steps: acquiring initial image data of a wafer surface through an optical detection device, and extracting geometric features and defect distribution information; processing through a multi-scale feature fusion algorithm, identifying an abnormal region and classifying defect types; dynamically adjusting process parameters of etching equipment according to defect conditions, and planning a self-adaptive etching path; during etching, a real-time monitoring module is used for collecting data, and etching parameters are corrected through a feedback control mechanism; and after etching, the etching precision is secondarily detected and verified by means of a multispectral imaging technology. According to the method, defects can be accurately positioned, the etching process is optimized, the etching precision and quality are effectively improved, the rejection rate is reduced, and the efficiency and reliability of semiconductor wafer manufacturing are improved.

The invention provides a regeneration wafer defect detection method and system based on point cloud, and belongs to the technical field of semiconductor manufacturing detection, and the method comprises the steps: carrying out the registration and fusion processing of the point cloud data of a target wafer, and obtaining the target point cloud data; performing plane fitting on the target point cloud data to determine a reference plane; performing feature extraction on the target point cloud data relative to the reference plane to obtain feature data; positioning a defect area based on the feature data, and calculating geometric parameters of the defect area; correcting the geometric parameters by using a preset error compensation model to obtain target geometric parameters; inputting the position of the defect area, the target geometric parameter and the feature data of the corresponding defect area into a defect classification model to obtain a defect type of the defect area; and generating a defect detection result of the target wafer based on the defect types, the positions, the target geometric parameters and the feature data of all the defect areas of the target wafer. According to the invention, the efficiency and reliability of regenerated wafer defect detection are improved.

The invention relates to the technical field of semiconductor packaging detection, and provides a self-adaptive semiconductor packaging detection method which comprises the following steps: synchronously acquiring packaging surface heat distribution data, three-dimensional deformation data and pin electric signal data through a multi-source sensor; performing dynamic weighted fusion on the multi-modal data based on the packaging process parameters to generate a defect feature matrix; performing dynamic threshold calibration on the defect feature matrix by adopting an adaptive threshold generation algorithm according to clustering center distribution in the historical defect pattern library; performing matching judgment on the dynamic threshold value and the real-time defect feature matrix through a multi-level logic decision model, and outputting a defect type, a position coordinate and a confidence score; and based on the defect type and the confidence score, triggering adaptive compensation control of the packaging process parameters, generating a feedback control instruction, and adjusting a packaging equipment execution mechanism in real time. The packaging quality and reliability can be improved, and the production cost and the defective rate can be reduced.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention discloses a multi-AGV cooperative path planning and scheduling method for chip intelligent storage, and belongs to the field of high-precision electronic component intelligent storage. The method comprises the following steps: running according to a highway guide strategy, and pre-allocating tasks of each robot by using an MTSP problem according to different task types before path planning; an improved A * algorithm is provided, a global thermodynamic diagram congestion prediction and turning waiting heuristic method is introduced to establish a space-time joint search model, and a transportation path is optimized by greatly reducing the number of nodes needing to be searched and the turning and waiting times of the AGV, so that the efficiency is improved; in addition, a series of priority rules are also provided, and appearing conflicts are eliminated. Experiments verify the effectiveness of the method, high-reliability and low-vibration dust-free workshop AGV collaborative scheduling can be realized, and an efficient and safe warehousing automation solution is provided for semiconductor manufacturing.

The invention discloses a joint test system, a silicon carbide metasurface grating detection method and a silicon carbide metasurface grating detection device, and belongs to the technical field of semiconductor detection. A synergistic excitation signal is generated by regulating a light source and a microwave source and is applied to the silicon carbide metasurface grating to be measured to form a light intensity and microwave field interference pattern. The method comprises the following steps: synchronously acquiring data through multiple channels, constructing a multi-dimensional matrix through time alignment, marker feature extraction and coordinate mapping, extracting defect features to establish a reference model, calculating deviation degree to judge quality, and carrying out abnormal point screening, candidate region construction and coupling verification on a defect grating to divide a potential defect region. For a potential defect area, excitation parameters are dynamically adjusted through a gradient descent algorithm, and defect grades are divided by combining the characteristic defect degree and the area. According to the invention, the problems of insufficient single-mode detection, low multi-mode alignment precision and blind adjustment of excitation parameters are solved, cross-band cooperative detection and intelligent grading are realized, and the detection reliability is improved.

The invention discloses a semiconductor device communication system and method based on an SECS / GEM protocol. The system comprises an SECS / GEM protocol processing module, a PLC communication module and a service logic processing module. The protocol processing module realizes message coding and decoding and state management through an HSMS / GEM layered architecture, and supports equipment capability dynamic negotiation; the PLC communication module adopts a factory mode to adapt to a multi-manufacturer controller to realize online mapping of a physical register and a logic address; and the business logic module dynamically loads the command processor based on a reflection mechanism, and realizes multi-condition event triggering through a rule engine. The method comprises the processes of system initialization, message priority scheduling, composite alarm processing and exception recovery, and the equipment integration efficiency and the communication reliability are remarkably improved. The method solves the problems of rigid parameter mapping, single event processing and poor equipment compatibility of a traditional scheme, and can be widely applied to equipment automation control of scenes such as semiconductor wafer manufacturing and packaging testing.

The invention discloses an automatic chip thermocompression bonding device and an intelligent calibration method, and belongs to the field of semiconductor packaging and manufacturing. The device comprises a main body frame, an alignment vision system, a side vision system, a bonding arm and a workbench, and micron-order alignment and eutectic bonding of a chip and a substrate can be realized. A bonding arm adopts a vacuum suction nozzle to suck a chip, a substrate is fixed on a workbench through vacuum adsorption, an alignment visual system realizes automatic precision calibration and position feedback of the device by using a calibration sheet, and micron-sized alignment and intelligent matching of chip thermocompression bonding process parameters are realized by collecting image feature recognition. The workbench is finely adjusted to align the marking points of the chip and the substrate, then the bonding arm carries out the thermocompression bonding process, and meanwhile, the side vision system monitors the precision and reliability of chip bonding. The chip alignment precision is high, the method is suitable for the scene that multiple chips are bonded at the same time, the problem that the equipment calibration efficiency is low in the thermocompression bonding process can be solved, and the process reliability can be improved.

The present invention relates to the technical field of semiconductor chip production, and provides a chip production simulation method and system based on digital twin technology. The method comprises: collecting a processing task of a target chip and retrieving a corresponding test data set; constructing a corresponding design parameter domain and design function; performing optimization, using digital twin technology to construct a twin chip, testing the twin chip, and calculating the design fitness; performing iterative optimization to acquire an optimal design parameter; constructing an optimal twin chip, calculating the similarity between the optimal twin chip and the existing family chips, and performing verification; and carrying out design and production of the target chip. The technical problems of incapability of considering possible hardware faults and anomalies, and incapability of guaranteeing the performance and reliability of the chip due to the uncertainty of the chip production process are solved. More accurate simulation and prediction are carried out on the chip design, and potential hazards are repaired in advance. Moreover, a more detailed and accurate simulation result is provided, so that the technical effects of improving the design efficiency, reducing the costs, and improving the performance and reliability of the chip are achieved.

The invention relates to the technical field of chip optical detection, and discloses a high-precision defect detection method and system for a semiconductor chip. Initial detection data are obtained through laser scattering and photo-thermal microscopic detection, key visual features are extracted and converted into a multi-dimensional visual feature matrix, and the multi-dimensional visual feature matrix is used for detecting the defects of the semiconductor chip; according to the method, a fuzzy sensing area is positioned and potential defects are identified by using a map clustering algorithm, adaptive analysis of a supplementary visual angle is carried out and supplementary detection data is generated, and finally defect identification is carried out through the supplementary data and popularity information to obtain a chip defect result. The method effectively improves the precision and reliability of defect detection, especially has obvious advantages in recognition of complex and fuzzy regions, and solves the problem of insufficient precision of single-path optical imaging detection in the prior art.

The invention relates to the technical field of semiconductor photoelectronics, and discloses a multi-physics field coupling silicon-based optical interconnection chip degradation model construction method and application, and the method comprises the steps: firstly constructing a multi-physics field coupling analysis model, and quantitatively representing the coupling relation of thermodynamics, optics, electricity and material aging through an inter-field coupling equation and a material aging dynamic model; simulating field distribution of a chip key area under multi-environment stress through finite element analysis, and extracting data; then historical degradation data is collected by combining an accelerated aging test and long-term operation monitoring, and a degradation parameter prediction model is established after data processing based on machine learning; and finally, inputting a finite element result and a prediction result into a material aging dynamic model, and finally forming a multi-physics field coupling degradation model. The problems that the prior art depends on a single physical field, degradation mechanism analysis is incomplete, and service life evaluation is inaccurate are solved, and support can be provided for reliability evaluation, structure optimization and service life prediction of the silicon-based optical interconnection chip.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method and system and semiconductor testing equipment, and the high-speed serial signal testing method comprises the steps: carrying out the time sequence adjustment of a testing signal through a phase-adjustable clock reference, actively introducing controllable jitter, and carrying out the jitter tolerance testing; a target test signal is sent to a receiving end through an emission driver, after a receiving signal is obtained, a target sampling time sequence is extracted based on clock recovery, a programmable receiving delay chain is controlled to carry out time scanning, and receiving data at multiple sampling moments are obtained; comparing each sampling data with the test signal, counting the bit error rate under each delay setting, and completing signal quality evaluation; the scheme has the advantages of modularization, high precision, low cost and the like, and the comprehensive test efficiency and reliability of the semiconductor test equipment on high-speed serial signals are improved.

The invention discloses a solar cell performance prediction method and device based on a physical information fusion model, and relates to the technical field of computer data processing and semiconductor characterization. According to the technical scheme provided by the invention, the deep neural network architecture is adopted to perform feature extraction and fusion on the multi-dimensional spectral information, the prediction precision is improved by more than 35%, and the reliability is improved by more than 40%, so that the prediction performance is remarkably improved; an innovative physical information fusion loss function is adopted for training the model and comprises a data-driven prediction loss item and a constraint loss item based on a semiconductor device physical rule, and a prediction task and a physical principle are deeply fused, so that the prediction model can understand a physical causal relationship between spectral characteristics and device performance, and the prediction efficiency is improved. According to the method, more accurate performance prediction and better physical interpretability are realized, multiple physical constraints are adopted to standardize the prediction result, so that the model prediction result conforms to the physical principle of the semiconductor device, and the physical rationality and engineering application value of the prediction result are improved.

The invention belongs to the technical field of semiconductor processing and manufacturing, and discloses a chip bonding device and a chip bonding system. The chip bonding device comprises a shell, a driving assembly, a sensor assembly and an adsorption assembly, the driving assembly comprises a first driving piece fixedly installed on the shell and a rotating shaft arranged at the output end of the first driving piece, the rotating shaft rotatably penetrates through the shell, and the shell is connected with the rotating shaft through a first thrust piece; the sensor assembly is fixedly installed on the shell, the sensor assembly is connected with the rotating shaft through the second thrust piece, and the sensor assembly can detect the force in the first range and the force in the second range; the adsorption assembly is arranged at the end, away from the first driving piece, of the rotating shaft and used for adsorbing chips. According to the chip bonding device, the problem of poor signal stability and reliability caused by rotation of the sensor assembly is avoided; due to the arrangement of the first thrust piece and the second thrust piece, the axial stress is effectively eliminated, and the accuracy of pressure measurement and feedback is ensured.

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

The invention discloses a semiconductor device structure, a preparation method thereof and a chip, and belongs to the technical field of semiconductor devices. The semiconductor device structure comprises a gold-silver alloy bump and a UBM layer, and the UBM layer is composed of a seed layer, a diffusion barrier layer and an adhesion layer or composed of the diffusion barrier layer and the adhesion layer. The diffusion barrier layer is composed of a platinum group element simple substance and / or an alloy containing a platinum group element, preferably composed of platinum, rhodium, iridium or an alloy thereof; the bottom of the gold-silver alloy bump is connected with the seed layer or the diffusion barrier layer, and the adhesion layer is connected with a chip electrode. By improving the UBM layer, the combination reliability of the gold-silver alloy bump and the UBM layer is improved, the obtained semiconductor device structure can pass a high-end chip reliability test, and a flip chip is prepared by replacing gold with gold-silver alloy.

The invention relates to the technical field of thermal management of semiconductor devices, and provides a high-efficiency semiconductor device thermal management method and system, and the method comprises the steps: arranging a three-dimensional temperature sensor array to obtain multi-dimensional temperature data, and generating a continuous temperature distribution matrix through spatial interpolation compensation; analyzing matrix characteristics through a dynamic weight fusion algorithm, and generating a heat conduction abnormal coefficient; a self-adaptive heat dissipation topology network containing active and passive heat dissipation paths is constructed in this way; dynamically distributing heat dissipation power and cooling liquid flow velocity according to a hierarchical control strategy; fusing data of the multi-source sensor to calculate a heat dissipation efficiency deviation; a multi-objective optimization model is established based on thermodynamic constraints and device performance, control parameters are iterated, and feature extraction rules are updated. The performance and reliability of the semiconductor device can be improved, and the service life of the semiconductor device is prolonged.

The invention discloses an intelligent cutting method and system for a semiconductor machined part based on path reconstruction, and relates to the technical field of semiconductor manufacturing processes, and the method comprises the steps: monitoring a machined part image, and extracting the edge contour and internal feature point information; fitting and constructing a three-dimensional contour model; planning a cutting path based on the model and outputting initial parameters; and cutting according to the initial parameters and iteratively optimizing the path according to the feedback information until the cutting task is completed. The technical problems that in the semiconductor device manufacturing process, a traditional cutting mode is difficult to cope with dynamic interference of semiconductor materials, fine modeling and protection on the edges and the interiors of the machined parts are lacked, cutting precision is insufficient, and the machined parts are prone to being damaged and scrapped are solved, fine modeling on the edges and the interiors of the machined parts is achieved, and the cutting precision is improved. The cutting path is optimized by combining dynamic interference real-time feedback, the cutting precision is improved, the damage rejection rate of machined parts is reduced, and the technical effects of high precision and high reliability of semiconductor device manufacturing are met.

A semiconductor structure including a high kappa (high-kappa) material for a source / drain (S / D) and / or heat spreader and a method of forming the same are provided. The semiconductor structure includes a substrate, a plurality of channel layers stacked over the substrate, a gate structure covering the plurality of channel layers, and S / D regions disposed over the substrate at opposite sides of the gate structure and connecting the plurality of channel layers. The material of the S / D region includes a highly thermally conductive material having a single crystal structure, such as boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. In this case, the high thermal conductivity material can effectively dissipate heat generated by the semiconductor structure, thereby improving the yield and reliability of the semiconductor structure.

The invention discloses a rapid thermal simulation method and system for a semiconductor power assembly, and relates to the technical field of semiconductors, and the method comprises the steps: collecting a voltage V (t) signal and a current I (t) signal of the semiconductor power assembly in real time through a voltage and current sampling circuit, constructing a power pulse input sequence A, and carrying out the hot carrier accumulation analysis according to the power fluctuation change amplitude; introducing a transient thermal resistance function Zth (t), fitting the transient thermal resistance function Zth (t) with a hot carrier pulse response index Mcx after numerical integration to analyze junction temperature change caused by power pulse, and evaluating an equivalent junction temperature dynamic change rate; when the analysis result is that the thermal drift out-of-control trend exists, thermal risk analysis is carried out, and thermal risk state assessment is generated; the simulation model optimizes thermal model parameters and outputs thermal control suggestions through a rollback correction path, and the working state of the semiconductor power assembly is automatically adjusted. According to the method, real-time monitoring and effective prevention and control of thermal runaway can be realized, and the reliability and safety of the semiconductor power assembly are improved.

The invention relates to the field of semiconductor processing, and discloses a semiconductor processing contour information extraction method, device and equipment and a storage medium, and the semiconductor processing contour information extraction method comprises the steps: obtaining a to-be-processed TEM graph and a design layout of a to-be-detected wafer; searching and determining a local layout corresponding to the TEM graph to be processed in the design layout; according to the contour distribution position in the local layout, determining a corresponding preliminary screening contour imaging area in the TEM graph to be processed; and contour edge detection is carried out according to the pixel value of each pixel point in the preliminary screening contour imaging area, and contour information of the processing contour of the to-be-detected wafer in the to-be-processed TEM graph is obtained. According to the method, the accuracy and reliability of contour information extraction in the TEM graph are realized by means of the design layout of the wafer to be tested, and a reliable data basis is provided for analysis of semiconductor process quality.

The invention provides an automatic SEM image analysis and process defect detection system based on a full database, and relates to the technical field of semiconductor manufacturing, the system combines self-adaptive feature extraction and density anomaly detection of a high-performance calculation unit through dynamic feature fusion (Sp1) of a multi-scale SEM image and a multi-channel acquisition device, and realizes automatic analysis of the SEM image. Precise classification of defect types and automatic identification of new defects are achieved, the feature range and the fusion weight are dynamically adjusted, traditional static detection limitation is broken through, adaptive analysis of process context is supported, the detection precision is improved to 98%, the misjudgment and missing judgment rate is reduced by 30%-50%, especially in advanced processes such as 3nm, the new defects can be rapidly identified, rules can be updated, and the method is suitable for large-scale popularization and application. The process research and development efficiency and the product reliability are remarkably improved, and the flexible and intelligent detection capability is provided for semiconductor manufacturing.

The invention provides a packaging processing method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: constructing an initial three-dimensional model of a packaging body, cleaning and detecting a bare chip, and correcting the model after laser cutting; electrical, thermal and stress performances are simulated and optimized, multiple chips are integrated by adopting an SiP technology, and three-dimensional wiring of a substrate is completed; and after three times of cleaning, a molding process is optimized through mold flow simulation, a system-level mainboard is connected by utilizing a BGA technology, and finally, a full-performance test is completed. Through multi-stage simulation and process collaborative optimization, the packaging density, reliability and manufacturing yield of the storage chip are improved, and the method is suitable for industrial production of high-density integrated storage devices.

The invention relates to the technical field of wafer detection, in particular to semiconductor wafer cutting section defect detection equipment and a detection method, and the semiconductor wafer cutting section defect detection equipment comprises a detection shell and a conveying shell; a carrying table is arranged in the conveying shell, and a piece taking device, a camera, a spotlight, a first rotating ring, a support and a first driving unit are arranged in the detection shell. The pick-up device is arranged in the detection shell and used for taking out the semiconductor wafer on the carrying table, the moving direction of the carrying table serves as a rotation axis, the pick-up device can rotate around the rotation axis, and the rotation angle of each time is 180 degrees; the camera is arranged on one side of the pick-up device; the spotlight is of an annular structure and is arranged on the periphery of the camera in a surrounding and sleeving mode. The first rotating ring is rotationally arranged in the detection shell along the rotating axis; the support is fixedly arranged on the first rotating ring, and the camera is arranged on the support; the first driving unit is arranged on one side of the first rotating ring. According to the invention, the precision and reliability of double-sided detection of the semiconductor wafer are improved.

The invention discloses an in-situ TEM (Transmission Electron Microscope) device sample preparation method based on a suspended thinning and parallel carrying technology, which can be used for preparing in-situ TEM samples of semiconductor two-end devices and three-end devices, and mainly solves the problems of unstable ohm contact, nonuniform thinning, low success rate and high time cost in the prior art. According to the invention, an FIB sample preparation technology is adopted, and stable and reliable ohmic contact between a sample electrode and an MEMS chip electrode is ensured through specific-angle sample extraction, suspended thinning, parallel carrying, circuit breaking treatment and an accurate electrode welding process. According to the sample prepared by the invention, the failure state of a device can be observed in real time under a transmission electron microscope, the sample has the advantages of high sample preparation success rate, good repeatability, stable electrical parameters and wide applicable chip variety, and the reliability and repeatability of in-situ TEM test data are remarkably improved.

The invention provides a semiconductor module packaging structure and a semiconductor module packaging method. The semiconductor module packaging structure comprises a first substrate, a second substrate and a metal shell, the first substrate comprises a first surface and a second surface which are opposite to each other, the second substrate comprises a third surface and a fourth surface which are opposite to each other, the fourth surface is recessed towards the third surface to form a groove, and the non-recessed part of the fourth surface is electrically connected with the first surface. The structure that the first substrate and the second substrate are directly interconnected replaces a traditional copper column interconnection structure, and the problems that in the prior art, a longitudinally-stacked semiconductor packaging structure is low in reliability, high in parasitic parameter and high in thermal resistance are solved.

The invention relates to an enhanced gallium nitride device based on lamination passivation and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer from bottom to top, a P-GaN cap layer is arranged on the upper side of the AlGaN barrier layer, passivation layers are arranged on the portions, on the two sides of the P-GaN cap layer, of the AlGaN barrier layer, source electrode metal and drain electrode metal are arranged on the two sides of each passivation layer respectively, the source electrode metal and the drain electrode metal extend to the GaN buffer layer, and grid electrode metal is arranged on the upper side of the P-GaN cap layer. According to the invention, the interface quality of the device is obviously improved, the surface trap effect and hot carrier injection are inhibited, the thermal stress mismatch is relieved, and the overall electrical performance and reliability of the device are improved.

The invention relates to the technical field of semiconductor wafer defect detection, and discloses a semiconductor wafer defect detection method and system, and the method comprises the steps: generating a spatial staggered excitation pattern, and projecting the spatial staggered excitation pattern to the surface of a semiconductor wafer, the spatial staggered excitation pattern comprising an excited region and an unexcited region; capturing an optical image of the surface of the semiconductor wafer; according to the optical image, calculating the difference between the optical signal intensity of the excited area and the optical signal intensity of the adjacent non-excited area in the optical image; according to the difference, carrying out background deduction on the optical image so as to display a potential defect signal; and identifying the manifested potential defect signal. Therefore, the method can significantly improve the sensitivity, accuracy and efficiency of semiconductor wafer defect detection, thereby effectively improving the yield and reliability of semiconductor products, and reducing the production cost.

The utility model relates to a semiconductor structure. The semiconductor structure comprises a target layer structure and a conductive structure. The target layer structure comprises at least one dielectric layer, and at least one groove is formed in the dielectric layer. The conductive structure is located in the groove and is in direct contact with the dielectric layer. Wherein the bottom surface, in direct contact with the dielectric layer, of the conductive structure has the maximum surface roughness D1, the side surface, in direct contact with the dielectric layer, of the conductive structure has the maximum surface roughness D2, and the maximum surface roughness D1gt; the maximum surface roughness is D2. The utility model is used for improving the process reliability and the electrical performance of the high-density integrated memory.