1092 results about "Reliability (semiconductor)" patented technology

This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.

Provided is a nitride semiconductor device with high reliability and high flexibility in design and manufacture of the device. The nitride semiconductor device comprises a seed crystal portion (11) formed on a sapphire substrate (10) and having a mask (12) on one side surface thereof, and a GaN layer (15) grown on the sapphire substrate (10) and the seed crystal portion (11) through epitaxial lateral overgrowth. The GaN layer (15) is grown only from an exposed side surface of the seed crystal portion (11) which is not covered with the mask (12), so the lateral growth of the GaN layer (15) is asymmetrically carried out. Thereby, a meeting portion (32) is formed in the vicinity of a boundary between the seed crystal portion (11) and the mask (12) in a thickness direction of the GaN layer (15). Therefore, as the meeting portion (32) is formed in a position away from the center between the adjacent seed crystal portions (11) in a direction parallel to a surface of the substrate, a width WL of a lateral growth region is larger with respect to a pitch WP of the seed crystal potion (11), compared with conventional configurations.

Exemplary embodiments of the present invention include a semiconductor device, a method for manufacturing the same, a circuit board and an electronic apparatus with increased productivity and reliability. An exemplary method for manufacturing a semiconductor device of the present invention includes forming a conductive part in a concave part on a first surface of a semiconductor substrate, the first surface having a plurality of chip mounting areas. Stacking at least one semiconductor chip in each of the chip mounting areas, providing a sealing member on the first surface of the semiconductor substrate and making part of a second surface of the semiconductor substrate thin so as to make the conductive part penetrate from the first surface to the second surface.

A surface adapting cap with an integrated adapting thermally conductive material on single and multi chip module provides reduced gap tolerance and hence better thermal performance of the semiconductor device which enhances the reliability of the semiconductor device. In one of the embodiments the cap is modified with an integrated, confined, and high thermal adaptive material. The membrane on this system is highly flexible. The cap is preassembled to the chip at a temperature above liquidus below curing temperature of the adaptive material. At this state, a hydrostatic pressure in the material develops due to the compression exerted from the cap to the chip and the confined volume of the buried material. This hydrostatic pressure causes the membrane to deflect and to adapt the warping and tolerances of the chip. Due to the adaptive surface the gap on each position of the chip and from chip to chip is same.

A semiconductor device including a positive polarity wiring plate, negative wiring plate, more than one output wiring plate, semiconductor switch element and conductive buffer or "cushion" member is disclosed. The semiconductor switch element and cushion member are compressively interposed between the output wiring plate and positive wiring plate and also between the output wiring plate and negative wiring plate to thereby constitute bridge circuitry. The positive wiring plate, negative wiring plate or output wiring plate is for use as one support body of a pressurization structure. With such an arrangement, it is possible to improve the heat releasability of semiconductor elements while at the same time reducing the inductance of direct current (DC) circuitry to thereby suppress heat generation of the semiconductor elements, thus increasing the reliability relative to temperature cycles.

The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

The invention provides a package structure and a manufacture method thereof, belonging to the technical field of micro-electronics manufacture. The package structure comprises a semiconductor substrate, a contact welding pad, a passivation layer, a stress buffer layer and columnar lugs formed on the buffer layer, wherein the areas corresponding to any of the columnar lug structures in the stress buffer layer are provided with main openings and one or more than one auxiliary opening, the main openings and the auxiliary openings are distributed evenly in the composition plane range of the corresponding columnar lugs. The package structure provided in the invention can avoid welding flux from collapsing during reflux in the forming process of columnar lugs and has the characteristic of high reliability.

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

The invention discloses a handheld inspection device of a EMOS (enhanced metal oxide semiconductor) for accurately detecting the parameters of electric equipment, realizing the paperless office and guaranteeing the reality and the reliability of the data standards, and comprises a handheld data terminal, a client computer and a server computer, wherein an inspection data collecting module is arranged in the handheld data terminal and is used for user leading, user register, data entry, data transmission, conventional inspection, random inspection, equipment inspection and inspection record inquiry; a communication control module is arranged in the handheld data terminal, the client computer and the server computer and is used for the communication of the random inspection, the equipment inspection and the inspection record inquire; and an inspection data managing module is arranged in the server computer and is used for the arrangement of the inspection equipment, the arrangement of an inspection group, the arrangement of an inspection route, the arrangement of an inspection task, the inspection record, the historical record of the inspection, the abnormal record of the inspectionand the arrangement of a dictionary. The invention also provides a handheld inspection method of the EMOS.

The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

0 Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.

A lead frame used for the production of a semiconductor package, wherein each of terminals of the lead frame to be wire-bonded to electrodes provided on the top surface of the semiconductor device has one or two groove(s) for limiting a plating area of noble metal. Since grooves are provided in each terminal, the accuracy of the plating area can be easily checked visually. Further, the grooves absorb stress applied to the terminal when the molded semiconductor packages are individually separated from each other by punching or dicing, and the situation where molding compound comes off of the terminal is prevented. In addition, since the grooves absorb vibrational stress applied to the terminal after mounting a semiconductor on the printed circuit board, the reliability of assembly is improved.

To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.

A method of manufacturing a semiconductor device, includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.

There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.

A multi-level semiconductor device wiring interconnect structure and method of forming the same to improve electrical properties and reliability of wiring interconnects including an electromigration resistance and electrical resistance, the method including forming a dielectric insulating layer over a conductive portion; forming a via opening in closed communication with the conductive portion; forming a first barrier layer to line the via opening; forming a layer of AlCu according to a sputtering process to fill the via opening to form an AlCu via including a portion overlying the first dielectric insulating layer; and, photolithographically patterning and dry etching the portion to form an AlCu interconnect line over the AlCu via.

In order to realize a semiconductor device which is easily mounted on a circuit board and which has high mounting reliability, a semiconductor device 1 of the present invention includes: a semiconductor substrate 2; and an Au bump 3 provided on an electrode 21. The Au bump 3 is provided with a projection 3a. Also, on a surface of the Au bump 3, a solder layer 32 is formed via a Ni layer 31. The projection 3a makes it possible to easily mount the semiconductor device 1 by applying a small weight. Further, even if the amount of solder 62 supplied on an electrode 61 on a circuit board 6 is reduced, it is possible to bond the semiconductor device with a sufficient amount of solder during mounting. Furthermore, because a Ni layer 31 prevents dissolution of the bump, it is possible to ensure high mounting reliability.

An adhesive sheet for a semiconductor connecting substrate consisting of a laminate having an adhesive layer on a substrate, wherein said adhesive layer contains a thermoplastic resin (A) and an epoxy resin (B) and said epoxy resin (B) contains at least one epoxy resin (B) selected from (I) dicyclopentadiene skeleton-containing epoxy resins, (II) terpene skeleton-containing epoxy resins, and (III) biphenyl skeleton-containing epoxy resins, as an essential component; an adhesive-backed tape for TAB consisting of a laminate having an adhesive layer and a protective film layer on a flexible organic insulating film. The adhesive sheet for a semiconductor connecting substrate, the adhesive-backed tape for TAB and the adhesive-backed tape for wire bonding connection of the present invention are excellent in adhesive strength, insulatability, dimensional accuracy, etc., and can improve the reliability of a semiconductor integrated circuit connecting substrate and a semiconductor device respectively for high density packaging.

The invention discloses a semiconductor device. The semiconductor device comprises a substrate, a multilayer semiconductor layer which is disposed on the substrate and comprises an active area and a passive area, a source and a drain which are disposed in the active area, a source electrode and a drain electrode which are disposed in the passive area, a gate disposed on the source area and a gate electrode disposed on the passive area, wherein the source, the drain and the gate and / or the source electrode, the drain electrode and the gate electrode are each provided with a graphene heat dissipation layer. Due to excellent heat dissipation characteristic of graphene, transverse transmission of the heat of a local heat source is accelerated, the heat dissipation approaches of the device are increased, the heat dissipation effect of the semiconductor device is improved, the temperature inside the semiconductor device is reduced, and the reliability of the semiconductor device is enhanced.