3110 results about "Reliability (semiconductor)" patented technology

The invention provides a semiconductor chip defect automatic detection method and system based on hyperspectral imaging, and relates to the technical field of chip detection, and the method comprises the steps: collecting a chip hyperspectral image, carrying out the image enhancement and illumination non-uniformity correction through an improved neuromorphic adaptive processing network and a dual-path diffusion model, and carrying out the detection of the hyperspectral image. Extracting multi-level features by using a dynamic mixed feature enhancement network based on neural architecture search, fusing the features through a cross-layer attention mechanism, generating an initial defect detection result by using a multi-branch expert decision-making module and an uncertainty dynamic integration strategy, constructing a space-time knowledge inference graph, and determining a defect detection result; and performing reliability evaluation and optimization on the initial defect detection result in combination with the form similarity, the spatial position relationship and the process parameter influence model to obtain a final defect detection result.

The invention provides a semiconductor equipment fault prediction and maintenance method and system based on data fusion, and relates to the technical field of semiconductor equipment fault prediction and maintenance, and the method comprises the steps: collecting the data of a multi-source sensor, constructing a process-stress-material multi-dimensional state model, and calculating the failure probability of a key part. And when the failure probability exceeds a threshold value, a fault diagnosis process is triggered, fault mode identification is performed based on a digital twin model, and a fault development trend is predicted in combination with historical data. And finally, constructing a maintenance objective function, determining an optimal maintenance scheme by using an adaptive optimization algorithm and a maintenance decision rule base, and carrying out maintenance guidance. According to the method, the maintenance knowledge graph is constructed, so that continuous optimization of fault prediction and maintenance capability is realized, and the reliability and production efficiency of semiconductor equipment are improved.

The invention relates to the technical field of semiconductor manufacturing, and discloses a semiconductor wafer etching method with a detection function. The method comprises the following steps: acquiring initial image data of a wafer surface through an optical detection device, and extracting geometric features and defect distribution information; processing through a multi-scale feature fusion algorithm, identifying an abnormal region and classifying defect types; dynamically adjusting process parameters of etching equipment according to defect conditions, and planning a self-adaptive etching path; during etching, a real-time monitoring module is used for collecting data, and etching parameters are corrected through a feedback control mechanism; and after etching, the etching precision is secondarily detected and verified by means of a multispectral imaging technology. According to the method, defects can be accurately positioned, the etching process is optimized, the etching precision and quality are effectively improved, the rejection rate is reduced, and the efficiency and reliability of semiconductor wafer manufacturing are improved.

The invention provides a regeneration wafer defect detection method and system based on point cloud, and belongs to the technical field of semiconductor manufacturing detection, and the method comprises the steps: carrying out the registration and fusion processing of the point cloud data of a target wafer, and obtaining the target point cloud data; performing plane fitting on the target point cloud data to determine a reference plane; performing feature extraction on the target point cloud data relative to the reference plane to obtain feature data; positioning a defect area based on the feature data, and calculating geometric parameters of the defect area; correcting the geometric parameters by using a preset error compensation model to obtain target geometric parameters; inputting the position of the defect area, the target geometric parameter and the feature data of the corresponding defect area into a defect classification model to obtain a defect type of the defect area; and generating a defect detection result of the target wafer based on the defect types, the positions, the target geometric parameters and the feature data of all the defect areas of the target wafer. According to the invention, the efficiency and reliability of regenerated wafer defect detection are improved.

The invention relates to the technical field of semiconductor packaging detection, and provides a self-adaptive semiconductor packaging detection method which comprises the following steps: synchronously acquiring packaging surface heat distribution data, three-dimensional deformation data and pin electric signal data through a multi-source sensor; performing dynamic weighted fusion on the multi-modal data based on the packaging process parameters to generate a defect feature matrix; performing dynamic threshold calibration on the defect feature matrix by adopting an adaptive threshold generation algorithm according to clustering center distribution in the historical defect pattern library; performing matching judgment on the dynamic threshold value and the real-time defect feature matrix through a multi-level logic decision model, and outputting a defect type, a position coordinate and a confidence score; and based on the defect type and the confidence score, triggering adaptive compensation control of the packaging process parameters, generating a feedback control instruction, and adjusting a packaging equipment execution mechanism in real time. The packaging quality and reliability can be improved, and the production cost and the defective rate can be reduced.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention discloses a multi-AGV cooperative path planning and scheduling method for chip intelligent storage, and belongs to the field of high-precision electronic component intelligent storage. The method comprises the following steps: running according to a highway guide strategy, and pre-allocating tasks of each robot by using an MTSP problem according to different task types before path planning; an improved A * algorithm is provided, a global thermodynamic diagram congestion prediction and turning waiting heuristic method is introduced to establish a space-time joint search model, and a transportation path is optimized by greatly reducing the number of nodes needing to be searched and the turning and waiting times of the AGV, so that the efficiency is improved; in addition, a series of priority rules are also provided, and appearing conflicts are eliminated. Experiments verify the effectiveness of the method, high-reliability and low-vibration dust-free workshop AGV collaborative scheduling can be realized, and an efficient and safe warehousing automation solution is provided for semiconductor manufacturing.

The invention discloses a joint test system, a silicon carbide metasurface grating detection method and a silicon carbide metasurface grating detection device, and belongs to the technical field of semiconductor detection. A synergistic excitation signal is generated by regulating a light source and a microwave source and is applied to the silicon carbide metasurface grating to be measured to form a light intensity and microwave field interference pattern. The method comprises the following steps: synchronously acquiring data through multiple channels, constructing a multi-dimensional matrix through time alignment, marker feature extraction and coordinate mapping, extracting defect features to establish a reference model, calculating deviation degree to judge quality, and carrying out abnormal point screening, candidate region construction and coupling verification on a defect grating to divide a potential defect region. For a potential defect area, excitation parameters are dynamically adjusted through a gradient descent algorithm, and defect grades are divided by combining the characteristic defect degree and the area. According to the invention, the problems of insufficient single-mode detection, low multi-mode alignment precision and blind adjustment of excitation parameters are solved, cross-band cooperative detection and intelligent grading are realized, and the detection reliability is improved.

The invention discloses a semiconductor device communication system and method based on an SECS / GEM protocol. The system comprises an SECS / GEM protocol processing module, a PLC communication module and a service logic processing module. The protocol processing module realizes message coding and decoding and state management through an HSMS / GEM layered architecture, and supports equipment capability dynamic negotiation; the PLC communication module adopts a factory mode to adapt to a multi-manufacturer controller to realize online mapping of a physical register and a logic address; and the business logic module dynamically loads the command processor based on a reflection mechanism, and realizes multi-condition event triggering through a rule engine. The method comprises the processes of system initialization, message priority scheduling, composite alarm processing and exception recovery, and the equipment integration efficiency and the communication reliability are remarkably improved. The method solves the problems of rigid parameter mapping, single event processing and poor equipment compatibility of a traditional scheme, and can be widely applied to equipment automation control of scenes such as semiconductor wafer manufacturing and packaging testing.

The invention discloses an automatic chip thermocompression bonding device and an intelligent calibration method, and belongs to the field of semiconductor packaging and manufacturing. The device comprises a main body frame, an alignment vision system, a side vision system, a bonding arm and a workbench, and micron-order alignment and eutectic bonding of a chip and a substrate can be realized. A bonding arm adopts a vacuum suction nozzle to suck a chip, a substrate is fixed on a workbench through vacuum adsorption, an alignment visual system realizes automatic precision calibration and position feedback of the device by using a calibration sheet, and micron-sized alignment and intelligent matching of chip thermocompression bonding process parameters are realized by collecting image feature recognition. The workbench is finely adjusted to align the marking points of the chip and the substrate, then the bonding arm carries out the thermocompression bonding process, and meanwhile, the side vision system monitors the precision and reliability of chip bonding. The chip alignment precision is high, the method is suitable for the scene that multiple chips are bonded at the same time, the problem that the equipment calibration efficiency is low in the thermocompression bonding process can be solved, and the process reliability can be improved.

The present invention relates to the technical field of semiconductor chip production, and provides a chip production simulation method and system based on digital twin technology. The method comprises: collecting a processing task of a target chip and retrieving a corresponding test data set; constructing a corresponding design parameter domain and design function; performing optimization, using digital twin technology to construct a twin chip, testing the twin chip, and calculating the design fitness; performing iterative optimization to acquire an optimal design parameter; constructing an optimal twin chip, calculating the similarity between the optimal twin chip and the existing family chips, and performing verification; and carrying out design and production of the target chip. The technical problems of incapability of considering possible hardware faults and anomalies, and incapability of guaranteeing the performance and reliability of the chip due to the uncertainty of the chip production process are solved. More accurate simulation and prediction are carried out on the chip design, and potential hazards are repaired in advance. Moreover, a more detailed and accurate simulation result is provided, so that the technical effects of improving the design efficiency, reducing the costs, and improving the performance and reliability of the chip are achieved.

The invention relates to the technical field of chip optical detection, and discloses a high-precision defect detection method and system for a semiconductor chip. Initial detection data are obtained through laser scattering and photo-thermal microscopic detection, key visual features are extracted and converted into a multi-dimensional visual feature matrix, and the multi-dimensional visual feature matrix is used for detecting the defects of the semiconductor chip; according to the method, a fuzzy sensing area is positioned and potential defects are identified by using a map clustering algorithm, adaptive analysis of a supplementary visual angle is carried out and supplementary detection data is generated, and finally defect identification is carried out through the supplementary data and popularity information to obtain a chip defect result. The method effectively improves the precision and reliability of defect detection, especially has obvious advantages in recognition of complex and fuzzy regions, and solves the problem of insufficient precision of single-path optical imaging detection in the prior art.

A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

The invention relates to the technical field of semiconductor photoelectronics, and discloses a multi-physics field coupling silicon-based optical interconnection chip degradation model construction method and application, and the method comprises the steps: firstly constructing a multi-physics field coupling analysis model, and quantitatively representing the coupling relation of thermodynamics, optics, electricity and material aging through an inter-field coupling equation and a material aging dynamic model; simulating field distribution of a chip key area under multi-environment stress through finite element analysis, and extracting data; then historical degradation data is collected by combining an accelerated aging test and long-term operation monitoring, and a degradation parameter prediction model is established after data processing based on machine learning; and finally, inputting a finite element result and a prediction result into a material aging dynamic model, and finally forming a multi-physics field coupling degradation model. The problems that the prior art depends on a single physical field, degradation mechanism analysis is incomplete, and service life evaluation is inaccurate are solved, and support can be provided for reliability evaluation, structure optimization and service life prediction of the silicon-based optical interconnection chip.

A package substrate and a method of fabrication thereof including stress buffer layers. Each stress buffer layer may be vertically spaced from and at least partially overlap with a corresponding bonding pad of the package substrate. The stress buffer pads may provide structural reinforcement to distribute tensile stress on the package substrate and inhibit warpage and crack formation in the package substrate. Accordingly, semiconductor package reliability and yields may be improved.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method and system and semiconductor testing equipment, and the high-speed serial signal testing method comprises the steps: carrying out the time sequence adjustment of a testing signal through a phase-adjustable clock reference, actively introducing controllable jitter, and carrying out the jitter tolerance testing; a target test signal is sent to a receiving end through an emission driver, after a receiving signal is obtained, a target sampling time sequence is extracted based on clock recovery, a programmable receiving delay chain is controlled to carry out time scanning, and receiving data at multiple sampling moments are obtained; comparing each sampling data with the test signal, counting the bit error rate under each delay setting, and completing signal quality evaluation; the scheme has the advantages of modularization, high precision, low cost and the like, and the comprehensive test efficiency and reliability of the semiconductor test equipment on high-speed serial signals are improved.

The invention discloses a semiconductor device structure, a preparation method thereof and a corresponding chip, and belongs to the technical field of semiconductor devices. The semiconductor device structure comprises a gold-silver alloy bump and a UBM layer, the UBM layer is composed of a seed layer and an adhesion layer, the bottom of the gold-silver alloy bump is connected with the seed layer, the adhesion layer is connected with a chip electrode, and the thermal expansion coefficient difference value of the gold-silver alloy bump and the adhesion layer is below 9ppm / K. According to the technical scheme provided by the invention, the technical problem that the gold-silver alloy bump and the existing UBM layer cannot pass a high-low temperature cycle reliability test is solved, the obtained semiconductor device structure and the corresponding chip can pass various reliability tests, the implementation feasibility is realized by replacing the pure gold bump with the gold-silver alloy, and the reliability of the gold-silver alloy bump is improved. Therefore, the production cost of the flip chip is greatly reduced.

The invention provides a semiconductor wafer defect automatic detection method based on deep learning, which relates to the technical field of semiconductor detection, and comprises the following steps: interacting quality monitoring units of a target wafer production line, extracting a plurality of wafer defect detection data, carrying out defect feature identification on the plurality of wafer defect detection data, and obtaining K defect feature clusters; and comparing the K defect feature edge intervals with the target wafer quality feature tolerance interval, configuring an automatic detection wheel disc based on the K defect factors to obtain an automatic detection scheme, and carrying out product defect automatic detection on the target wafer production line according to the automatic detection scheme to obtain a defect detection result. The technical problems that in the prior art, semiconductor defect detection efficiency is low, missing detection and false detection are prone to occurring, wafer detection accuracy is not high, and real-time performance is insufficient are solved. The technical effects of automatically and dynamically detecting the wafer defects in real time and improving the wafer defect detection efficiency, accuracy and reliability are achieved.

The invention discloses a solar cell performance prediction method and device based on a physical information fusion model, and relates to the technical field of computer data processing and semiconductor characterization. According to the technical scheme provided by the invention, the deep neural network architecture is adopted to perform feature extraction and fusion on the multi-dimensional spectral information, the prediction precision is improved by more than 35%, and the reliability is improved by more than 40%, so that the prediction performance is remarkably improved; an innovative physical information fusion loss function is adopted for training the model and comprises a data-driven prediction loss item and a constraint loss item based on a semiconductor device physical rule, and a prediction task and a physical principle are deeply fused, so that the prediction model can understand a physical causal relationship between spectral characteristics and device performance, and the prediction efficiency is improved. According to the method, more accurate performance prediction and better physical interpretability are realized, multiple physical constraints are adopted to standardize the prediction result, so that the model prediction result conforms to the physical principle of the semiconductor device, and the physical rationality and engineering application value of the prediction result are improved.

The invention relates to the technical field of semiconductor device process reliability testing, and discloses a method, a device and equipment for predicting the time-dependent breakdown life of an insulating dielectric layer, and a medium, and the method comprises the steps: carrying out the ramp voltage testing of the insulating dielectric layer in a plurality of to-be-predicted devices; determining the breakdown electric field intensity of each to-be-predicted device according to the ramp voltage test result, the nominal insulation dielectric layer thickness and the specified voltage; determining the TDDB life of each insulating dielectric layer according to an electric field acceleration model corresponding to the TDDB and the breakdown electric field intensity of each to-be-predicted device; constants in the electric field acceleration model are determined according to TDDB test results obtained by carrying out TDDB tests on historical devices. According to the scheme disclosed by the invention, the slope voltage test is performed on the to-be-predicted device and the TDDB test result of the historical device is combined to predict the TDDB life of the insulating dielectric layer, so that the TDDB life prediction efficiency of the insulating dielectric layer is improved, and the TDDB life evaluation is quickly and effectively performed.

The invention belongs to the technical field of semiconductor processing and manufacturing, and discloses a chip bonding device and a chip bonding system. The chip bonding device comprises a shell, a driving assembly, a sensor assembly and an adsorption assembly, the driving assembly comprises a first driving piece fixedly installed on the shell and a rotating shaft arranged at the output end of the first driving piece, the rotating shaft rotatably penetrates through the shell, and the shell is connected with the rotating shaft through a first thrust piece; the sensor assembly is fixedly installed on the shell, the sensor assembly is connected with the rotating shaft through the second thrust piece, and the sensor assembly can detect the force in the first range and the force in the second range; the adsorption assembly is arranged at the end, away from the first driving piece, of the rotating shaft and used for adsorbing chips. According to the chip bonding device, the problem of poor signal stability and reliability caused by rotation of the sensor assembly is avoided; due to the arrangement of the first thrust piece and the second thrust piece, the axial stress is effectively eliminated, and the accuracy of pressure measurement and feedback is ensured.

The invention discloses a silicon-based GaN-HEMT epitaxial structure and a manufacturing method thereof, and belongs to the technical field of semiconductor device design and manufacturing, the silicon-based GaN-HEMT epitaxial structure comprises a substrate, the substrate is a silicon substrate, a nucleating layer is epitaxially grown on the substrate, a defect filtering layer is epitaxially grown on the nucleating layer, and the defect filtering layer is arranged on the substrate. An impurity regulation and control layer is epitaxially grown on the defect filtering layer, a channel layer is epitaxially grown on the impurity regulation and control layer, a barrier layer is epitaxially grown on the channel layer, the defect filtering layer deposits a GaN layer on the nucleating layer, and the GaN layer structurally comprises a plurality of vertical insertion layers. According to the silicon-based GaN-HEMT epitaxial structure and the manufacturing method thereof, the silicon-based GaN-HEMT epitaxial structure comprises a nucleating layer, a defect filtering layer, an impurity regulation and control layer, a channel layer and a barrier layer, the electrical performance, reliability and consistency of a device are improved, defects can be effectively reduced, impurity distribution can be effectively controlled by optimizing materials and growth process parameters of all layers, and the performance of the device is improved. And the voltage-resistant electric leakage performance of the device is improved.

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

The invention discloses a semiconductor device structure, a preparation method thereof and a chip, and belongs to the technical field of semiconductor devices. The semiconductor device structure comprises a gold-silver alloy bump and a UBM layer, and the UBM layer is composed of a seed layer, a diffusion barrier layer and an adhesion layer or composed of the diffusion barrier layer and the adhesion layer. The diffusion barrier layer is composed of a platinum group element simple substance and / or an alloy containing a platinum group element, preferably composed of platinum, rhodium, iridium or an alloy thereof; the bottom of the gold-silver alloy bump is connected with the seed layer or the diffusion barrier layer, and the adhesion layer is connected with a chip electrode. By improving the UBM layer, the combination reliability of the gold-silver alloy bump and the UBM layer is improved, the obtained semiconductor device structure can pass a high-end chip reliability test, and a flip chip is prepared by replacing gold with gold-silver alloy.

The invention relates to the technical field of thermal management of semiconductor devices, and provides a high-efficiency semiconductor device thermal management method and system, and the method comprises the steps: arranging a three-dimensional temperature sensor array to obtain multi-dimensional temperature data, and generating a continuous temperature distribution matrix through spatial interpolation compensation; analyzing matrix characteristics through a dynamic weight fusion algorithm, and generating a heat conduction abnormal coefficient; a self-adaptive heat dissipation topology network containing active and passive heat dissipation paths is constructed in this way; dynamically distributing heat dissipation power and cooling liquid flow velocity according to a hierarchical control strategy; fusing data of the multi-source sensor to calculate a heat dissipation efficiency deviation; a multi-objective optimization model is established based on thermodynamic constraints and device performance, control parameters are iterated, and feature extraction rules are updated. The performance and reliability of the semiconductor device can be improved, and the service life of the semiconductor device is prolonged.

The invention discloses an intelligent cutting method and system for a semiconductor machined part based on path reconstruction, and relates to the technical field of semiconductor manufacturing processes, and the method comprises the steps: monitoring a machined part image, and extracting the edge contour and internal feature point information; fitting and constructing a three-dimensional contour model; planning a cutting path based on the model and outputting initial parameters; and cutting according to the initial parameters and iteratively optimizing the path according to the feedback information until the cutting task is completed. The technical problems that in the semiconductor device manufacturing process, a traditional cutting mode is difficult to cope with dynamic interference of semiconductor materials, fine modeling and protection on the edges and the interiors of the machined parts are lacked, cutting precision is insufficient, and the machined parts are prone to being damaged and scrapped are solved, fine modeling on the edges and the interiors of the machined parts is achieved, and the cutting precision is improved. The cutting path is optimized by combining dynamic interference real-time feedback, the cutting precision is improved, the damage rejection rate of machined parts is reduced, and the technical effects of high precision and high reliability of semiconductor device manufacturing are met.

The embodiment of the invention provides a gold-silver alloy bump structure, a preparation method and a semiconductor device, and the preparation method comprises the steps: providing a semiconductor device, and forming a seed layer on the surface of the semiconductor device; a first gold-silver alloy bump is formed on the seed layer through an electroplating technology, the gold content in the formed first gold-silver alloy bump is larger than 45%, and the thickness of the first gold-silver alloy bump ranges from 0.2 micrometer to 5 micrometers; and electroplating the first gold-silver alloy bump by using the same electroplating liquid to form a second gold-silver alloy bump, wherein the gold content in the formed second gold-silver alloy bump is less than 30%, and the thickness range of the second gold-silver alloy bump is 3-20 [mu] m. The first gold-silver alloy bump with high gold content improves the binding force between the bottom of the gold-silver alloy bump structure and the seed layer of the semiconductor device, and improves the reliability of the semiconductor device. The second gold-silver alloy bump with low gold content can avoid pure gold bumps on the surface of the gold-silver alloy bump structure, the hardness and morphology of the gold-silver alloy bump structure are controlled, and subsequent packaging is ensured.

A semiconductor structure including a high kappa (high-kappa) material for a source / drain (S / D) and / or heat spreader and a method of forming the same are provided. The semiconductor structure includes a substrate, a plurality of channel layers stacked over the substrate, a gate structure covering the plurality of channel layers, and S / D regions disposed over the substrate at opposite sides of the gate structure and connecting the plurality of channel layers. The material of the S / D region includes a highly thermally conductive material having a single crystal structure, such as boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. In this case, the high thermal conductivity material can effectively dissipate heat generated by the semiconductor structure, thereby improving the yield and reliability of the semiconductor structure.

The invention discloses a WOA-BP-based SiC MOSFET life prediction method and device and a storage medium, and relates to the technical field of reliability prediction of power electronic equipment. The method comprises the following steps: selecting drain-source electrode voltage as an aging characteristic parameter of the SiC MOSFET, and acquiring voltage data in real time in an aging test process by using a sensor; the collected voltage data are preprocessed, abnormal values are eliminated, missing values are supplemented, and the data are smoothed; parameters of a back propagation neural network BP are optimized through a whale optimization algorithm WOA, and a WOA-BP prediction model is constructed; and initializing a WOA-BP model and inputting voltage data for training, and establishing a mapping relation between the service life of the SiC MOSFET and the voltage to realize prediction of the residual service life of the SiC MOSFET. The SiC MOSFET service life prediction model has the advantages of being high in adaptability, low in calculation complexity, high in prediction precision and the like, can be widely applied to the fields of the semiconductor industry, new energy automobiles, industrial automation and the like, and provides powerful support for health management and maintenance of equipment.