1271 results about "Reliability (semiconductor)" patented technology

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

The invention discloses a rapid thermal simulation method and system for a semiconductor power assembly, and relates to the technical field of semiconductors, and the method comprises the steps: collecting a voltage V (t) signal and a current I (t) signal of the semiconductor power assembly in real time through a voltage and current sampling circuit, constructing a power pulse input sequence A, and carrying out the hot carrier accumulation analysis according to the power fluctuation change amplitude; introducing a transient thermal resistance function Zth (t), fitting the transient thermal resistance function Zth (t) with a hot carrier pulse response index Mcx after numerical integration to analyze junction temperature change caused by power pulse, and evaluating an equivalent junction temperature dynamic change rate; when the analysis result is that the thermal drift out-of-control trend exists, thermal risk analysis is carried out, and thermal risk state assessment is generated; the simulation model optimizes thermal model parameters and outputs thermal control suggestions through a rollback correction path, and the working state of the semiconductor power assembly is automatically adjusted. According to the method, real-time monitoring and effective prevention and control of thermal runaway can be realized, and the reliability and safety of the semiconductor power assembly are improved.

The invention relates to the field of semiconductor processing, and discloses a semiconductor processing contour information extraction method, device and equipment and a storage medium, and the semiconductor processing contour information extraction method comprises the steps: obtaining a to-be-processed TEM graph and a design layout of a to-be-detected wafer; searching and determining a local layout corresponding to the TEM graph to be processed in the design layout; according to the contour distribution position in the local layout, determining a corresponding preliminary screening contour imaging area in the TEM graph to be processed; and contour edge detection is carried out according to the pixel value of each pixel point in the preliminary screening contour imaging area, and contour information of the processing contour of the to-be-detected wafer in the to-be-processed TEM graph is obtained. According to the method, the accuracy and reliability of contour information extraction in the TEM graph are realized by means of the design layout of the wafer to be tested, and a reliable data basis is provided for analysis of semiconductor process quality.

The invention discloses an in-situ TEM (Transmission Electron Microscope) device sample preparation method based on a suspended thinning and parallel carrying technology, which can be used for preparing in-situ TEM samples of semiconductor two-end devices and three-end devices, and mainly solves the problems of unstable ohm contact, nonuniform thinning, low success rate and high time cost in the prior art. According to the invention, an FIB sample preparation technology is adopted, and stable and reliable ohmic contact between a sample electrode and an MEMS chip electrode is ensured through specific-angle sample extraction, suspended thinning, parallel carrying, circuit breaking treatment and an accurate electrode welding process. According to the sample prepared by the invention, the failure state of a device can be observed in real time under a transmission electron microscope, the sample has the advantages of high sample preparation success rate, good repeatability, stable electrical parameters and wide applicable chip variety, and the reliability and repeatability of in-situ TEM test data are remarkably improved.

The invention relates to the technical field of semiconductor wafer defect detection, and discloses a semiconductor wafer defect detection method and system, and the method comprises the steps: generating a spatial staggered excitation pattern, and projecting the spatial staggered excitation pattern to the surface of a semiconductor wafer, the spatial staggered excitation pattern comprising an excited region and an unexcited region; capturing an optical image of the surface of the semiconductor wafer; according to the optical image, calculating the difference between the optical signal intensity of the excited area and the optical signal intensity of the adjacent non-excited area in the optical image; according to the difference, carrying out background deduction on the optical image so as to display a potential defect signal; and identifying the manifested potential defect signal. Therefore, the method can significantly improve the sensitivity, accuracy and efficiency of semiconductor wafer defect detection, thereby effectively improving the yield and reliability of semiconductor products, and reducing the production cost.

The invention provides a Laplace-DLTS stabilization inversion method and system, and the method comprises the steps: applying a pulse bias voltage to a tested semiconductor device, and collecting a transient capacitance signal of the tested semiconductor device; the transient capacitance signal is preprocessed; performing inverse Laplacian transformation processing on the preprocessed transient capacitance signal, and introducing at least one of non-negative constraint, sparsity constraint, physical prior constraint and time window segmentation constraint in an inversion process; carrying out optimization processing on the obtained inversion result, and judging the stability of the inversion result; and extracting a deep energy level trap parameter based on the inversion result, and outputting the deep energy level trap parameter and the processed transient spectrum data. At least one, preferably at least two, constraint conditions are introduced in the inverse Laplacian inversion process, so that the influence of noise and abnormal peaks on the inversion result is effectively inhibited, and the stability, physical consistency and parameter extraction reliability of the inversion are improved.

The invention discloses an Agent task planning and workflow generation method driven by knowledge in the semiconductor field, and relates to the cross technical field of artificial intelligence and semiconductor manufacturing. According to the method, in order to solve the problems that in the prior art, a semiconductor data analysis task lacks domain knowledge support, workflow generation stability is poor, and execution links are uncontrollable, a Task-Planner and Executor-Planner double-layer framework is adopted, and accurate matching from user requirements to domain subtasks is achieved by constructing a semiconductor domain task knowledge base; a structured prompt mechanism is designed, and a directed acyclic graph workflow with complete logic is generated in combination with the fine-tuned large language model; error localization processing is introduced, and reliable execution of the workflow is guaranteed; the method can automatically complete the planning and execution of complex tasks such as yield analysis and fault diagnosis in semiconductor wafer manufacturing, packaging testing and equipment operation and maintenance, improves the data analysis efficiency and reliability, and is suitable for a high-precision semiconductor manufacturing scene.

The invention relates to a method. The invention discloses an ATE-based method for batch detection of pseudo soldering and sealing-off of chip packaging bonding, and belongs to the technical field of semiconductors. The method comprises the following steps: aiming at packaged and bonded chips, providing excitation current for each chip to be tested through an ATE test machine, and conducting an ESD (Electro-Static Discharge) diode connected with each pin of the chip; detecting the voltage drop between each pin and the pin GND; and calculating the equivalent resistance to determine whether pseudo soldering or unsoldering exists. The detection method has high practicability, is simple to operate, is very suitable for large-scale application and popularization, and has a certain promotion effect on improvement of a chip packaging test technology, improvement of chip performance reliability and chip packaging inspection.

The invention relates to the technical field of semiconductor detection and automatic packaging, discloses a vision detection and accurate placement system and method for MINI chips, and aims to solve the problems that in the prior art, due to the lack of multi-source sensing fusion and closed-loop control, the chip positioning precision is insufficient, the grabbing and placement reliability is low, and the whole-process quality monitoring is lack. The method comprises the following steps: acquiring three-dimensional coordinates and attitude data of a chip through a distance measurement detection unit; the vacuum pressure of the suction nozzle is monitored in real time to confirm the grabbing state; the actual posture of the chip and the burning station reference data are fused, a six-dimensional space compensation vector is calculated, a manipulator is driven to conduct fine adjustment, and accurate placement is achieved; and visual inspection is carried out at the discharging braid end, and comprehensive judgment of position, appearance and character recognition is completed. According to the scheme, submicron positioning correction, closed-loop grabbing control and whole-process quality monitoring are achieved, and the chip placement precision, the production yield and the automation efficiency are remarkably improved.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

The invention discloses a wafer high-precision alignment mechanism, and relates to the technical field of semiconductor manufacturing and packaging, the wafer high-precision alignment mechanism comprises a casing and a vertical box integrally and fixedly connected to the upper part of the rear side of the casing, a cantilever is fixedly connected to the center of the upper part of the front side of the vertical box, and a detection mechanism for performing optical detection on a wafer is arranged between the cantilever and the upper wall of the casing. A circular movable hole is formed in the upper wall of the machine shell, the central axis of the movable hole is located on the central axis face of the cantilever, and an alignment mechanism used for adjusting the position of the wafer is arranged in the movable hole. By arranging the cleaning assembly and adopting a closed-loop design combining blowing and suction, the invention has the following remarkable beneficial effects: firstly, the structure forms an air curtain barrier with directional flow through the synergistic effect of positive-pressure blowing and negative-pressure suction, not only can dust on the mirror surface of the optical probe be continuously removed, but also pollutants can be actively discharged from the inside of equipment, so that the cleaning efficiency is greatly improved; the secondary pollution is fundamentally avoided, and the thoroughness and reliability of cleaning are greatly improved.

The application relates to a semiconductor package failure detection method based on high harmonic amplitude-phase demodulation, and relates to the technical field of semiconductor package detection. The application is used to solve the problems existing in the prior art semiconductor package defect detection method. The application applies a current excitation to a measured semiconductor package to make the semiconductor package generate heat, and collects a thermal image sequence of the semiconductor package; a same-frequency quadrature reference signal of each harmonic of the thermal image sequence is synthesized according to the current excitation; a demodulation phase is extracted by using the same-frequency quadrature reference signal; a dominant path is extracted according to a fourth-order demodulation phase; the dominant path is verified according to a fifth-order and sixth-order demodulation phase; if the dominant path is verified to be correct, it is determined that the measured semiconductor package has a failure state corresponding to the dominant path; otherwise, the thermal image sequence of the measured semiconductor package is collected again for detection. The application is suitable for the fields of semiconductor package manufacturing and testing, quality and reliability control, failure analysis and the like.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention belongs to but not limited to the technical field of power semiconductor packaging, and discloses a packaging structure of a power semiconductor device. The power module comprises a lead frame, a plastic package body, a base island, a bonding wire and a semiconductor chip assembly, a first power unit and a second power unit are integrated, the first unit comprises two driving ICs, six IGBTs and six FRD chips, the second unit comprises two driving ICs and six MOS chips, 46 pins are provided, and functions are clearly divided. All the IC chips and the FRD chips are arranged on the same base island, the back faces of the chips are welded to the base island, and the front faces of the chips are connected with pins in a standard mode through bonding wires. The structure solves the problems of complex packaging layout, disordered connection and the like in the prior art, can drive the compressor and the fan respectively, realizes high integration level and compact layout, shortens an electric connection path, reduces parasitic parameters, reduces the overall size and cost, and improves reliability and engineering compatibility.

The invention discloses a semiconductor sealing ring irregular surface contour detection method and system, and relates to the technical field of semiconductor sealing rings, and the method comprises the following steps: marking contour data collected in real time in historical detection data as to-be-detected contour data; dividing the to-be-measured contour data into environment sensitive contour data and environment tolerant contour data according to the environment response deformation characteristics, and processing the environment sensitive contour data and the environment tolerant contour data to obtain a to-be-measured environment sensitive ratio; performing environment dimension feature division on the to-be-measured contour data according to the to-be-measured environment sensitivity ratio to obtain an environment dimension scheme; acquiring a standard environment deformation reference of the contour data according to the environment dimension scheme; processing and analyzing the to-be-measured contour data and the standard environment deformation reference to obtain a coincidence environment time sequence comparison result and a difference environment time sequence comparison result; the overall quality and reliability of the semiconductor sealing ring are improved.

The invention relates to the technical field of semiconductor packaging, and discloses a bonding wire welding method based on bare chip interconnection, and the method comprises the steps: collecting and fusing acoustic response and optical reflection signals of a bonding interface in real time through a multi-mode in-situ sensing mechanism integrating acoustic resonance and surface plasmon resonance; dynamically calculating the thickness, the mechanical coupling deformation and the energy dissipation state of the intermetallic compound layer; and the ultrasonic power and the bonding force are subjected to closed-loop adjustment in combination with a model prediction control algorithm, so that the welding process is evolved along a preset optimal physical path all the time. The system comprises a multi-mode sensing welding head, a synchronous data acquisition module, a state resolving module and a self-adaptive control module. The transparent and intelligent welding process is realized, and the bonding consistency, reliability and yield of high-density interconnection are remarkably improved.

The invention discloses a multi-mode fusion power semiconductor module full-automatic detection system and method, relates to the technical field of semiconductor testing, constructs a multi-topology loading module, and realizes mechanical load testing under a frequency converter working condition, electrical load simulation under a grid-connected working condition and static electrical parameter testing. And covering dynamic and static performance detection of the module in a multi-application environment. A multi-source temperature monitoring and weighted fusion technology is introduced, and precise regulation and control of local junction temperature, surface temperature and radiator temperature of the module are realized. Dynamic switch characteristics are extracted from various collected data through wavelet transformation, and module failure probability prediction is completed in combination with a Weibull life model. Automation of whole-process data analysis and detection report generation is achieved, and the test efficiency and the evaluation intelligent level are improved. The method is suitable for multi-scene performance evaluation and reliability analysis of the power semiconductor module.

The invention discloses a full-automatic life test system for an isolation device, which belongs to the field of reliability test of semiconductor devices, and comprises a system host used for providing a test environment and bearing a plurality of test channels; the high-low voltage isolation conversion module is arranged corresponding to each test channel and is used for switching between a high-voltage aging loop and an insulation resistance measurement loop of each channel; the real-time leakage current monitoring module is used for continuously monitoring the leakage current of each isolation device in the high-voltage aging process; the precision measurement and data acquisition module is used for carrying out insulation resistance measurement on the isolation device in a measurement mode; the central control and software system module is respectively connected with the high-low voltage isolation conversion module, the real-time leakage current monitoring module and the precision measurement and data acquisition module, and the central control and software system module is used for automatically triggering and controlling an insulation resistance measurement process according to leakage current data, judging the state of a device according to a measurement result, and outputting the state of the device. And aging and stopping of the test channel are managed.

The invention discloses an LED chip packaging optimization method and device based on thermal management and a medium, and relates to the technical field of semiconductor device packaging and thermal management, and the method comprises the steps: carrying out the thermal field simulation of an LED chip packaging three-dimensional model, obtaining the temperature distribution, the heat flow direction and the thermal resistance path in a packaging body, carrying out the heat flow analysis of the thermal resistance path, and carrying out the thermal field simulation of the LED chip packaging three-dimensional model; determining a heat conduction channel and generating a heat conduction path parameter set; and applying the packaging adhesive function partitioning scheme to the updated LED chip packaging three-dimensional model, performing thermal-stress joint simulation to obtain an optimized LED chip packaging three-dimensional model, and extracting an LED chip packaging parameter set. According to the invention, the thermal function partition operation of the packaging adhesive is carried out based on the optimized heat flux density vector field, partition cooperation of the heat conduction performance and the flexibility of the packaging adhesive is realized, and the heat dissipation performance and the reliability of the structure are improved.

The invention provides a training method, a server, equipment, a medium and a product, and the method comprises the steps: obtaining the key information of a plurality of teacher models trained by a first server from the first server, and the training data of each teacher model comprises a first group of wafer sample images, training a first pre-trained student model based on the key information of each teacher model and each second group of wafer sample images to obtain each candidate student model, determining a target momentum parameter based on the performance index of each candidate student model and the momentum parameters of the plurality of teacher models, and obtaining a target momentum parameter of the candidate student model based on the candidate student model corresponding to the target momentum parameter. And determining a wafer defect detection model. The wafer defect detection model trained by the method can give full play to the potential adaptive ability, generalization ability, high availability and high reliability of AI, thereby ensuring that the model can adapt to the requirements of the semiconductor manufacturing industry.

The invention relates to an ultrasonic bonding process and a bonding process reliability evaluation method, and belongs to the technical field of semiconductor device packaging. The invention relates to an ultrasonic bonding process, which comprises the following steps of: 1, before bonding, carrying out plasma cleaning on a metal ceramic shell to remove surface contamination and an oxide layer; step 2, enabling the aluminum wire to penetrate into a chopper of a bonding machine, enabling the aluminum wire to be in contact with the surface of the gold-plated layer at the bonding pressure of 250cN-280cN by adopting the chopper, and enabling the aluminum wire to be in contact with the surface gold-plated layer of the bonding area in a low-pressure mode; and step 3, the bonding machine applies ultrasonic power of 10.5-12.3 W for 400-500 ms, the aluminum wire begins to rub and destroy the gold-plated layer on the surface of the bonding area under the action of the ultrasonic power, and after the gold-plated layer is destroyed, the aluminum wire penetrates through the gold-plated layer and forms an atomic-scale mutual diffusion interface with the nickel-plated layer. Reliable combination of gold, aluminum and nickel is achieved, meanwhile, a reliability evaluation method is provided, and therefore it is guaranteed that devices, circuits and the like adopting the ultrasonic bonding technology work reliably in the life cycle.

The invention discloses a preparation method of a fan-out type packaging structure, and belongs to the technical field of semiconductor packaging. According to the invention, by introducing two molding processes and combining the support of the vertical guide pillar, a stress-balanced double-sided coating structure is constructed, so that packaging body warping caused by material thermal mismatch is significantly inhibited. By adopting the stable low-warping structure formed by the invention, the yield of subsequent processes such as photoetching is greatly improved, the dependence on an expensive compensation material is reduced, and a complicated warping correction step is omitted. The area of the dielectric layer is limited in the central area of the surface of the molding compound, so that the path of environmental moisture invading from the edge is structurally blocked, the problems of interface layering and reliability degradation caused by moisture absorption of dielectric materials such as photosensitive polyimide are fundamentally solved, meanwhile, an edge stress concentration area is avoided, and the service life of the dielectric material is prolonged. And the interface stability is enhanced. In addition, the pre-formed vertical guide pillars also provide vertical electrical interconnection and heat dissipation paths for packaging.

The invention relates to the technical field of reliability testing of semiconductor power devices, and discloses a short-circuit robustness testing method and system based on grid stress degradation of a silicon carbide device, and the method comprises the steps of pre-testing short circuit, grid stress application and post-testing short circuit are continuously executed under the same physical connection by configuring a coupling testing time sequence. The control unit cooperates with the driving unit to generate a static positive and negative bias and dynamic switch stress mode, and cooperates with the power loop auxiliary switch action to simulate different short circuit faults. A dynamic and static index correlation model is established to quantitatively evaluate robustness by collecting transient waveforms and measuring static parameters and calculating short-circuit energy integral, threshold voltage and drift distance of on resistance. According to the invention, the in-situ test of the aging and short-circuit characteristics of the device is realized, the contact resistance change and the loop parasitic parameter difference caused by the repeated disassembly and assembly of the device in the traditional discrete test are eliminated, and the change of the two short-circuit waveforms completely corresponds to the internal degradation of the device caused by the grid stress.

The invention relates to the technical field of semiconductor equipment, and discloses a chip high-temperature test machine, which comprises a workbench, and a chip feeding module, a turret transfer module, an appearance detection module, a defective product collection module and a high-temperature test module which are arranged on the workbench, the chip supply module, the appearance detection module, the defective product collection module and the high-temperature test module are arranged on one side of the turret transfer module at intervals around the turret transfer module; wherein the turret transfer module is provided with a material taking station, a detection station, a defective product discharging station and a test discharging station, the chip supply module is arranged corresponding to the material taking station, the appearance detection module is arranged corresponding to the detection station, the defective product collection module is arranged corresponding to the defective product discharging station, and the high-temperature test module is arranged corresponding to the test discharging station. According to the high-temperature chip testing machine, high-temperature testing can be carried out on the chip, physical appearance defects of the chip can be detected, and the tested chip has good performance and reliability.

The invention discloses a processing defect detection method and system based on a semiconductor integrated circuit, and belongs to the technical field of semiconductor manufacturing data processing and defect detection, and the method comprises the steps: obtaining a high-resolution surface topography scanning matrix, an interlayer stress distribution matrix and a transient electrical response matrix of a specified process layer of a target wafer, and constructing an original feature tensor after correction; generating a multi-dimensional coupling feature matrix, and constructing a spatial adjacency topology network and a cross-layer coupling energy propagation graph model; performing energy iteration deduction on the basis of introducing a current density direction vector and a thermal diffusion coefficient parameter to obtain a potential energy gathering path; a microdefect risk coupling coefficient distribution diagram is generated through time sequence folding mapping and nonlinear coupling calculation, hidden defect characterization parameters are extracted through multi-scale feature compression and abnormal clustering analysis, and defect space positioning and process compensation parameter adjustment suggestion output are achieved; according to the invention, the subcritical microscale latent defect can be identified, and the detection sensitivity and reliability are improved.

The invention belongs to the technical field of power semiconductor devices. The invention provides a SiC MOSFET surge current transient electrothermal coupling failure modeling method. A real packaging three-dimensional structure model is established, and material parameters are defined; dividing grids, constructing a current and solid heat transfer module, applying surge waveform data and realizing real-time coupling; carrying out transient solution to obtain temperature data, extracting a hot spot area and comparing thermodynamic critical parameters of the material; and establishing a multi-class failure mechanism model, and outputting a failure prediction result and reliability evaluation. The method is high in structural reduction degree, transient temperature rise and hot spot distribution can be accurately simulated, the problems that modeling is not accurate, transient electrothermal coupling analysis is lacked and a real failure mode cannot be reflected in the prior art are solved, the failure position, mode and threshold value can be accurately predicted, the method is suitable for reliability evaluation under the multi-surge condition, and the method is suitable for popularization and application. And the method has engineering application value and research significance.

The invention discloses a method for optimizing the contour of a contact hole and a semiconductor structure, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: introducing a silicon-containing precursor gas and a carbon-containing precursor gas on a substrate, and depositing to form a first amorphous silicon layer serving as an etching deceleration layer; and depositing on the first amorphous silicon layer to form a second amorphous silicon layer by stopping introducing the carbon-containing precursor gas and continuing introducing the silicon-containing precursor gas. Through in-situ deposition of the laminated structure of the carbon-containing layer and the pure amorphous silicon layer, the intrinsic etching selection ratio is constructed by using the property difference of materials, and an additional ion implantation step is not needed. According to the method, the technological process is simplified, the cost and the thermal budget are reduced, the etching bias load effect can be effectively improved, the contour of the contact hole is optimized, the contact hole is closer to be vertical and is uniform up and down, and therefore the yield and the reliability of the device are improved.

The invention belongs to the technical field of third-generation semiconductor material defect control. According to the method for eliminating the silicon carbide small stacking fault based on high-temperature oxidation, a silicon carbide substrate is scanned and represented in a photoluminescence mode, and the target small stacking fault is accurately recognized and positioned; cleaning the substrate to remove surface impurities, performing high-temperature oxidation treatment in a dry oxygen atmosphere, and growing an oxide layer under control; constructing a composite interface stress field at an interface by utilizing thermal expansion coefficient mismatch and reaction molar volume expansion between the oxide layer and the substrate, and driving target stacking fault atom arrangement to generate directional reconstruction, so that the target stacking fault atom arrangement is converted into a matrix standard sequence; and finally, nitric oxide auxiliary annealing is carried out, and the reconstructed lattice configuration is solidified by utilizing a nitrogen passivation effect. The method is simple in process and high in compatibility, small stacking fault can be efficiently and stably eliminated, the silicon carbide substrate crystal quality is remarkably improved, and a guarantee is provided for preparation of a high-reliability power device.

The invention discloses a wide-range switch tube leakage current detection method and system, and relates to the technical field of semiconductor device detection, and the method comprises the steps: connecting a to-be-detected NMOS switch tube with a trans-impedance amplifier, and collecting the drain current; the trans-impedance amplifier converts drain current into an output voltage signal V. The switchable feedback resistor at least comprises two feedback branches corresponding to different ranges. When it is detected that the output voltage approaches a negative output saturation threshold, a corresponding gain range is switched; before each measurement period, an analog-to-digital converter is grounded through an analog switch, system offset voltage is sampled, and a digital compensation value of switch tube leakage current is calculated and compensated; rC low-pass filtering and software notch filtering are carried out on the compensated voltage signal, and then sampling is carried out; and comparing the sampling result with a preset threshold value, and outputting a leakage current detection result. According to the invention, the accuracy of the measurement result of the drain current of the NMOS transistor is improved, and the reliability of device performance evaluation is guaranteed.