1517 results about "Reliability (semiconductor)" patented technology

The invention provides a regeneration wafer defect detection method and system based on point cloud, and belongs to the technical field of semiconductor manufacturing detection, and the method comprises the steps: carrying out the registration and fusion processing of the point cloud data of a target wafer, and obtaining the target point cloud data; performing plane fitting on the target point cloud data to determine a reference plane; performing feature extraction on the target point cloud data relative to the reference plane to obtain feature data; positioning a defect area based on the feature data, and calculating geometric parameters of the defect area; correcting the geometric parameters by using a preset error compensation model to obtain target geometric parameters; inputting the position of the defect area, the target geometric parameter and the feature data of the corresponding defect area into a defect classification model to obtain a defect type of the defect area; and generating a defect detection result of the target wafer based on the defect types, the positions, the target geometric parameters and the feature data of all the defect areas of the target wafer. According to the invention, the efficiency and reliability of regenerated wafer defect detection are improved.

The invention relates to the technical field of semiconductor photoelectronics, and discloses a multi-physics field coupling silicon-based optical interconnection chip degradation model construction method and application, and the method comprises the steps: firstly constructing a multi-physics field coupling analysis model, and quantitatively representing the coupling relation of thermodynamics, optics, electricity and material aging through an inter-field coupling equation and a material aging dynamic model; simulating field distribution of a chip key area under multi-environment stress through finite element analysis, and extracting data; then historical degradation data is collected by combining an accelerated aging test and long-term operation monitoring, and a degradation parameter prediction model is established after data processing based on machine learning; and finally, inputting a finite element result and a prediction result into a material aging dynamic model, and finally forming a multi-physics field coupling degradation model. The problems that the prior art depends on a single physical field, degradation mechanism analysis is incomplete, and service life evaluation is inaccurate are solved, and support can be provided for reliability evaluation, structure optimization and service life prediction of the silicon-based optical interconnection chip.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention discloses a solar cell performance prediction method and device based on a physical information fusion model, and relates to the technical field of computer data processing and semiconductor characterization. According to the technical scheme provided by the invention, the deep neural network architecture is adopted to perform feature extraction and fusion on the multi-dimensional spectral information, the prediction precision is improved by more than 35%, and the reliability is improved by more than 40%, so that the prediction performance is remarkably improved; an innovative physical information fusion loss function is adopted for training the model and comprises a data-driven prediction loss item and a constraint loss item based on a semiconductor device physical rule, and a prediction task and a physical principle are deeply fused, so that the prediction model can understand a physical causal relationship between spectral characteristics and device performance, and the prediction efficiency is improved. According to the method, more accurate performance prediction and better physical interpretability are realized, multiple physical constraints are adopted to standardize the prediction result, so that the model prediction result conforms to the physical principle of the semiconductor device, and the physical rationality and engineering application value of the prediction result are improved.

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

The invention discloses a rapid thermal simulation method and system for a semiconductor power assembly, and relates to the technical field of semiconductors, and the method comprises the steps: collecting a voltage V (t) signal and a current I (t) signal of the semiconductor power assembly in real time through a voltage and current sampling circuit, constructing a power pulse input sequence A, and carrying out the hot carrier accumulation analysis according to the power fluctuation change amplitude; introducing a transient thermal resistance function Zth (t), fitting the transient thermal resistance function Zth (t) with a hot carrier pulse response index Mcx after numerical integration to analyze junction temperature change caused by power pulse, and evaluating an equivalent junction temperature dynamic change rate; when the analysis result is that the thermal drift out-of-control trend exists, thermal risk analysis is carried out, and thermal risk state assessment is generated; the simulation model optimizes thermal model parameters and outputs thermal control suggestions through a rollback correction path, and the working state of the semiconductor power assembly is automatically adjusted. According to the method, real-time monitoring and effective prevention and control of thermal runaway can be realized, and the reliability and safety of the semiconductor power assembly are improved.

The invention relates to the field of semiconductor processing, and discloses a semiconductor processing contour information extraction method, device and equipment and a storage medium, and the semiconductor processing contour information extraction method comprises the steps: obtaining a to-be-processed TEM graph and a design layout of a to-be-detected wafer; searching and determining a local layout corresponding to the TEM graph to be processed in the design layout; according to the contour distribution position in the local layout, determining a corresponding preliminary screening contour imaging area in the TEM graph to be processed; and contour edge detection is carried out according to the pixel value of each pixel point in the preliminary screening contour imaging area, and contour information of the processing contour of the to-be-detected wafer in the to-be-processed TEM graph is obtained. According to the method, the accuracy and reliability of contour information extraction in the TEM graph are realized by means of the design layout of the wafer to be tested, and a reliable data basis is provided for analysis of semiconductor process quality.

The invention relates to the technical field of wafer detection, in particular to semiconductor wafer cutting section defect detection equipment and a detection method, and the semiconductor wafer cutting section defect detection equipment comprises a detection shell and a conveying shell; a carrying table is arranged in the conveying shell, and a piece taking device, a camera, a spotlight, a first rotating ring, a support and a first driving unit are arranged in the detection shell. The pick-up device is arranged in the detection shell and used for taking out the semiconductor wafer on the carrying table, the moving direction of the carrying table serves as a rotation axis, the pick-up device can rotate around the rotation axis, and the rotation angle of each time is 180 degrees; the camera is arranged on one side of the pick-up device; the spotlight is of an annular structure and is arranged on the periphery of the camera in a surrounding and sleeving mode. The first rotating ring is rotationally arranged in the detection shell along the rotating axis; the support is fixedly arranged on the first rotating ring, and the camera is arranged on the support; the first driving unit is arranged on one side of the first rotating ring. According to the invention, the precision and reliability of double-sided detection of the semiconductor wafer are improved.

The invention discloses an in-situ TEM (Transmission Electron Microscope) device sample preparation method based on a suspended thinning and parallel carrying technology, which can be used for preparing in-situ TEM samples of semiconductor two-end devices and three-end devices, and mainly solves the problems of unstable ohm contact, nonuniform thinning, low success rate and high time cost in the prior art. According to the invention, an FIB sample preparation technology is adopted, and stable and reliable ohmic contact between a sample electrode and an MEMS chip electrode is ensured through specific-angle sample extraction, suspended thinning, parallel carrying, circuit breaking treatment and an accurate electrode welding process. According to the sample prepared by the invention, the failure state of a device can be observed in real time under a transmission electron microscope, the sample has the advantages of high sample preparation success rate, good repeatability, stable electrical parameters and wide applicable chip variety, and the reliability and repeatability of in-situ TEM test data are remarkably improved.

The invention relates to the technical field of semiconductor wafer defect detection, and discloses a semiconductor wafer defect detection method and system, and the method comprises the steps: generating a spatial staggered excitation pattern, and projecting the spatial staggered excitation pattern to the surface of a semiconductor wafer, the spatial staggered excitation pattern comprising an excited region and an unexcited region; capturing an optical image of the surface of the semiconductor wafer; according to the optical image, calculating the difference between the optical signal intensity of the excited area and the optical signal intensity of the adjacent non-excited area in the optical image; according to the difference, carrying out background deduction on the optical image so as to display a potential defect signal; and identifying the manifested potential defect signal. Therefore, the method can significantly improve the sensitivity, accuracy and efficiency of semiconductor wafer defect detection, thereby effectively improving the yield and reliability of semiconductor products, and reducing the production cost.

The invention provides a Laplace-DLTS stabilization inversion method and system, and the method comprises the steps: applying a pulse bias voltage to a tested semiconductor device, and collecting a transient capacitance signal of the tested semiconductor device; the transient capacitance signal is preprocessed; performing inverse Laplacian transformation processing on the preprocessed transient capacitance signal, and introducing at least one of non-negative constraint, sparsity constraint, physical prior constraint and time window segmentation constraint in an inversion process; carrying out optimization processing on the obtained inversion result, and judging the stability of the inversion result; and extracting a deep energy level trap parameter based on the inversion result, and outputting the deep energy level trap parameter and the processed transient spectrum data. At least one, preferably at least two, constraint conditions are introduced in the inverse Laplacian inversion process, so that the influence of noise and abnormal peaks on the inversion result is effectively inhibited, and the stability, physical consistency and parameter extraction reliability of the inversion are improved.

The invention discloses an Agent task planning and workflow generation method driven by knowledge in the semiconductor field, and relates to the cross technical field of artificial intelligence and semiconductor manufacturing. According to the method, in order to solve the problems that in the prior art, a semiconductor data analysis task lacks domain knowledge support, workflow generation stability is poor, and execution links are uncontrollable, a Task-Planner and Executor-Planner double-layer framework is adopted, and accurate matching from user requirements to domain subtasks is achieved by constructing a semiconductor domain task knowledge base; a structured prompt mechanism is designed, and a directed acyclic graph workflow with complete logic is generated in combination with the fine-tuned large language model; error localization processing is introduced, and reliable execution of the workflow is guaranteed; the method can automatically complete the planning and execution of complex tasks such as yield analysis and fault diagnosis in semiconductor wafer manufacturing, packaging testing and equipment operation and maintenance, improves the data analysis efficiency and reliability, and is suitable for a high-precision semiconductor manufacturing scene.

The invention relates to a method. The invention discloses an ATE-based method for batch detection of pseudo soldering and sealing-off of chip packaging bonding, and belongs to the technical field of semiconductors. The method comprises the following steps: aiming at packaged and bonded chips, providing excitation current for each chip to be tested through an ATE test machine, and conducting an ESD (Electro-Static Discharge) diode connected with each pin of the chip; detecting the voltage drop between each pin and the pin GND; and calculating the equivalent resistance to determine whether pseudo soldering or unsoldering exists. The detection method has high practicability, is simple to operate, is very suitable for large-scale application and popularization, and has a certain promotion effect on improvement of a chip packaging test technology, improvement of chip performance reliability and chip packaging inspection.

The invention relates to the technical field of semiconductor detection and automatic packaging, discloses a vision detection and accurate placement system and method for MINI chips, and aims to solve the problems that in the prior art, due to the lack of multi-source sensing fusion and closed-loop control, the chip positioning precision is insufficient, the grabbing and placement reliability is low, and the whole-process quality monitoring is lack. The method comprises the following steps: acquiring three-dimensional coordinates and attitude data of a chip through a distance measurement detection unit; the vacuum pressure of the suction nozzle is monitored in real time to confirm the grabbing state; the actual posture of the chip and the burning station reference data are fused, a six-dimensional space compensation vector is calculated, a manipulator is driven to conduct fine adjustment, and accurate placement is achieved; and visual inspection is carried out at the discharging braid end, and comprehensive judgment of position, appearance and character recognition is completed. According to the scheme, submicron positioning correction, closed-loop grabbing control and whole-process quality monitoring are achieved, and the chip placement precision, the production yield and the automation efficiency are remarkably improved.

The invention relates to a quartz crucible coating and a preparation method thereof.The coating is of a double-layer composite structure and comprises a substrate layer and a functional layer, the substrate layer is composed of 40-65 vol% of polycrystalline silicon powder (the particle size D50 ranges from 1 micrometer to 5 micrometers) and 35-60 vol% of nanometer silica sol, and the functional layer covers the surface of the substrate layer and is composed of 50-70 vol% of polycrystalline silicon powder, 20-35 vol% of nanometer silica sol and 5-15 vol% of calcium fluoride powder (the particle size D90 is smaller than 0.5 micrometer). The preparation method comprises the following steps: preparing a substrate layer slurry and a functional layer slurry, sequentially coating the inner wall of a crucible with the slurry, drying, and sintering in an inert atmosphere according to a three-step temperature control program to finally form a coating with the thickness of 180-300 microns and the porosity of 8-15 vol%; the coating structure can avoid pollution of silicon nitride or silicon carbide particles, has excellent demolding performance, thermal stability and adhesive force, further improves the service life of a crucible and the purity of a silicon ingot, and meets the requirements of an advanced semiconductor process for cleanliness and reliability.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The invention provides a satellite disc rotating speed detection method and system of MOCVD equipment, computer equipment and a storage medium, and relates to the technical field of semiconductor detection. Weak rotating speed characteristic signals are accurately extracted from noise through time domain and frequency domain fusion and a state estimation algorithm; the detection capability and the peak position stability of the rotating speed characteristic under the strong noise background are obviously improved; by taking a fusion result as an initial value and introducing state estimation of system dynamics, millisecond-level real-time updating and high-precision rotating speed analysis can be realized; the preset system dynamics model can dynamically fuse the current observation value and the historical state, the random error caused by airflow disturbance, mechanical vibration and electromagnetic interference is effectively inhibited, the output result is smooth and stable, and the reliability is greatly enhanced.

The embodiment of the invention discloses a semiconductor device service life evaluation method based on a power cycle test and related equipment, and the method comprises the steps: dividing semiconductor devices produced by the same factory in the same batch into two parts, and executing a second-level power cycle test on one part, a millisecond-level power cycle test is firstly executed on the other part, and then a second-level power cycle test is executed on the other part; establishing a first life model according to one test result, and establishing a second life model according to the other test result; and calculating a third life model corresponding to the millisecond power cycle test according to the first life model and the second life model, and performing life evaluation on the semiconductor device according to the third life model. By adopting the embodiment of the invention, the reliability assessment requirement of the power semiconductor device in the future can be met, and the aims of accelerating aging and meeting the actual working condition can be fulfilled, so that an important reference significance is provided for the research of the reliability test of the device and the assessment of the actual life.

Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The redistribution structure includes a first redistribution structure portion physically and electrically connected to the first semiconductor die, a second redistribution structure portion physically and electrically connected to the second semiconductor die, and a dummy bump region positioned between and electrically isolated from the first redistribution structure portion and the second redistribution structure portion.

The invention provides a silicon carbide chip performance evaluation method and evaluation system, and relates to the field of semiconductor testing. Nonlinear disturbance components are separated from dynamic response data; constructing a link transmission compensation function based on the nonlinear disturbance component, and determining dynamic characteristic parameters through the link transmission compensation function and the dynamic response data; performing multi-dimensional spectrum analysis on the dynamic characteristic parameters to obtain high-frequency performance parameters, and further performing thermal energy efficiency derivation on the silicon carbide chip according to the high-frequency performance parameters to obtain an energy efficiency trend and energy efficiency thermal coupling characteristics; performing multi-working-condition pulse excitation on the silicon carbide chip according to the deviation abnormal value to obtain a multi-dimensional compensation matrix; adaptive coupling compensation is carried out on the energy efficiency trend and the energy efficiency thermal coupling characteristics based on the multi-dimensional compensation matrix, then a performance evaluation data set of the silicon carbide chip is obtained, multi-dimensional adaptive coupling compensation based on abnormal value driving can be achieved, and the reliability of performance evaluation of the silicon carbide chip is improved.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

The invention discloses a wafer high-precision alignment mechanism, and relates to the technical field of semiconductor manufacturing and packaging, the wafer high-precision alignment mechanism comprises a casing and a vertical box integrally and fixedly connected to the upper part of the rear side of the casing, a cantilever is fixedly connected to the center of the upper part of the front side of the vertical box, and a detection mechanism for performing optical detection on a wafer is arranged between the cantilever and the upper wall of the casing. A circular movable hole is formed in the upper wall of the machine shell, the central axis of the movable hole is located on the central axis face of the cantilever, and an alignment mechanism used for adjusting the position of the wafer is arranged in the movable hole. By arranging the cleaning assembly and adopting a closed-loop design combining blowing and suction, the invention has the following remarkable beneficial effects: firstly, the structure forms an air curtain barrier with directional flow through the synergistic effect of positive-pressure blowing and negative-pressure suction, not only can dust on the mirror surface of the optical probe be continuously removed, but also pollutants can be actively discharged from the inside of equipment, so that the cleaning efficiency is greatly improved; the secondary pollution is fundamentally avoided, and the thoroughness and reliability of cleaning are greatly improved.

The application relates to a semiconductor package failure detection method based on high harmonic amplitude-phase demodulation, and relates to the technical field of semiconductor package detection. The application is used to solve the problems existing in the prior art semiconductor package defect detection method. The application applies a current excitation to a measured semiconductor package to make the semiconductor package generate heat, and collects a thermal image sequence of the semiconductor package; a same-frequency quadrature reference signal of each harmonic of the thermal image sequence is synthesized according to the current excitation; a demodulation phase is extracted by using the same-frequency quadrature reference signal; a dominant path is extracted according to a fourth-order demodulation phase; the dominant path is verified according to a fifth-order and sixth-order demodulation phase; if the dominant path is verified to be correct, it is determined that the measured semiconductor package has a failure state corresponding to the dominant path; otherwise, the thermal image sequence of the measured semiconductor package is collected again for detection. The application is suitable for the fields of semiconductor package manufacturing and testing, quality and reliability control, failure analysis and the like.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention belongs to but not limited to the technical field of power semiconductor packaging, and discloses a packaging structure of a power semiconductor device. The power module comprises a lead frame, a plastic package body, a base island, a bonding wire and a semiconductor chip assembly, a first power unit and a second power unit are integrated, the first unit comprises two driving ICs, six IGBTs and six FRD chips, the second unit comprises two driving ICs and six MOS chips, 46 pins are provided, and functions are clearly divided. All the IC chips and the FRD chips are arranged on the same base island, the back faces of the chips are welded to the base island, and the front faces of the chips are connected with pins in a standard mode through bonding wires. The structure solves the problems of complex packaging layout, disordered connection and the like in the prior art, can drive the compressor and the fan respectively, realizes high integration level and compact layout, shortens an electric connection path, reduces parasitic parameters, reduces the overall size and cost, and improves reliability and engineering compatibility.

The invention discloses a semiconductor sealing ring irregular surface contour detection method and system, and relates to the technical field of semiconductor sealing rings, and the method comprises the following steps: marking contour data collected in real time in historical detection data as to-be-detected contour data; dividing the to-be-measured contour data into environment sensitive contour data and environment tolerant contour data according to the environment response deformation characteristics, and processing the environment sensitive contour data and the environment tolerant contour data to obtain a to-be-measured environment sensitive ratio; performing environment dimension feature division on the to-be-measured contour data according to the to-be-measured environment sensitivity ratio to obtain an environment dimension scheme; acquiring a standard environment deformation reference of the contour data according to the environment dimension scheme; processing and analyzing the to-be-measured contour data and the standard environment deformation reference to obtain a coincidence environment time sequence comparison result and a difference environment time sequence comparison result; the overall quality and reliability of the semiconductor sealing ring are improved.

The invention relates to the technical field of semiconductor packaging, and discloses a bonding wire welding method based on bare chip interconnection, and the method comprises the steps: collecting and fusing acoustic response and optical reflection signals of a bonding interface in real time through a multi-mode in-situ sensing mechanism integrating acoustic resonance and surface plasmon resonance; dynamically calculating the thickness, the mechanical coupling deformation and the energy dissipation state of the intermetallic compound layer; and the ultrasonic power and the bonding force are subjected to closed-loop adjustment in combination with a model prediction control algorithm, so that the welding process is evolved along a preset optimal physical path all the time. The system comprises a multi-mode sensing welding head, a synchronous data acquisition module, a state resolving module and a self-adaptive control module. The transparent and intelligent welding process is realized, and the bonding consistency, reliability and yield of high-density interconnection are remarkably improved.

The invention discloses a multi-mode fusion power semiconductor module full-automatic detection system and method, relates to the technical field of semiconductor testing, constructs a multi-topology loading module, and realizes mechanical load testing under a frequency converter working condition, electrical load simulation under a grid-connected working condition and static electrical parameter testing. And covering dynamic and static performance detection of the module in a multi-application environment. A multi-source temperature monitoring and weighted fusion technology is introduced, and precise regulation and control of local junction temperature, surface temperature and radiator temperature of the module are realized. Dynamic switch characteristics are extracted from various collected data through wavelet transformation, and module failure probability prediction is completed in combination with a Weibull life model. Automation of whole-process data analysis and detection report generation is achieved, and the test efficiency and the evaluation intelligent level are improved. The method is suitable for multi-scene performance evaluation and reliability analysis of the power semiconductor module.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a plurality of MEMS standard devices and at least one MEMS test device on the front surface of the substrate, enabling a vibrating diaphragm of the MEMS test device to be provided with an opening, and enabling vibrating diaphragms of the MEMS standard devices not to be provided with an opening; the back surface of the substrate is provided with a back cavity forming area corresponding to each device; forming a gas guide groove in the back surface of the substrate, wherein the gas guide groove is connected with the MEMS standard device and the back cavity forming area of the MEMS test device; a back cavity is formed in a back cavity forming area on the back face of the substrate, and the back cavities of the MEMS standard device and the MEMS test device are communicated through a gas guide groove. According to the invention, through the arrangement of the air guide groove, the diaphragm in the MEMS standard device can be prevented from being absorbed or even broken, so that the CP test can be carried out on the MEMS standard device at the delivery end, and the reliability of the product is improved.

The invention discloses a full-automatic life test system for an isolation device, which belongs to the field of reliability test of semiconductor devices, and comprises a system host used for providing a test environment and bearing a plurality of test channels; the high-low voltage isolation conversion module is arranged corresponding to each test channel and is used for switching between a high-voltage aging loop and an insulation resistance measurement loop of each channel; the real-time leakage current monitoring module is used for continuously monitoring the leakage current of each isolation device in the high-voltage aging process; the precision measurement and data acquisition module is used for carrying out insulation resistance measurement on the isolation device in a measurement mode; the central control and software system module is respectively connected with the high-low voltage isolation conversion module, the real-time leakage current monitoring module and the precision measurement and data acquisition module, and the central control and software system module is used for automatically triggering and controlling an insulation resistance measurement process according to leakage current data, judging the state of a device according to a measurement result, and outputting the state of the device. And aging and stopping of the test channel are managed.