Stacked via-stud with improved reliability in copper metallurgy

a copper metallurgy and via-stud technology, applied in the direction of semiconductor/solid-state device details, thin material processing, semiconductor devices, etc., can solve the problems of increasing crack propensity, increasing crack generation, and increasing the proneness of stacked via-studs to cracks, so as to facilitate redundant paths and increase the flexibility of stacked via-studs
US20060014376A1Inactive Publication Date: 2006-01-19GLOBALFOUNDRIES INC
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
GLOBALFOUNDRIES INC
Publication Date
2006-01-19
Estimated Expiration
Not applicable · inactive patent

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Abstract

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.
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Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a new semiconductor process and integrated circuit structure, and more particularly, to a new process and structure which provides stacked via-studs, in multilevel interconnection wiring of semiconductor devices with high conductivity copper metallurgy and low-k dielectric, with improved mechanical stability under large thermal excursions.

[0003] 2. Description of the Prior Art

[0004] In order to meet the ever increasing demand for increased device density and performance, a semiconductor technology consisting of a low-k dielectric material and an interconnection wiring of copper metallurgy, defined by a dual damascene method, is the present day choice. Because, dry air has the theoretically lowest dielectric constant of one (1), most low-k materials such as aerogels, hydrogen silsesquioxane (HSQ), fluorinated organic polymers (e.g., SiLK, a trade mark of Dow chemical Co., ...

Claims

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