Stacked via-stud with improved reliability in copper metallurgy

Abstract

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a new semiconductor process and integrated circuit structure, and more particularly, to a new process and structure which provides stacked via-studs, in multilevel interconnection wiring of semiconductor devices with high conductivity copper metallurgy and low-k dielectric, with improved mechanical stability under large thermal excursions.

[0003] 2. Description of the Prior Art

[0004] In order to meet the ever increasing demand for increased device density and performance, a semiconductor technology consisting of a low-k dielectric material and an interconnection wiring of copper metallurgy, defined by a dual damascene method, is the present day choice. Because, dry air has the theoretically lowest dielectric constant of one (1), most low-k materials such as aerogels, hydrogen silsesquioxane (HSQ), fluorinated organic polymers (e.g., SiLK, a trade mark of Dow chemical Co., ...

Examples

Embodiment Construction

[0048] The present invention is generally related to methods for forming metal filled via-studs and conductor lines on a substrate where the via-studs and conductor lines are formed using a dual damascene method, and preferably copper metallurgy and low-k dielectric material. The present invention has particular relevance to stacked via-stud schemes which particularly use low strength low-k dielectric materials and incorporate a cantilever structure within the stacked via-stud which may serve as an effective thermal fatigue crack stop.

[0049] Particularly referring to FIG. 2, there is shown a semiconductor substrate 10 above which a sequence of dielectric layers 111, 112, 113 is deposited, subsequently patterned and metallized to form a first level of interconnection. It should be understood that a plurality of semiconductor devices may be formed in the substrate and, although not shown, are provided with a local interconnect line 101, typically tungsten with underlayers of titanium...

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a new semiconductor process and integrated circuit structure, and more particularly, to a new process and structure which provides stacked via-studs, in multilevel interconnection wiring of semiconductor devices with high conductivity copper metallurgy and low-k dielectric, with improved mechanical stability under large thermal excursions.

[0003] 2. Description of the Prior Art

[0004] In order to meet the ever increasing demand for increased device density and performance, a semiconductor technology consisting of a low-k dielectric material and an interconnection wiring of copper metallurgy, defined by a dual damascene method, is the present day choice. Because, dry air has the theoretically lowest dielectric constant of one (1), most low-k materials such as aerogels, hydrogen silsesquioxane (HSQ), fluorinated organic polymers (e.g., SiLK, a trade mark of Dow chemical Co., ...

Examples

Embodiment Construction

[0048] The present invention is generally related to methods for forming metal filled via-studs and conductor lines on a substrate where the via-studs and conductor lines are formed using a dual damascene method, and preferably copper metallurgy and low-k dielectric material. The present invention has particular relevance to stacked via-stud schemes which particularly use low strength low-k dielectric materials and incorporate a cantilever structure within the stacked via-stud which may serve as an effective thermal fatigue crack stop.

[0049] Particularly referring to FIG. 2, there is shown a semiconductor substrate 10 above which a sequence of dielectric layers 111, 112, 113 is deposited, subsequently patterned and metallized to form a first level of interconnection. It should be understood that a plurality of semiconductor devices may be formed in the substrate and, although not shown, are provided with a local interconnect line 101, typically tungsten with underlayers of titanium...

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