Impedance matching network (104, 204, 400, 500), comprising: a first
signal terminal (212, 302, 402, 502) configured to receive a
signal from a source circuit (102, 202); a second
signal terminal (214, 304, 404, 504) configured to provide the signal to a
load circuit (106, 206); a series
branch comprising a variable capacitive component (208, 300, 350, 401, 501) between the first signal terminal (212, 302, 402, 502) and the second signal terminal (214, 304, 404, 504), wherein the variable capacitive component (208, 300, 350, 401, 501) comprises a plurality of series-connected capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508), wherein at least one of the capacitive sections comprises a switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprising a stack of series-connected transistors (352a...352N), and a control component (210, 426, 526) configured to control a
capacitance of the variable capacitive component (208, 300, 350, 401, 501) by controlling at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) based on a predetermined
algorithm, wherein the at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprises a first capacitive section comprising a first switching element comprising a stack of series-connected transistors, and a second capacitive section comprising a second switching element comprising a stack of series-connected transistors, wherein the control component (210, 426, 526) is configured to switch the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching elements (316, 318, 320, 416, 418, 420, 516, 518, 520) on or off in series in steps of one in a predetermined direction according to the predetermined
algorithm in order to avoid
voltage overload.