48 results about "Capacitance multiplier" patented technology

A phase detector (PD) generates an up / down signal based on the phase error between data and clock signals input to the phase detector. A voltage controlled oscillator (VCO) generates the clock signal. The up / down signal is applied to a proportional charge pump and a truncated version of the up / down signal is applied to an integral charge pump. The proportional charge pump generates a first voltage for a first time period across a resistor based on the up / down signal, while the integral charge pump generates a second voltage for a second time period across a capacitor based upon the truncated version of the up / down signal and the sampling rate of the data signal by the PD. The second time period is less than the first time period. The first and second voltages are combined and applied to the VCO to drive the clock signal to synchronization with the data.

An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

The invention discloses an on-chip full integration compensation network based on a constant transconductance amplifier and a capacitance multiplier, which can be flexibly applied to a TYPE-I, a TYPE-II and a TYPE-III compensation network structure of a switching DC-DC converter. The on-chip full integration compensation network comprises an impedor Z1, an impedor Z2 and an operational amplifier AMP, wherein an input end of the impedor Z1 is connected to input voltage Vin, and an output end of the impedor Z1 is connected to a first input end of the operational amplifier AMP; an input end of the impedor Z2 is connected to the first input end of the operational amplifier AMP, and an output end of the impedor Z2 is connected to an output end of the operational amplifier AMP; and a second input end of the operational amplifier AMP is connected to reference voltage Vref. According to the invention, the constant transconductance amplifier is adopted to act as an active resistor, the capacitance multiplier acts as an active capacitor, discrete devices such as a passive resistor, a capacitor and the like adopted by the impedor Z1 and the impedor Z2 in a traditional compensation network, thereby realizing on-chip integration, and improving the system integration degree; the on-chip full integration compensation network is simple in structure and easy to design, and has excellent process corner resisting stability; and the design is universal, thereby being convenient for popularization and expansion.

A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging / discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

A variable capacitance circuit on an integrated circuit comprises a MOS transistor, and a capacitance multiplier connected to one end of a channel of the MOS device. A MOS device is formed in series with an inductance, and a capacitance multiplier is formed to be connected to a node between the MOS device and the inductance.

The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplier has less parasitic components, occupies a smaller chip area with higher simulated capacitance value.

The invention discloses a high-gain isolated type direct current-direct current (DC-DC) convertor for fuel-cell power generation and belongs to the technical field of convertors. The convertor comprises an input current multiplier, a switch capacity multiplier, a clamping circuit and a transformer. The input current multiplier comprises a first input inductor, a second input inductor, a first switch tube and a second switch tube. The clamping circuit comprises a clamping capacitor Cc, a first clamping switch tube and a second clamping switch tube. The switch capacity multiplier comprises a first resonant capacitor, a second resonant capacitor, a first output capacitor C2a, a second output capacitor C2b and four rectifier tubes. The primary side of the transformer is connected with the input current multiplier and the clamping circuit respectively, and the secondary side of the transformer is connected with the switch capacity multiplier. When high-gain isolated type DC-DC convertor is applicable to the fuel-cell power generation and grid connection, the convertor needs an occasion with high gain, small input current ripple and high efficiency, and the convertor is also applicable to other types of new energy power generation including low-output-voltage power generation and the like.