4 results about "Capacitance multiplier" patented technology

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

The invention provides an operational amplifier with a built-in capacitance multiplier. The operational amplifier comprises an input transistor, a current mirror circuit and a capacitor. The input transistor generates an input current according to an input signal, and the current mirror circuit generates a current mirror output current at a current output terminal of the current mirror circuit according to a current mirror input current corresponding to the input current received by a current input terminal of the current mirror circuit. Wherein the current output terminal is coupled to an amplifier output terminal of the operational amplifier. Furthermore, a first terminal of the capacitor is coupled to the amplifier output terminal, and a second terminal of the capacitor is coupled to the current input terminal, such that an equivalent capacitance value of the capacitor at the amplifier output terminal is multiplied by the current mirror circuit.

A grounded positive and negative capacitance multiplier including a first number (i) of current conveyors connected in a cascaded manner. Each current conveyor includes a transconductance amplifier (OTA), a feedback network (FBN) including a second number (N) of CMOS inverters, and a feedforward network (FFN) including a third number (M) of CMOS inverters. A base capacitor is connected between a first input terminal of a first current conveyor of the cascaded current conveyors and a ground node. A multiplied capacitance is obtained between a second input terminal of the first current conveyor and the ground node, with a capacitance value given by(-MN)i*CB.CB represents a capacitance of the base capacitor. When i is an odd number, the multiplied capacitance has a negative value, and when i is an even number, the multiplied capacitance has a positive value.

An integrated circuit may include one or more circuits coupled to capacitance multiplier circuitry. The capacitance multiplier circuitry may include a capacitor, fixed and tunable resistances, and a transconductance circuit. The tunable resistance can be adjusted to control the overall capacitance of the capacitance multiplier circuitry. The transconductance circuit may include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component may be a diode-connected transistor, a direct shorting wire, a resistor, an inductor, or a current source. The second electrical component may be a current source, a direct shorting wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuitry can provide a large adjustable amount of capacitance without a voltage drop and without consuming a large amount of power.