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30results about How to "Increase effective capacitance" patented technology

High-density low-parasitic capacitor

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Tailorable battery cell, battery and manufacturing method thereof

The invention discloses a cuttable battery cell, a battery and a manufacturing method of the cuttable battery cell, and relates to the technical field of battery structures. The cuttable battery cell comprises at least two electrode units, each electrode unit comprises an electrode layer and a current collection layer which are arranged in a stacked mode, each electrode layer comprises a first electrode body and a second electrode body, and an electrode arm of each first electrode body is meshed with an electrode arm of each second electrode body; the adjacent electrode units are connected through an electric connection structure, and the electric connection structure is used for cutting to split the adjacent electrode units; the adjacent electrode units are connected through an electric connection structure for cutting. The pole arm of the first electrode body is meshed with the pole arm of the second electrode body, so that the area utilization rate is improved, the ion transmission distance is shortened, the internal resistance of the battery is reduced, and the effective capacitance can be improved. In addition, through connection of the electric connection structure for tailoring, the tailorable battery cell can be conveniently disassembled, customized tailoring is facilitated, and the battery with the required capacity can be rapidly assembled.
Owner:ZINERGY SHENZHEN LTD

High-density low-parasitic capacitor

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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