High-density low-parasitic capacitor

A capacitor device, low parasitic technology, applied in circuits, electrical components, electro-solid devices, etc., can solve problems such as restricting applications and affecting circuit performance, reducing additional power consumption, improving performance, and achieving significant effects
CN101789430BActive Publication Date: 2012-05-30INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Patents(China)
Current Assignee / Owner
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
Publication Date
2012-05-30

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.
Need to check novelty before this filing date? Find Prior Art

Description

Technical field

[0001] The present invention relates to the technical field of integrated circuits, in particular to a high-density and low-parasitic capacitor device, which can be applied to multiple sub-fields under the integrated circuit, such as memory, RFID, charge pump and the like. Background technique

[0002] How to maximize the use of integrated circuit technology to produce high-density, low-parasitic, and high-precision capacitors is crucial to all areas of integrated circuit design. High-density capacitors can greatly reduce the chip area and cost; low-parasitic capacitors can reduce the additional power consumption of the chip; high-precision capacitors can greatly improve the performance of the chip; and high-performance compatible with MOS technology The capacitor can greatly reduce the additional manufacturing cost of the chip.

[0003] At present, the capacitors compatible with MOS technology mainly include MOS capacitors, MIM capacitors, and capacitors formed be...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More