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High-density low-parasitic capacitor

A capacitor device, low parasitic technology, applied in circuits, electrical components, electro-solid devices, etc., can solve problems such as restricting applications and affecting circuit performance, reducing additional power consumption, improving performance, and achieving significant effects

Active Publication Date: 2012-05-30
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For capacitors implemented by NMOS tubes, one end of the capacitor must be grounded, which limits its application
For the capacitance realized by PMOS transistor, due to the large parasitic capacitance between the N well and the P substrate, the parasitic capacitance is usually about 10% to 20% of the effective capacitance, which will cause additional power consumption in the circuit and affect the circuit. performance

Method used

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Embodiment Construction

[0027] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the present invention in detail with reference to specific embodiments and drawings.

[0028] The high-density and low-parasitic capacitor device proposed by the present invention firstly maximizes the capacitance per unit area, and secondly can effectively reduce the parasitic capacitance from the N well to the P substrate in the PMOS capacitor. In addition, the present invention uses The special interlayer metal interconnection structure can maximize the capacitance between the same metal layer and the capacitance between the through hole and the through hole. As the feature size of the process decreases, the lithography accuracy increases, and the number of metal layers increases, The distance between the metal layer and the metal layer, and the distance between the through hole and the through hole can be further reduced, and the effecti...

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PUM

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Abstract

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.

Description

Technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to a high-density and low-parasitic capacitor device, which can be applied to multiple sub-fields under the integrated circuit, such as memory, RFID, charge pump and the like. Background technique [0002] How to maximize the use of integrated circuit technology to produce high-density, low-parasitic, and high-precision capacitors is crucial to all areas of integrated circuit design. High-density capacitors can greatly reduce the chip area and cost; low-parasitic capacitors can reduce the additional power consumption of the chip; high-precision capacitors can greatly improve the performance of the chip; and high-performance compatible with MOS technology The capacitor can greatly reduce the additional manufacturing cost of the chip. [0003] At present, the capacitors compatible with MOS technology mainly include MOS capacitors, MIM capacitors, and capacitors formed be...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/08H01L29/94H01L29/92
Inventor 冯鹏吴南健
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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