32results about How to "Improve lithography precision" patented technology

The invention discloses suspension shakeproof equipment. The equipment comprises a shakeproof suspension table which has a rigid working state and a flexible shakeproof suspension working state. The shakeproof suspension table comprises a shake isolation cavity which is filled with media, and a mounting foundation is arranged on the media. A protected device is connected with the mounting foundation to be placed on the shakeproof suspension table, and under the rigid working state, the protected device is in rigid connection to the bottom of the shake isolation cavity; and under the flexible shakeproof suspension working state, the protected device is separated from the bottom of the shake isolation cavity.

The invention provides a manufacturing method of an electric testing structure for detecting through holes. When a layout is designed, a through hole graph is connected with the overlapping area of a plurality of adjacent metal graphs in an intersection mode, the through hole graph size is larger than the target through hole size, a through hole pattern subsequently formed in optical resist is enabled to be larger than a target through hole graph in size, and therefore a photo-etched technical window is widened, and the photoetching resolution and the photoetching precision are improved; besides, a hard mask layer serves as a mask, and an upper layer metal pattern in the hard mask layer is etched into an etched barrier layer and an upper dielectric layer so that a target through hole pattern can be formed; the target through hole size is determined by the size of the upper metal pattern in the hard mask layer and the through hole size jointly and not determined by the size of the through hole graph in the optical resist, and therefore target through holes with smaller intervals can be obtained without splitting the through hole graph, the technical window is widened, and the photoetching resolution ratio is increased.

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.