32results about How to "Improve lithography precision" patented technology

Disclosed are a semiconductor etching device and an etching method of a semiconductor structure. The etching method includes: a etching process with a first bias power source is utilized to etch a to-be-etched material layer, and the first bias power source generates continuous bias power to form a first opening which does not expose a etching blocking layer; and then a etching process with a second bias power source is utilized to etch the first opening, and the second bias power source generates pulse bias power until the etching blocking layer is exposed to form a second opening. Due to the fact that the continuous bias power is utilized to form bias voltage for etching firstly, side wall appearance is good, and etching selection ratio to a photo layer is high. The continuous bias power is switched into pulse bias power to form bias voltage for etching in prior to exposure of the etching blocking layer, so that cuts are avoided from being formed at the side wall bottom, close to the etching blocking layer, of the to-be-etched material layer.

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.

The invention discloses an alignment mark and its alignment method. The alignment mark includes a set of main marks formed on a semiconductor substrate, the main mark is composed of N groups of sub-marks, and the N groups of sub-marks Formed in N layers of film layers on the substrate, N is the number of layers that need to be aligned in this photolithography process; each group of sub-marks includes the first sub-mark in the horizontal direction and the second sub-mark in the vertical direction; the The first sub-marks are two groups of gratings in the horizontal direction, and the second sub-marks are two groups of gratings in the vertical direction. In this way, it can be aligned with multiple layers during alignment, thereby improving photolithographic precision and device yield.

A vacuum drying apparatus comprises a vacuum chamber provided with an exhaust vent and a chamber door, a vacuum pumping apparatus in communication with the exhaust vent, and a heating assembly disposed in the vacuum chamber. A vacuum drying method by using the vacuum drying apparatus comprises: when vacuum drying is performed on a substrate coated with a photoresist, simultaneously performing the heating and vacuum drying on the photoresist, the vacuum degree preferably ranging from 26Pa to 500Pa during the drying, and the heating temperature preferably ranging from 30 to 90 degrees centigrade, so as to produce less hardening films, thereby reducing the residual amount of a solvent in the photoresist, and improving the photolithographic accuracy.

The invention provides a wafer exposure method. When the wafer is exposed, firstly, the alignment mark area on the glued wafer is exposed through the first mask plate, and the development operation is carried out on the alignment mark area, so that when the secondary exposure is carried out, the alignment mark in the alignment mark area on the wafer can be clearly exposed, and exposure operation is carried out at the moment, so that the wafer can be accurately positioned, and the photoetching precision is effectively improved.

The invention relates to the technical field of photoetching machines, in particular to a photoetching machine system and a photoetching method. The photoetching machine system comprises a light source module, wherein the light source module can emit at least two energy light beams; the energy beam adjusting module is used for adjusting the wavelength and energy of the energy beam; the optical assembly module is used for carrying out collinear axis combination and focusing on the energy light beams to form Bessel light beams; the four-wave mixing light emitting module is used for providing four-wave mixing blue light, and the four-wave mixing blue light and the Bessel beam are subjected to collinear axis combination and focusing to form a short-wave energy beam; the movement assembly module comprises a sample table and an intelligent manipulator, the sample table is set to be in a position moving state, the intelligent manipulator is used for adjusting the position of a sample to be etched on the sample table, the line width of a photoetching light beam can be reduced infinitely through the system, the light beam can be reduced to 5nm, 3nm, 2nm or even lower, and the accuracy of photoetching is improved. And the power consumption is reduced while the photoetching precision is improved.

The invention provides a small-spacing close-packed vertical cavity surface emitting laser and a preparation method thereof. The laser includes a substrate, an epitaxial layer, mesas prepared on the epitaxial layer, upper electrodes and a lower electrode. The multiple mesas are arranged on the surface of one side of the epitaxial layer. Any mesa forms a light emitting point of the epitaxial layer.Any mesa is provided with upper electrodes thereon. The lower electrode is arranged on the surface of one side of the substrate. The center spacing between adjacent mesas is 8-20 microns, and the edge spacing between adjacent mesas is 0.5-5 microns. A layer of silicon oxide, silicon nitride or other dielectric material is deposited on the back of the epitaxial wafer. By adjusting the thickness and stress level of the material, the warpage of the epitaxial wafer is reduced. Therefore, the lithography precision in the manufacture of the small-spacing close-packed vertical cavity surface emitting laser is improved, and the preparation of a small-spacing close-packed vertical cavity surface emitting laser is realized.

Disclosed are a semiconductor etching device and an etching method of a semiconductor structure. The etching method includes: a etching process with a first bias power source is utilized to etch a to-be-etched material layer, and the first bias power source generates continuous bias power to form a first opening which does not expose a etching blocking layer; and then a etching process with a second bias power source is utilized to etch the first opening, and the second bias power source generates pulse bias power until the etching blocking layer is exposed to form a second opening. Due to the fact that the continuous bias power is utilized to form bias voltage for etching firstly, side wall appearance is good, and etching selection ratio to a photo layer is high. The continuous bias power is switched into pulse bias power to form bias voltage for etching in prior to exposure of the etching blocking layer, so that cuts are avoided from being formed at the side wall bottom, close to the etching blocking layer, of the to-be-etched material layer.

The invention relates to a two-dimensional electronic material device and a mixed photoetching method thereof, wherein the method comprises the following steps: forming at least one lead metal layer on a substrate, and performing optical photoetching on the at least one lead metal layer so as to form at least one layer of lead figures, wherein an uppermost layer comprises a plurality of upper layer leads, and a grid electrode, a source electrode and a drain electrode are respectively connected with one upper layer lead; forming an electrode metal layer; performing the optical photoetching on the electrode metal layer so as to form a transistor region; performing electron-beam photoetching on the electrode metal layer so as to form the figures of the grid electrode, the source electrode and the drain electrode; forming a grid dielectric layer; performing the optical photoetching on the grid dielectric layer so as to form the figure of the grid dielectric layer; forming the figure of a two-dimensional electronic material layer; and forming the figure of an ohmic contact layer. The device is capable of eliminating or decreasing the destruction of intrinsic properties of the two-dimensional electronic material, capable of greatly improving the photoetching precision of small-size devices based on guaranteeing the process cost and improving the performance of the devices, and capable of saving the processing time based on guaranteeing the processing precision.

The invention relates to the technical field of semiconductor manufacturing, and discloses a NOR flash memory manufacturing method, circuit and application thereof. The method comprises the steps that on the basis of a wafer of a NOR flash memory circuit with a flash memory unit and three metal layers, a third metal layer is covered with a fourth metal layer communicated with the third metal layer. The method disclosed in the invention is compatible with the existing process. The metal wiring requirement of the Nor flash memory chip with more complex functions can be met, feasible preconditions are provided for arranging more aluminum pads to meet the requirement of advanced packaging pressure welding, and the practical value in practical significance is achieved.

A method to improve vibration isolation in semiconductor process level inhibits vibration frequencies transmitted through building structure from production tools, pumps, compressors, chillers, AHUs (Air Handling Units), and footfalls traffic on raised floor system on to tool pedestals and pads from affecting semiconductor fabrication processes. Rapid advancement and technological evolution in semiconductor industry foresee the imminent requirements for decrease in semiconductor chip node sizes to single digit nanometer. Dealing with such advancements, the tool pedestal systems are also requiring tighter specifications for stiffness and vibration isolation / reduction. Some key tools used in the semiconductor fabrication process require improved barrier from electromagnetic interference (EMI), as the disturbance from EMI degrade the performance of semiconductor processing tools that are key to the fabrication process and production yield rate.

The invention provides a manufacturing method of an electric testing structure for detecting through holes. When a layout is designed, a through hole graph is connected with the overlapping area of a plurality of adjacent metal graphs in an intersection mode, the through hole graph size is larger than the target through hole size, a through hole pattern subsequently formed in optical resist is enabled to be larger than a target through hole graph in size, and therefore a photo-etched technical window is widened, and the photoetching resolution and the photoetching precision are improved; besides, a hard mask layer serves as a mask, and an upper layer metal pattern in the hard mask layer is etched into an etched barrier layer and an upper dielectric layer so that a target through hole pattern can be formed; the target through hole size is determined by the size of the upper metal pattern in the hard mask layer and the through hole size jointly and not determined by the size of the through hole graph in the optical resist, and therefore target through holes with smaller intervals can be obtained without splitting the through hole graph, the technical window is widened, and the photoetching resolution ratio is increased.

Provided are a micromechanical chip test probe card and a method of fabricating same. A cantilever beam pattern (20) is defined in an SOI substrate. A blind hole (105) whose inner wall is insulated is fabricated on a floating end (201) of a cantilever beam. A probe (107) is fabricated in the blind hole (105). A metal lead (108) is fabricated on the surface of the cantilever beam. A solder ball (112) is fabricated on the fixed end (202) of the cantilever beam. SOI is etched on the front surface to form a cantilever beam structure. The solder ball (112) is inversely installed in a ceramic substrate (114). A silicon substrate (101) is etched from the bottom surface to release the cantilever beam and complete the preparation. The advantages of the micromechanical chip test probe card and the method of fabricating same are as follows: the processing precision is high; the processing technique is simple; the mechanical strength of the fabricated test probe card is high; probes can be arranged based on the pin position distribution of a chip to be tested. The fabricating technique is compatible with a conventional CMOS technique and a micromachining technique and is suitable for industrial production.

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.

The invention discloses a step-and-scan photoetching machine's isolation system simulation test device; it divides the whole test device into the internal world and the outside world. The outside world mostly complete the simulation of the photoetching machine's precision scanning movements, it lets the workpiece platform and the mask plate have the curve movement according to the schedule speed and acceleration, it completely reappears the true photoetching machine's step-and-scan movement, the internal world is mainly to install the optics system and the workpiece platform and the mask plate, and finishes the last photoetching service. Internal world and the outside world can be joined by the six degrees of freedom precision initiative vibration damper, it depresses the vibration of that the outside world passes to the internal world and this can ensure the internal world's quiet. The invention can let the core part-installation source system's work platform is in the range that the design allows. It improves the silicon's photoetching precision, at the same time; it has precise positioning and synchronous control of step-and-scan photoetching machine's isolation system simulation test device.