31results about How to "Good sidewall morphology" patented technology

Provided is a self-aligned double patterning formation method. The method comprises the following steps: a material layer to be etched is provided; a bottom part antireflective layer and a photo-resist layer which are soluble in a developing solvent are formed on the surface of the material layer to be etched; exposure and developing are synchronously performed on the bottom part antireflective layer and the photo-resist layer so that a patterned sacrificial bottom part antireflective layer and a sacrificial photo-resist layer are formed; first covering film material layers are formed on the surface of the material layer to be etched, the side wall surfaces of the sacrificial bottom part antireflective layer and the sacrificial photo-resist layer and the surface of the sacrificial photo-resist layer; the first covering film material layers are back-etched so that first covering film patterns are formed; and the sacrificial bottom part antireflective layer and the sacrificial photo-resist layer are removed. The bottom part antireflective layer and the photo-resist layer after exposure are synchronously soluble in the developing solvent so that the sacrificial photo-resist layer does not need to be utilized as a covering film to etch the bottom part antireflective layer, and one step in etching technology is saved. Besides, side wall appearance of a first covering film pattern is great so that the side wall appearance of the finally formed etching pattern is great.

A method for forming a semiconductor device includes the steps of providing a material layer to be etched, wherein material layer to be etched has a barrier layer; forming a plurality of discrete sacrificial layers on the surface of the barrier layer; forming a first sidewall material layer on the top surfaces and the sidewall surfaces of the sacrificial layers, and the surface of the barrier layer; etching the first sidewall material layer until exposing the surface of the barrier layer and top surfaces of the sacrificial layers, forming a first side wall on the sidewalls of the sacrificial layers, with an etching selection ratio of the first sidewall material layer to the barrier layer being greater than or equal to 10; and after removing the sacrificial layers, etching the barrier layerand the material to be etched by using the first sidewall as a mask. The method of forming the semiconductor device improves the performance of the patterns in the semiconductor device.

The invention provides a formation method of a semiconductor structure. The formation method comprises the steps that a first opening is formed in a dielectric layer, and the first opening crosses adjacent gate structures; a first mask layer is formed on the surface of the sidewall of the first opening, and the first mask layer crosses the adjacent gate structures; a sacrificial layer fully filling in the first opening is formed on the surface of first mask layer, and the material etching resistance of the first mask layer is greater than that of the sacrificial layer; a second mask layer having a second opening is formed on the surface of the dielectric layer, the surface of the sacrificial layer and the surface of the first mask layer, and the second opening crosses the sacrificial layer and the first mask layer; the dielectric layer exposed out of the sacrificial layer and the first mask layer is etched along the second opening with the second mask layer acting as the mask, and discrete contact holes are formed in the dielectric layer arranged between the adjacent gate structures; and conductive plugs fully filling in the contact holes are formed. The sidewall position accuracy and the shape accuracy of the formed contact holes can be enhanced so as to improve the performance of the formed semiconductor structure.

The invention provides a formation method of a semiconductor structure. The method includes the following steps that: a substrate is provided, a plurality of active regions are arranged in the substrate, and isolation structures are arranged between adjacent active regions, the substrate surfaces of a part of the active regions are provided with gate structures, two sides of each gate structure are respectively provided with a source region and a drain region; a first dielectric layer is formed on the surfaces of the active regions, the isolation structures and the gate structures; the first dielectric layer on the isolation structures is removed, initial through holes are formed in the first dielectric layer; a protective layer is formed on the surfaces of the side walls of the initial through holes; after the first dielectric layer at the bottoms of the initial through holes is removed, first through holes are formed in the first dielectric layer; a second dielectric layer is formed in the first through holes; after the first dielectric layer is removed, a second through hole and a source line trench are formed at two sides of each gate structure respectively; and drain conductive structures are formed in the second through holes, and source line conductive structures are formed in the source line trenches. The semiconductor structure formed by adopting the method has a beautiful appearance and stable performance.

A formation method of a semiconductor device includes providing a substrate having a to-be-etched layer including a graph dense zone and a graph sparse zone; forming a first mask layer having sparse images on the surface of the graph sparse zone of the to-be-etched layer; forming a photo-etching layer covering the surface of the to-be-etched layer and the surface of the first mask layer; performing exposure development on the photo-etching layer and forming a second mask layer having dense images on the image dense zone of the to-be-etched layer and the surface of the first mask layer; etching the graph dense zone of to-be-etched layer by taking the second mask layer as a mask and etching the graph sparse zone of the to-be-etched layer by taking the second mask layer and the first mask layer as the mask until the surface of the substrate is exposed. By adopting the invention, problems caused by load effect during an etching process can be solved, so that the etching layer formed after the etching process of the graph sparse zone has a good appearance.

The invention provides a forming method of a resistive random-access memory. The method comprises the steps as follows: a substrate is provided; a lower electrode layer is arranged in the substrate; the top part of the lower electrode layer is flush with the surface of the substrate; a dielectric material layer is formed on the surface of the substrate; an upper electrode layer is formed on the surface of the dielectric material layer; a hard mask layer is formed on the surface of the upper electrode layer; the hard mask layer is patterned; an opening for exposing the upper electrode layer is formed in the hard mark layer; with the hard mask layer with the opening as a mask, the upper electrode layer and the dielectric material layer are sequentially etched by a dry etching process until the surface of the substrate is exposed; an etching gas for the dry etching process is H2; the hard mask layer with the opening is removed. The etching pollution to the upper electrode layer and the dielectric material layer caused by the etching process is avoided; and the side wall of the etched upper electrode layer and the side wall of the dielectric material layer are clean, so that the electrical properties of the formed resistive random-access memory are improved.

The invention relates to the field of process processing, in particular to a method for forming a nanopillar array on a semiconductor substrate, which comprises the following steps of: providing the semiconductor substrate, coating photoresist on the semiconductor substrate, and photoetching on the photoresist to form a pattern; a mask layer is formed on the prepared pattern, and light propagation is stopped through the mask layer; according to the method, a semiconductor substrate containing a mask layer is subjected to electrochemical etching, patterns with different heights are obtained by controlling etching conditions, then the mask layer is removed, the semiconductor substrate comprises a silicon carbide substrate slice or a gallium nitride substrate slice, the length and width of the semiconductor substrate are 2-8 inches, the thickness of the semiconductor substrate is 200-500 micrometers, and the thickness of the semiconductor substrate is 1-10 micrometers. An electron beam direct writing technology is adopted in the photoetching mode, and the pattern is in a nanopillar array shape. By adopting the photoelectrochemical etching method, the large-scale preparation of the nano-pillar array with controllable diameter size and height can be realized on the surface of the wafer-level wide bandgap semiconductor substrate slice, the process is simple, and the yield is high.

The invention provides a super junction and a manufacturing method thereof, and a deep trench manufacturing method of the super function. In the deep trench manufacturing method of the super function,a mask layer formed on a substrate or formed on an epitaxial layer of the substrate is subjected to etching through high-molecular polymer gas to form a hard mask plate, the substrate or the epitaxial layer formed on the substrate is etched step by step through the hard mask plate under stepped increasing gas pressure, and thus, a deep trench is formed on the substrate or the epitaxial formed onthe substrate. By the deep trench manufacturing method provided by the invention, the deep trench with relatively good characteristic size uniformity, depth uniformity and angle uniformity can be formed.

The present invention relates to a method for forming a stepped structure of a three-dimensional memory, comprising: providing a substrate on which a stacked structure is formed, the stacked structure including a stepped area; forming a mask layer on the surface of the stepped area, and The mask layer includes at least a first sub-mask layer whose hardness is greater than that of the organic polymer layer; using the mask layer as a mask, step etching is performed on the step region of the stacked structure to form a step structure. The above method can improve the sidewall morphology of the formed step structure.

A forming method of a semiconductor structure comprises: providing a substrate, wherein a dielectric layer is formed at the surface of the substrate; etching to remove the dielectric layer of first thickness by means of first etching process, and forming a pre-opening in the dielectric layer; depositing a silicon layer at the bottom and sidewall surface of the pre-opening by means of depositing process; etching to remove the silicon layer at the bottom surface of the pre-opening by means of second etching process, and etching to remove the dielectric layer of second thickness below the pre-opening; repeating the depositing process and the second etching process until an opening running through the dielectric layer is formed, and exposing the bottom of the opening to the surface of the substrate; forming a conductive layer filling the opening. The shape of the sidewall of the formed opening is improved, breakthrough voltage of the semiconductor structure that is formed is improved, and the breakthrough problem of time related media is improved.

The invention provides a method for manufacturing a metal nanowire, a semiconductor device, and a method for manufacturing the same. After a patterned core layer and the surface of a semiconductor substrate are covered with a metal layer, a spacer is formed on the sidewall of the metal layer. Then, under the protection of the spacer, the metal layer on the top surface of the patterned core layer and the surface of the semiconductor substrate outside the spacer is removed, thereby forming an L-shaped metal nanowire sandwiched between the patterned core layer and the spacer. The metal nanowire has a good sidewall shape and high thickness uniformity, which can improve device performance and a product yield.