31results about How to "Good sidewall morphology" patented technology

Provided is a method for forming a through silicon via. The method comprises: obtaining a first etching stage and a second etching stage according to a through silicon via to be formed; etching a silicon substrate with a first Bosch process in the first etching stage at a first etching temperature in order to form a first via; and etching the silicon substrate with a second Bosch process along the first via in the second etching stage at a second etching temperature until a through silicon via is formed, wherein the second Bosch process comprises: etching the silicon substrate with the first etching in order to form an opening; forming a protection layer on the sidewall and the bottom of the opening with passivation deposition; and successively and circularly using the first etching and the passivation deposition until the through silicon via is formed, wherein the second etching temperature is below the first etching temperature or over the first etching temperature. The through silicon via formed by using the method for forming a through silicon via has high quality.

The invention provides a method for forming self-alignment duplex pattern. The method comprises the following steps: providing a material layer to be etched, forming a sacrificial photoresist layer on the material layer to be etched, curing the sacrificial photoresist layer, forming a first mask pattern on the side wall surface of the sacrificial photoresist layer, and removing the sacrificial photoresist layer. As the sacrificial photoresist layer is cured, the hardness of the sacrificial photoresist layer is increased, and during the process of forming the first mask pattern, the sacrificial photoresist layer does not deform under the stress generated by the first mask material layer, so that the side wall of the sacrificial photoresist layer is still perpendicular to the surface of the material layer to be etched, and finally, the side wall of the etched pattern which is formed by etching the material layer to be etched has a better profile.

A method for forming a semiconductor structure, comprising: forming a first opening in a dielectric layer, the first opening spanning an adjacent gate structure; forming a first mask layer on the sidewall surface of the first opening, and the first mask layer The film layer spans the adjacent gate structure; a sacrificial layer filling the first opening is formed on the surface of the first mask layer, and the material etch resistance of the first mask layer is greater than the material etch resistance of the sacrificial layer; A second mask layer with a second opening is formed on the surface of the dielectric layer, the surface of the sacrificial layer and the surface of the first mask layer, and the second opening spans the sacrificial layer and the first mask layer; as a mask, etch the dielectric layer exposed by the sacrificial layer and the first mask layer along the second opening, and form discrete contact holes in the dielectric layer between adjacent gate structures; plug. The invention improves the position accuracy and shape accuracy of the side wall of the formed contact hole, thereby improving the performance of the formed semiconductor structure.

A formation method of a semiconductor device includes providing a substrate having a to-be-etched layer including a graph dense zone and a graph sparse zone; forming a first mask layer having sparse images on the surface of the graph sparse zone of the to-be-etched layer; forming a photo-etching layer covering the surface of the to-be-etched layer and the surface of the first mask layer; performing exposure development on the photo-etching layer and forming a second mask layer having dense images on the image dense zone of the to-be-etched layer and the surface of the first mask layer; etching the graph dense zone of to-be-etched layer by taking the second mask layer as a mask and etching the graph sparse zone of the to-be-etched layer by taking the second mask layer and the first mask layer as the mask until the surface of the substrate is exposed. By adopting the invention, problems caused by load effect during an etching process can be solved, so that the etching layer formed after the etching process of the graph sparse zone has a good appearance.

The invention provides a method for manufacturing a metal nanowire, a semiconductor device and a method for manufacturing the same. After covering a patterned core layer and a surface of a semiconductor substrate with a metal layer, first form a side wall on the side wall of the metal layer, and then Under the protection of the sidewall, the metal layer on the top surface of the patterned core layer and the surface of the semiconductor substrate outside the sidewall is removed, thereby forming an L-shaped structure sandwiched between the patterned core layer and the sidewall. The metal nanowires have better sidewall morphology and higher thickness uniformity, thereby improving device performance and product yield.

The invention discloses a forming method of a resistance-type random access memory. The forming method comprises the following steps: using a hard mask layer with an opening as a mask, etching a top electrode layer with a first dry method etching technology until the surface of a dielectric material layer is exposed, wherein etching gas of the first dry method etching technology is CH4; continuously using the hard mask layer with the opening as the mask, etching the dielectric material layer with a second dry method etching technology until the surface of a bottom electrode layer is exposed, wherein etching gas of the second dry method etching technology is H2. According to the forming method, the etching technologies are prevented from causing etching pollution on the top electrode layer and the dielectric material layer, so that the side wall of the top electrode layer and the side wall of the dielectric material layer after etching are clean, and then the electrical property of the formed resistance-type random access memory is improved.

Disclosed are a semiconductor etching device and an etching method of a semiconductor structure. The etching method includes: a etching process with a first bias power source is utilized to etch a to-be-etched material layer, and the first bias power source generates continuous bias power to form a first opening which does not expose a etching blocking layer; and then a etching process with a second bias power source is utilized to etch the first opening, and the second bias power source generates pulse bias power until the etching blocking layer is exposed to form a second opening. Due to the fact that the continuous bias power is utilized to form bias voltage for etching firstly, side wall appearance is good, and etching selection ratio to a photo layer is high. The continuous bias power is switched into pulse bias power to form bias voltage for etching in prior to exposure of the etching blocking layer, so that cuts are avoided from being formed at the side wall bottom, close to the etching blocking layer, of the to-be-etched material layer.

The invention provides a formation method of a semiconductor structure. The method includes the following steps that: a substrate is provided, a plurality of active regions are arranged in the substrate, and isolation structures are arranged between adjacent active regions, the substrate surfaces of a part of the active regions are provided with gate structures, two sides of each gate structure are respectively provided with a source region and a drain region; a first dielectric layer is formed on the surfaces of the active regions, the isolation structures and the gate structures; the first dielectric layer on the isolation structures is removed, initial through holes are formed in the first dielectric layer; a protective layer is formed on the surfaces of the side walls of the initial through holes; after the first dielectric layer at the bottoms of the initial through holes is removed, first through holes are formed in the first dielectric layer; a second dielectric layer is formed in the first through holes; after the first dielectric layer is removed, a second through hole and a source line trench are formed at two sides of each gate structure respectively; and drain conductive structures are formed in the second through holes, and source line conductive structures are formed in the source line trenches. The semiconductor structure formed by adopting the method has a beautiful appearance and stable performance.

The invention provides a forming method of a resistive random-access memory. The method comprises the steps as follows: a substrate is provided; a lower electrode layer is arranged in the substrate; the top part of the lower electrode layer is flush with the surface of the substrate; a dielectric material layer is formed on the surface of the substrate; an upper electrode layer is formed on the surface of the dielectric material layer; a hard mask layer is formed on the surface of the upper electrode layer; the hard mask layer is patterned; an opening for exposing the upper electrode layer is formed in the hard mark layer; with the hard mask layer with the opening as a mask, the upper electrode layer and the dielectric material layer are sequentially etched by a dry etching process until the surface of the substrate is exposed; an etching gas for the dry etching process is H2; the hard mask layer with the opening is removed. The etching pollution to the upper electrode layer and the dielectric material layer caused by the etching process is avoided; and the side wall of the etched upper electrode layer and the side wall of the dielectric material layer are clean, so that the electrical properties of the formed resistive random-access memory are improved.

The invention provides a super junction and its manufacturing method, and a method for manufacturing a deep trench of a super junction. The method of manufacturing a deep trench of a super junction is formed on a substrate or formed on a substrate by a polymer gas pair. The mask layer on the epitaxial layer is etched to form a hard mask, and the substrate or the epitaxial layer formed on the substrate is etched step by step through the hard mask with stepwise increasing gas pressure, so that A deep trench is formed on the substrate or an epitaxial layer formed on the substrate. The invention can form deep grooves with better feature size uniformity, better depth uniformity and better angle uniformity.

The invention provides a formation method of a semiconductor structure. The formation method comprises the steps that a first mask layer crossing a dielectric layer between the adjacent gate structures is formed on the surface of the dielectric layer; a side wall layer is formed on the surface of the sidewall of the first mask layer on the surface of the dielectric layer between the adjacent gate structures; a second mask layer having an opening is formed on the surface of the first mask layer and the surface of the dielectric layer, and the opening crosses the first mask layer and the side wall layer; the dielectric layer exposed out of the side wall layer and the first mask layer is etched along the opening with the second mask layer acting as the mask until the surface of a substrate is exposed, and discrete contact holes are formed in the dielectric layer between the adjacent gate structures; the second mask layer and the first mask layer are removed; and conductive plugs fully filling in the contact holes are formed. The sidewall position accuracy and the shape accuracy of the formed contact holes are improved so as to enhance the electrical performance and the yield rate of the formed semiconductor structure.

A self-aligned double patterning formation method comprises the steps of providing a material layer to be etched, forming a sacrificial photoresist layer on the material layer to be etched, forming a polymer layer on the surfaces of the top and the side walls of the sacrificial photoresist layer, forming a first mask material layer on the surface of the polymer layer, and back-etching the first mask material layer to enable the first mask material layer on the two sides of the sacrificial photoresist layer to form a first mask pattern. As the polymer layer is formed on the surfaces of the top and the side walls of the sacrificial photoresist layer, and the hardness of the polymer layer is far higher than that of the sacrificial photoresist layer, the shape of the sacrificial photoresist layer does not deform due to stress generated by the first mask material layer. Moreover, the rotation angle of the polymer layer formed by the use of a deposition process and an etching process is a right angle, which enables the sidewall morphology of the final etched pattern to be good.