Formation method of semiconductor structure

Abstract

The invention provides a formation method of a semiconductor structure. The formation method comprises the steps that a first opening is formed in a dielectric layer, and the first opening crosses adjacent gate structures; a first mask layer is formed on the surface of the sidewall of the first opening, and the first mask layer crosses the adjacent gate structures; a sacrificial layer fully filling in the first opening is formed on the surface of first mask layer, and the material etching resistance of the first mask layer is greater than that of the sacrificial layer; a second mask layer having a second opening is formed on the surface of the dielectric layer, the surface of the sacrificial layer and the surface of the first mask layer, and the second opening crosses the sacrificial layer and the first mask layer; the dielectric layer exposed out of the sacrificial layer and the first mask layer is etched along the second opening with the second mask layer acting as the mask, and discrete contact holes are formed in the dielectric layer arranged between the adjacent gate structures; and conductive plugs fully filling in the contact holes are formed. The sidewall position accuracy and the shape accuracy of the formed contact holes can be enhanced so as to improve the performance of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous development of semiconductor process technology, such as the introduction of high-K gate dielectric layer, stress engineering technology, pocket ion implantation, and continuous optimization of materials and device structures, the size of semiconductor devices continues to shrink. However, when the feature size of the device is further reduced, planar transistors face huge challenges due to the more significant short-channel effect, process variation, and reduced reliability. Compared with planar transistors, FinFETs have fully depleted fins, lower dopant ion concentration fluctuations, higher carrier mobility enhancement, lower parasitic junction capacitance, and higher area usage efficiency has received extensive attention. [0003] In the integrated circuit m...

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Problems solved by technology

[0004] In the prior art, during the formation of the semiconductor structure, the size of the contact hole formed by the self-alignment process is likely to deviate from the design value, which will affect the connection performance of the formed conductive plug and affect the performance of the formed semiconductor structure

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