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41results about How to "Improve interface quality" patented technology

Two-dimensional magnetic material device and preparation method and regulation and control method thereof

ActiveCN119562753Aregulation and stabilitySmall working currentMagnetic anisotropyIonic liquid
The invention discloses a two-dimensional magnetic material device and a preparation method and a regulation and control method thereof, and the regulation and control method comprises the steps: enabling ionic liquid to cover the surface of a two-dimensional magnetic material, enabling the ionic liquid to be in contact with a grid electrode, a source electrode, a drain electrode and the two-dimensional magnetic material, and continuously applying current from the grid electrode to the source electrode and to the drain electrode, and the regulation and control of the two-dimensional magnetic material device are completed. According to the two-dimensional magnetic material device and the preparation method and the regulation and control method thereof provided by the invention, the ionic liquid containing the cationic molecular chains with different lengths is selected to perform intercalation on the two-dimensional magnetic material device, so that regulation and control on the two-dimensional magnetic material device are realized, and the regulation and control flexibility of the two-dimensional magnetic material is greatly improved; and the coercive field, the magnetic anisotropy energy and the carrier concentration of the two-dimensional magnetic material can be changed.
Owner:NANJING UNIV OF POSTS & TELECOMM

Diamond / gallium oxide heterojunction and application thereof in solar-blind ultraviolet detector

The invention relates to the technical field of solar-blind ultraviolet detector materials, and particularly discloses a diamond / gallium oxide heterojunction and application of the diamond / gallium oxide heterojunction to a solar-blind ultraviolet detector, and the diamond / gallium oxide heterojunction comprises a single crystal diamond layer and a Zr-doped epsilon-Ga2O3 layer located on the single crystal diamond layer; the single crystal diamond layer is made of (100) oriented single crystal diamond, and the surface roughness RMS of the single crystal diamond is 2-6 nm; the Zr-doped epsilon-Ga2O3 layer is Zr-doped epsilon-Ga2O3 which is grown on the surface of the monocrystal diamond in a heteroepitaxial manner by adopting a pulse laser deposition method; zr-doped epsilon-Ga2O3 grows on the surface of the monocrystal diamond along the (001) direction; and the Zr doped epsilon-Ga2O3 is of a columnar crystal structure. The heterojunction provided by the invention realizes excellent photoelectric detection performance, solves the problem of poor selectivity of a traditional solar blind ultraviolet detector, and has wide application value.
Owner:HUNAN UNIV +1

Enhanced MOSHEMT device with groove gate wrapped by ultrahigh K dielectric and preparation method of enhanced MOSHEMT device

The invention discloses an enhanced MOSHEMT (Metal-Oxide-Semiconductor High Electron Mobility Transistor) device with an ultrahigh K dielectric wrapped groove gate, which structurally comprises a substrate, a buffer layer, a channel layer and a barrier layer in sequence, a source electrode and a drain electrode are respectively arranged on two sides of the barrier layer, a groove is arranged in the middle of the barrier layer close to the source electrode, a passivation layer is arranged in the area of the barrier layer except for the source electrode and the drain electrode, and a metal oxide semiconductor layer is arranged on the passivation layer. An ultrahigh K gate dielectric layer is arranged on the passivation layer, a groove gate is arranged above the ultrahigh K gate dielectric layer corresponding to the groove of the barrier layer, and an ultrahigh K dielectric layer is further arranged to cover the groove gate. The invention also discloses a preparation method. The enhanced HEMT device with high threshold voltage and high transconductance is realized by introducing a high-quality ultra-high K medium and utilizing polarization charges generated by the high-quality ultra-high K medium to assist depletion and accumulation of 2DEG under a gate; after the gate metal is deposited, the ultra-high K dielectric layer is secondarily covered to form a wrapped groove gate, a peak electric field can be effectively reduced by utilizing polarization charges, close to a drain end region, of the gate edge, and high breakdown voltage is achieved.
Owner:NANJING UNIV

Gallium nitride epitaxial structure formation method and semiconductor device

ActiveCN122054629BThreshold Voltage Stabilityavoid damageDevice materialContact layer
The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.
Owner:YUANSHAN ADVANCED MATERIAL TECH INC

Low-evaporation three-layer film cathode assembly for space traveling wave tube and preparation method of low-evaporation three-layer film cathode assembly

The invention relates to the field of electron tubes, and discloses a low-evaporation three-layer film cathode assembly for a space traveling wave tube, which comprises a tungsten substrate positioned on a substrate; the first layer of rhenium film and the rhenium film cover the tungsten substrate; the carbon nanotube composite material layer is deposited on the rhenium film; the second osmium-tungsten film is deposited on the carbon nanotube layer; the third osmium-ruthenium film is deposited on the osmium-tungsten film; wherein the thicknesses of the rhenium film, the carbon nanotube layer, the osmium-tungsten film and the osmium-ruthenium film are respectively controlled to be 0.5-2 mu m, 10-50 nm, 50-200 nm and 20-100 nm, and the carbon nanotube composite material layer is obtained by growing on the rhenium film through chemical vapor deposition. By adopting the osmium-tungsten and osmium-ruthenium films with high crystallinity and the optimized carbon nanotube composite material layer, the electron emission efficiency of the cathode assembly is remarkably improved, so that the energy required by electron emission is reduced, and the electron output quantity under the same working condition is increased.
Owner:NANJING SANLE GROUP

A method for electrochemically layer-by-layer delamination of a high temperature alloy

PendingCN122709542Aavoid electrolysishigh selectivity
The present application belongs to the technical field of high-temperature alloy material performance detection, and particularly relates to a kind of high-temperature alloy electrochemical layer-by-layer stripping test methods.The present application is pretreated after high-temperature alloy sample, and the non-stripping area is coated with insulating glue, solidified, and the obtained sample to be stripped is used as anode, titanium alloy is used as cathode, is immersed in 30~40℃ electrolyte in stirring state, constant current is applied, and electrochemical stripping is carried out;Specifically: the first piece of sample to be stripped in the same batch is subjected to short-time stripping in batches, and the depth is compared layer by layer, the stripping time-stripping depth correspondence is established, the stirring, temperature and current are kept unchanged, and the other samples to be stripped in the same batch are stripped according to the stripping time-stripping depth correspondence.The method provided by the present application is simple in process, low in cost, good in stripping uniformity, high in precision, solves the problems of uneven stripping, product accumulation and low depth control precision in the existing high-temperature alloy electrochemical stripping technology.
Owner:XIAN AISHEN AVIATION TECHNOLOGY CO LTD

Process method for improving channel mobility and gate dielectric layer reliability of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

The invention relates to a process method for improving channel mobility and gate dielectric layer reliability of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The process method comprises the following steps of: forming a channel layer on an epitaxial layer by adopting ion implantation; carrying out surface treatment on the SiC epitaxial layer in a sacrificial oxidation mode; forming SiO2 on the surface of SiC by adopting a low-pressure chemical vapor deposition process to serve as a gate dielectric layer; and performing an NO post-deposition annealing process on the gate dielectric layer. The SiC / SiO2 interface roughness formed by the method is reduced, the problem that carbon clusters and carbon particles are generated in traditional thermal oxidation is avoided, and the interface state density is reduced, so that the channel carrier mobility is enhanced; besides, a step-by-step low-pressure chemical vapor deposition process is adopted, gate dielectric layer densification is carried out in a gap between two or more stages of deposition processes, residues of a precursor in deposition are fully decomposed, stress of the gate dielectric layer is released, the electric leakage level of the gate dielectric layer is reduced, the reliability of the gate dielectric layer is enhanced, and the device yield is improved.
Owner:ZHEJIANG UNIV

Method for improving interface quality of additive manufacturing gradient functional material

The invention discloses a method for improving the interface quality of an additive manufacturing gradient functional material, and belongs to the field of advanced processing and preparation of metal materials. According to the method, firstly, the additive manufacturing gradient functional material is subjected to heat preservation for 1 h to 3 h in a heat treatment furnace under the condition of 400 DEG C to 1000 DEG C, then thermal deformation is conducted under the condition of the thermal deformation speed of 0.1 mm / s to 10 mm / s, and the deformation amount is 10% to 70%. The additive manufacturing gradient functional material is subjected to thermal deformation treatment, diffusion of alloy elements at the interface is promoted, the connection strength of chemical bonds at the interface is improved, the defects at the gradient interface are eliminated, the path of cracks in the expansion process is more zigzag, the deflection angle is increased, and the performance of the gradient functional material is improved. And the quality of the additive manufacturing gradient functional material interface is greatly improved.
Owner:INST OF METAL RESEARCH - CHINESE ACAD OF SCI

Light emitting diode, preparation method thereof and communication system

PendingCN121985641AKeep the interface clearsuppressed interdiffusionClose-range type systemsIndiumCommunications system
The invention relates to the technical field of semiconductors, and provides a light-emitting diode, a preparation method thereof and a communication system. The light emitting diode comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence. The active layer comprises at least one group of quantum well layers and quantum barrier layers which are periodically and alternately stacked; the quantum well layer comprises an In component; the active layer further comprises at least one covering layer; the covering layer is located between the quantum well layer and the quantum barrier layer; the material of the covering layer is selected from a III-V group nitride semiconductor material, and the bond energy of a chemical bond formed by a metal element contained in the III-V group nitride semiconductor material and a nitrogen element is higher than the bond energy of In-N formed by an indium element and the nitrogen element in the quantum well layer. Through the above arrangement, mutual diffusion of In atoms in the quantum well containing the In component is effectively inhibited, a clear interface of the quantum well layer is maintained, and high-speed LED communication is further realized.
Owner:XIAMEN UNIV

Solid-phase composite manufacturing device based on micro-macro wire feeding and composite material manufacturing method

The invention discloses a solid-phase composite manufacturing device based on micro-macro wire feeding and a composite material manufacturing method.The solid-phase composite manufacturing device based on micro-macro wire feeding comprises a macro additive manufacturing module and a micro additive manufacturing module, and the macro additive manufacturing module comprises a first wire feeding mechanism and a first stirring head; a first spiral groove is formed in the periphery of one end of the first stirring head, the first wire feeding mechanism is used for conveying a base material towards the first spiral groove, the microscopic additive manufacturing module comprises a second wire feeding mechanism and a second stirring head, and the second stirring head is arranged in the first stirring head and can rotate relative to the first stirring head; a second spiral groove is formed in the periphery of the end, close to the first spiral groove, of the second stirring head. The second wire feeding mechanism is used for conveying reinforcing materials towards the second spiral groove. According to the solid-phase composite manufacturing device based on micro-macro wire feeding, the composite material with the reinforcing material distribution controllable can be manufactured, and the base material and the reinforcing material can be conveyed without shutdown.
Owner:ANHUI WORLD WIDE WELDING CO LTD

A method for regrowth of epitaxial layer of semiconductor structure

The present invention relates to a method for regrowth of an epitaxial layer of a semiconductor structure, comprising: providing an etched semiconductor structure; preparing a self-assembled organic solution; placing the etched semiconductor structure in the self-assembled organic solution, the self-assembled organic solution forming a self-assembled monolayer film on the surface of the semiconductor structure, the self-assembled monolayer film serving as a passivation film; placing the semiconductor structure formed with the self-assembled monolayer film in a growth device, heating it to a first temperature to remove the self-assembled monolayer film; the first temperature is the decomposition temperature of the self-assembled monolayer film; heating it to a second temperature to regrow on the surface of the semiconductor structure to form an epitaxial layer; the second temperature is the growth temperature of the epitaxial layer. The method for regrowth of an epitaxial layer of a semiconductor structure provided by the present invention can ensure that no oxide layer is generated before the epitaxial layer is formed on the surface of the semiconductor structure, improve the interface quality between the epitaxial layer and the semiconductor structure, improve the quality and efficiency of the growth of the epitaxial layer, and thus improve the electrical and optical properties of the device finally formed.
Owner:WUXI HUACHEN XINGUANG SEMICON TECH CO LTD

A diamond-based boron nitride film and a method for preparing the same

ActiveCN121896602BUniform nucleationuniform continuity
The application discloses a diamond-based boron nitride film and a preparation method thereof, and relates to the technical field of semiconductor epitaxial materials. The preparation method comprises the following steps: sequentially polishing and cleaning and pretreating a single crystal diamond substrate; performing glow discharge cleaning treatment on a cavity, and increasing the temperature in the cavity to a growth temperature; performing glow discharge activation treatment on the surface of the pretreated single crystal diamond substrate; performing auxiliary glow discharge activation treatment on the surface of the single crystal diamond substrate after the glow discharge activation treatment; growing a boron nitride film on the surface of the single crystal diamond substrate after the surface treatment; reducing the growth temperature to room temperature to obtain a diamond-based boron nitride film after the temperature reduction treatment; and performing annealing treatment on the diamond-based boron nitride film after the temperature reduction treatment to obtain a finally prepared diamond-based boron nitride film. The method can simultaneously meet the key requirements of low damage, high nucleation activity and controllable stress release of the interface.
Owner:XIDIAN UNIV

A homogenous multi-channel thin film transistor and a method of manufacturing the same

PendingCN122602550AAchieve differentiated distributionLow interface state defects
The application provides a homogenous multi-channel thin film transistor and a preparation method thereof. The preparation method comprises the following steps: preparing a gate electrode and a gate dielectric layer on a substrate in sequence; using an atomic layer deposition process to deposit at least two InGaO sub-channel layers on the gate dielectric layer in a direction away from the gate dielectric layer in sequence, and stacking the InGaO sub-channel layers to form a channel layer; during the deposition of each InGaO sub-channel layer, the same type of Ga precursor source and different types of In precursor source are used, or the same type of In precursor source and different types of Ga precursor source are used, so that each InGaO sub-channel layer has different carrier concentrations; during the deposition of each InGaO sub-channel layer, the sub-cycle periods are the same; performing a patterning treatment on the channel layer; preparing a source electrode and a drain electrode on the patterned channel layer to obtain the homogenous multi-channel thin film transistor. The application can simplify the preparation process, improve the interlayer interface quality, and does not need high-temperature annealing treatment.
Owner:MOZI LABORATORY

Semiconductor laser structure with cyclic strain buffer layer

The invention relates to the technical field of semiconductors, and particularly discloses a semiconductor laser structure with cyclic strain buffer layers, which comprises an epitaxial structure layer and a substrate, a plurality of groups of strain buffer layers are arranged between the epitaxial structure layer and the substrate, each group of strain buffer layers comprises a strain layer and a buffer layer, the buffer layers are made of gallium arsenide, and the cyclic strain buffer layers are arranged between the epitaxial structure layer and the substrate. The material of the strain layer is Al < x > Ga < 1-x > In < y > P, xlt; 1, 0lt; yt; Yt; and 0.48, 3 to 50 groups of strain buffer layers are arranged. The laser epitaxial structure has the effect of improving the defect of serious warping caused by large pressure stress of the laser epitaxial structure.
Owner:WUXI HUACHEN XINGUANG SEMICON TECH CO LTD

Semiconductor laser element provided with quantum confinement stark regulation and control layer

The semiconductor laser element sequentially comprises a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer and an upper limiting layer from bottom to top, and the quantum limiting stark regulation and control layer is arranged between the active layer and the lower waveguide layer. The electric field distribution of the active layer is regulated and controlled, domain wall motion is induced to be generated, the quantum limited stark effect and InN phase separation of the active layer are inhibited, the interface quality is improved, and the non-radiative recombination center is reduced; light field limitation and limiting factors are enhanced, and the light power of the laser is improved; the quantum confinement stark regulation and control layer generates lattice displacement to induce phase change, improves mutual solution gaps of InN and GaN, inhibits InN segregation of the active layer and the waveguide layer, reduces In component fluctuation, reduces thermal degradation, improves interface crystal quality and thermal stability, reduces a non-radiative recombination center, and improves laser power and slope efficiency.
Owner:GEN SEMICONDUCTOR (ANHUI) CO LTD

Multi-layer thin film structure, preparation method and application of multi-layer thin film structure

The invention discloses a multi-layer thin film structure, a preparation method and application of the multi-layer thin film structure. The multi-layer thin film structure comprises a single crystal substrate, an aluminum thin film and a tantalum thin film. The preparation method comprises the following steps: processing the surface of a single crystal substrate; epitaxially growing an aluminum film on the surface of the single crystal substrate; a tantalum film is epitaxially grown over the aluminum film. According to the multilayer film structure, the preparation method and the superconducting quantum bit device provided by the invention, the preparation method of a tantalum film is expanded, uniform growth of a large-area alpha-phase tantalum film is realized, the interface quality of the multilayer film is high, and the superconducting critical temperature is 2-4K. Meanwhile, the superconducting quantum bit device designed by the invention is long in de-coherence time, and the manufactured resonant cavity circuit has a high quality factor and can be applied to the fields of superconducting quantum bit devices, superconducting quantum computers and the like.
Owner:NANJING UNIV +1

Titanium-steel composite plates and their preparation methods, shipbuilding

This application relates to the field of metal material processing technology, and discloses a titanium-steel composite plate, its preparation method, and a ship. The titanium-steel composite plate includes a steel substrate layer, a pure titanium cladding layer, and an alloy layer, wherein the alloy layer is disposed between the steel substrate layer and the pure titanium cladding layer; wherein the alloy layer includes a Fe-intermediate element-Ti ternary alloy layer, and the Fe-intermediate element-Ti ternary alloy layer satisfies the following conditions along the direction from the steel substrate layer to the pure titanium cladding layer: the Fe content gradually decreases, the Ti content gradually increases, and the content of the intermediate element first gradually increases and then gradually decreases; the intermediate element is a transition element in the Fe-Ti system. This composite plate exhibits excellent interface quality, as well as excellent structural stability and corrosion resistance.
Owner:ANHUI WORLD WIDE WELDING CO LTD

Composite device and method for preparing double-metal gradient structure round pipe through single-step deformation

PendingCN122057796AImprove interface qualityStructural continuityExtrusion diesMetallic materialsStructural engineering
The invention discloses a composite device and method for preparing a double-metal gradient structure circular pipe through single-step deformation. The composite device comprises a first half die, a second half die, a first forming die, a second forming die, a clamp, a punch, a supporting rod and a taking-out rod, modular integrated design is adopted, and disassembly and combination are convenient. Through cooperative plastic flowing of the forming channel, the outer layer metal material and the inner layer metal material are stably combined in the one-time forming process, the problems of multi-pass machining, mold replacement and the like in a traditional technology are solved, and the production efficiency is remarkably improved. The gradient structure can effectively improve stress distribution between the inner metal layer and the outer metal layer, and the fatigue life and the overall service performance of the pipe are improved. The method is suitable for combination of various metal materials, has wide application prospects, and particularly has important application values in the fields requiring high strength, corrosion resistance, wear resistance and the like.
Owner:SOUTH CHINA UNIV OF TECH

Power device and method of manufacturing the same

This application discloses a power device and its fabrication method. The power device includes a semiconductor device, a first electrode, a second electrode, a filler structure, and a thermal buffer layer. The semiconductor device includes a first surface and a second surface opposite to each other along its thickness direction. The first surface is provided with a first electrode and a control electrode, and the second surface is provided with a second electrode. The first electrode is in contact with the first electrode. The second electrode is in contact with the second electrode. The filler structure is disposed between the control electrode and the first electrode. The wall surface of the filler structure facing the first electrode is flush with or protrudes from the wall surface of the first electrode facing the first electrode. The filler structure includes a solid insulating element, and the thermal resistance of the solid insulating element is less than or equal to the thermal resistance of air. The thermal buffer layer is sandwiched between the control electrode and the filler structure. The control electrode forms contact with the first electrode at least through the thermal buffer layer and the solid insulating element. The thermal expansion coefficient of the thermal buffer layer is between the thermal expansion coefficient of the control electrode and the thermal expansion coefficient of the solid insulating element.
Owner:TSINGHUA UNIVERSITY

Apparatus and method for producing fluorine-based glass optical fiber preform clad hollow tube

The application relates to a device and a method for preparing a fluorine-based glass optical fiber preform rod cladding hollow tube. In the device, by reducing the air pressure in a closed crucible environment and assisting with a constant rotation rate, dissolved gas in the glass liquid can be effectively removed, and a fluorine-based glass preform rod cladding hollow tube without bubbles, high uniformity and high interface quality can be automatically / semi-automatically prepared. The method has a short preparation period and is expected to be applied to the preparation of a fluorine-based optical fiber preform rod with a high-quality core-cladding structure.
Owner:SHANGHAI INST OF OPTICS & FINE MECHANICS CHINESE ACAD OF SCI

Corrosion-resistant surgical instrument

The utility model relates to the technical field of surgical instruments, in particular to a corrosion-resistant surgical instrument. According to the technical scheme, the corrosion-resistant surgical instrument comprises a sheath, a knife handle, a blade and an installation groove, a first reed is arranged in the sheath, second reeds are arranged on the two sides of the knife handle, the knife handle is installed in the sheath in a limited mode through cooperation of the second reeds and the first reed, the installation groove is formed in the knife handle, and the blade is arranged in the installation groove. A fixing buckle is arranged in the installation groove, and a blade is installed in the installation groove of the knife handle in a limited mode through the fixing buckle. The utility model provides a safer, more convenient and more reliable operation tool for medical personnel, and is beneficial to improving the success rate of an operation and the treatment effect of a patient.
Owner:SUZHOU HUARUIJIE NEW MATERIAL TECH CO LTD

Photon synaptic device applied to image recognition and preparation method thereof

The invention discloses a photon synaptic device applied to image recognition and a preparation method of the photon synaptic device. The device sequentially comprises a top electrode, a MoS2 functional layer, a CsPbBr3 quantum dot functional layer and a bottom electrode from top to bottom. The specific preparation method comprises the following steps: (1) providing a MoS2 solution and a CsPbBr3 quantum dot solution; (2) transferring a MoS2 solution to bottom electrode ITO glass, and annealing in a vacuum drying oven at 130 DEG C for 20 minutes to obtain a MoS2 functional layer; (3) depositing a CsPbBr3 quantum dot solution on the surface of the MoS2 functional layer, and annealing in the vacuum drying oven at 170 DEG C for 20 minutes to form a CsPbBr3 quantum dot functional layer; and (4) covering the surface of the CsPbBr3 quantum dot functional layer with a piece of ITO conductive glass as a top electrode to prepare the photon synapse device. The photon synaptic device disclosed by the invention can simulate short-term plasticity (STP) and long-term plasticity (LTP) of neurons, can be applied to image recognition, and effectively improves the recognition precision.
Owner:NANJING ZHIMALI NETWORK TECHNOLOGY CO LTD +1

Method for optimizing ohmic contact structure on back surface of GaN device through sin insertion layer

The utility model provides a structure for optimizing ohmic contact on the back surface of a GaN device through a sin insertion layer, which belongs to the technical field of GaN devices, and comprises a GaN substrate and a sin layer arranged on the back surface of the GaN substrate, the sin layer is provided with a concave-convex structure, and the concave-convex structure is provided with a concave-convex groove. The GaN substrate is provided with a concave-convex structure, the concave-convex structure is specifically protrusions formed on the surface of the sin layer, the GaN substrate is further provided with a metal contact layer, the metal contact layer makes contact with the concave-convex structure, the metal contact layer is provided with structures matched with the protrusions on the surface of the sin layer, and the sin layer and the metal contact layer are physically interlocked through the concave-convex structure. According to the utility model, the peeling phenomenon of the contact layer under the condition of high temperature or high pressure is solved, and the long-term reliability of the device is improved.
Owner:SUZHOU CHUANGXIN ZHISHANG MICROELECTRONICS CO LTD

Low-defect-density compound semiconductor film and preparation method and application thereof

The invention discloses a low-defect-density compound semiconductor film and a preparation method and application thereof, and the method comprises the steps: alternately growing a compound semiconductor layer and a defect blocking layer on a substrate, and enabling the defect blocking layer to be provided with a groove-shaped structure, and to be used for limiting defect propagation and guiding the transverse growth of the compound semiconductor layer; gradually expanding the low-defect area through multiple alternate growth until a complete low-defect-density compound semiconductor film is formed; depositing a two-dimensional material layer on the terminal layer grown on the compound semiconductor film for subsequent stripping of the low-defect-density compound semiconductor film; and transferring the separated film to a new substrate, and repeating the growing and stripping steps to realize industrial batch production. The defect barrier layer with the groove-shaped structure is introduced to the surface of the thin film, the deposition and stripping technology of the two-dimensional material layer is combined, defect propagation can be effectively limited, the crystal quality of the thin film is improved, lossless separation and repeated transfer of the thin film are achieved, and the method is suitable for batch industrial production.
Owner:SHANGHAI FENGZHENG CHUANGZHAN SEMICONDUCTOR CO LTD

Passivated contact solar cell and method of making same

The invention relates to the technical field of photovoltaics, and discloses a passivation contact solar cell and a preparation method thereof. The preparation method comprises the following steps: providing a substrate layer with a first surface and a second surface which are opposite; forming an oxide layer on the first surface of the substrate layer; performing laser sintering treatment on the surface of the oxide layer; forming a first doping layer on the oxide layer after laser sintering treatment; forming a second doping layer on the second surface of the substrate layer; and forming a first electrode connected with the first doping layer on one side of the first surface of the substrate layer, and forming a second electrode connected with the second doping layer on one side of the second surface of the substrate layer. According to the invention, the laser sintering treatment is carried out on the oxide layer to realize accurate optimization of the surface of the oxide layer and improve the surface and interface characteristics, so that the surface recombination rate of the oxide layer and the substrate layer and the first doping layer is reduced, the service life of a carrier is prolonged, the photoelectric conversion efficiency and stability of the cell are improved, and the power generation efficiency is improved.
Owner:HENGDIAN GRP DMEGC MAGNETICS CO LTD

An organic semiconductor vertical heterojunction single crystal array and a preparation method thereof

The application provides an organic semiconductor longitudinal heterojunction monocrystal array and a preparation method thereof, and the preparation method comprises the following steps: providing a first silicon column template, a second silicon column template and a substrate; the first silicon column template and the second silicon column template are respectively provided with a first silicon column array and a second silicon column array, and the first silicon column template, the second silicon column template and the substrate are respectively provided with a first alignment mark, a second alignment mark and a third alignment mark; based on the melting point difference of different organic semiconductor systems, a longitudinal heterojunction monocrystal array with a determined crystal orientation and a controllable structure size is prepared through step-by-step melting, directional crystallization and alignment control. Compared with the traditional longitudinal heterojunction which is usually prepared layer by layer by using a solution method, the solvent is easy to damage the first layer of crystals when the second layer of crystals is formed, the step-by-step crystallization is realized by using the melting point difference in the application, the influence of the solvent on the first layer of crystals is avoided, and the application has the advantages of high controllability, good stability and strong applicability.
Owner:SUZHOU INST FOR ADVANCED STUDY USTC +1

Perovskite semiconductor device and preparation method thereof

The invention discloses a perovskite semiconductor device and a preparation method thereof. The semiconductor device adopts a transparent glass substrate. The perovskite semiconductor device structurally comprises a first transparent conductive oxide layer, a perovskite layer, a quantum dot doping layer, an electron selection layer, an electron transmission layer, a buffer layer and a second transparent conductive oxide layer from a transparent glass substrate to the top in sequence. Both the first transparent conductive oxide layer and the second transparent conductive oxide layer adopt ITO (Indium Tin Oxide); the perovskite layer is made of CH3NH3PbI3, and the quantum dot doping layer is made of CdSe quantum dots for doping; the electron selection layer is made of a Bi2Se3 thin film material; the perovskite semiconductor device has high short-circuit current and energy conversion efficiency, the light absorption capacity and the carrier transmission efficiency of the cell are improved under the synergistic effect of introduction of the quantum dot doping layer and the bismuth selenide layer, and the photoelectric conversion efficiency is remarkably improved.
Owner:SHENZHEN UNIV

A method for manufacturing a gate oxide layer

The embodiment of the present application discloses a preparation method of a gate oxide layer. The preparation method of the gate oxide layer comprises the following steps: providing a semiconductor body; the semiconductor body comprises a first surface and a second surface arranged oppositely; forming a first gate oxide layer on the first surface of the semiconductor body; annealing the first gate oxide layer by using a first gas; forming a second gate oxide layer on the side of the first gate oxide layer away from the first surface; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; annealing the first gate oxide layer and the second gate oxide layer by using a second gas; the second gas is different from the first gas. The technical scheme of the embodiment of the present application can improve the quality of the gate oxide layer and the interface quality of the semiconductor body.
Owner:YOFC ADVANCED SEMICONDUCTOR (WUHAN) CO LTD

Preparation method of gate oxide layer of switching device based on SiC substrate and switching device

The invention provides a method for preparing a gate oxide layer of a switching device based on a SiC substrate and a switching device, and relates to the technical field of semiconductors. The invention uses an atomic layer deposition method to sequentially form an aluminum oxide film and a hafnium oxide film on the surface of a SiC substrate to form a gate oxide layer of a laminated structure. The thickness of the formed aluminum oxide film and the hafnium oxide film are uniform and the thickness can be precisely controlled, so as to ensure that the thickness and thickness of the entire gate oxide layer can accurately meet the requirements. Since aluminum oxide and hafnium oxide have higher dielectric constants, the laminated structure formed by the two can improve the overall dielectric constant of the gate oxide layer, increase the capacitance effect of the gate dielectric, and suppress tunneling leakage current. Annealing the aluminum oxide film and the hafnium oxide film can improve the crystallinity and interface quality of the film. Rapid thermal annealing is performed on the prepared switching device sample to further optimize the performance of the gate oxide layer and reduce defects and interface charges.
Owner:ANHUI UNIV +1

Synaptic device and preparation method thereof

PendingCN121985559ASuppress depolarizing fieldsimprove performanceSynaptic deviceSemiconductor
The invention discloses a synaptic device and a preparation method thereof. The synaptic device comprises an insulating substrate; the first electrode layer is positioned on the insulating substrate; the two-dimensional ferroelectric dielectric layer is located on a part of the first electrode layer; the two-dimensional semiconductor layer at least covers part of the two-dimensional ferroelectric medium layer, and the two-dimensional semiconductor layer covers at least part of the first electrode layer on one side of the two-dimensional ferroelectric medium layer; and a second electrode layer on the two-dimensional semiconductor layer on the two-dimensional ferroelectric layer. According to the synaptic device, the first electrode layer and the second electrode layer are respectively arranged below and above the two-dimensional ferroelectric dielectric layer, so that a depolarization field in the two-dimensional ferroelectric dielectric layer can be effectively inhibited, the ferroelectric polarization retentivity of the two-dimensional ferroelectric dielectric layer is remarkably improved, and the performance of the synaptic device is effectively improved.
Owner:SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI