3 results about "Transistor channel" patented technology

The application provides a semiconductor vertical field effect device preparation method, which comprises the following steps: S100, processing a wafer to form a vertical field effect device prototype with exposed gate part, performing isotropic etching on the exposed gate part to form a gate trench; S200, forming an oxide layer on the gate by oxidation growth; S300, filling metal in the gate trench to form a self-aligned word line; and S400, forming a drain on the upper part of the silicon surface of the wafer by epitaxial growth process. In the preparation process, the length and diameter of the transistor channel and the height and thickness of the gate word line can be accurately adjusted according to the requirement, meanwhile, the flatness of the bottom of the gate oxide layer and the bit line metal is better, so that the current can be adjusted and the leakage current can be reduced, and due to the overall integration of the bit line, the process flow is simplified and the preparation cost is reduced.

The invention relates to a depth image sensor. Each pixel of the sensor comprises first and second detection nodes and a collection area located above a photosensitive region formed in a substrate; first and second transfer transistors comprising first and second vertical gates and first and second channels, respectively; and a multi-gate photosensitive region initialization transistor comprising a collection channel controllable by the first and second vertical gates. The transistor channels extend between the photosensitive region on one side and the detection nodes and the collection area on the other. The readout circuit is configured to apply first and second electrical signals to the first and second vertical gates, respectively, so as to alternately conduct each of the first channel, the second channel, and the collection channel, independently of the other two channels.Figure for the abbreviation: figure 1A.

The utility model provides a self-clamping protection circuit. A power supply end VS is connected with a drain electrode of a power transistor M0 and a voltage sampling module VS-sns; the voltage sampling module VS-sns is connected with the control end of the voltage-controlled current source I0; on one hand, the voltage sampling module Gate-sns is connected with the grid electrode of the power transistor M0, and on the other hand, the voltage sampling module Gate-sns is connected with the control end of the voltage-controlled current source I1; a grid electrode of the power transistor M0 is connected with the driving module on one hand, and is grounded through the voltage-controlled current source I0 and the voltage-controlled current source I1 on the other hand; the enabling module is connected with the control end of the voltage sampling module VS-sns and the control end of the voltage sampling module Gate-sns through the switching circuit. According to the utility model, the voltage-controlled current source I0 and the voltage-controlled current source I1 complement each other so as to achieve the self-pull-down function that the channel of the power transistor M0 is opened due to different power-on speeds of the power supply end VS, so that the power transistor M0 can be protected when the power supply is rapidly powered on.