18 results about "Transistor channel" patented technology

In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source / drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source / drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source / drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source / drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.

An integrated circuit includes a compressive stressor and a tensile stressor, each located directly over an active region of a transistor, where a portion of the compressive stressor and a portion of the tensile stressor directly overlap with each other. In some embodiments, utilizing a compressive stressor and tensile stressor located directly over an active region with overlapping portions may allow for an adjustment of the stress applied to a channel region of a transistor to compensate for stress imparted by package structures.

Embodiments of the disclosure provide methods of manufacturing electronic devices that meet compressive stress requirements for PMOS transistors and tensile stress requirements for NMOS transistors. Each P-metal stack and P-metal stack: is formed on a top surface of a channel located between a source and a drain on a semiconductor substrate, and comprises nanosheet channel layers and trenches between each nanosheet channel layer, and has at least one side defining a gate trench. Some embodiments include forming a work function layer in the channel and inducing a work function layer strain in the channel. Some embodiments include forming a gate metal fill layer on each of the P-metal stack and the N-metal stack and inducing a gate metal fill layer strain in the channel. The gate metal fill layer covers the at least one side of each of the P-metal stack and the N-metal stack and fills the gate trench.

The invention relates to a memory device with segmented SGD drain. Various applications may include memory devices designed to provide enhanced gate-induced drain leakage (GIDL) current during memory erase operations. An enhancement operation may be provided to a string of memory cells at a segmented drain of a select gate transistor by enhancing an electric field in a channel structure of the select gate transistor. The segmented drain may have conductive fins integrated with the transistor channel structure and extending vertically from a top boundary of the transistor channel structure, wherein the conductive fins are separated from each other by a non-conductive region on the top boundary. The segmented drain may include a portion extending downward below the top boundary. The transistor channel structure may be integrated with a channel structure forming a pillar of the memory cell string. Additional apparatus, systems, and methods are discussed.

Aiming at the shortcomings and limitations of the existing two-dimensional ion-sensitive field effect transistor and extended gate field effect transistor, an ion-sensitive field effect transistor and an extended field effect bio-detection chip are proposed. In addition to extending the gate to the top of the chip or configuring metal internal connections on the gate, so that the area reacting with the biological sample to be detected is away from the transistor channel to reduce noise and interference, the profile of the conductor located above the transistor channel is adjusted to have different parts extending in different directions, thereby increasing the reaction area with the biological sample to be detected and improving the reaction efficiency and accuracy. In addition, a single transistor is corresponded to multiple or even multiple electrodes, even multiple adjacent transistors are configured as described and grouped together, and the signals generated by the reaction with the biological sample to be detected are output to the external circuit, thereby simultaneously detecting multiple or even multiple biological samples to be detected, and reducing the cost of consumables and noise.

The application provides a semiconductor vertical field effect device preparation method, which comprises the following steps: S100, processing a wafer to form a vertical field effect device prototype with exposed gate part, performing isotropic etching on the exposed gate part to form a gate trench; S200, forming an oxide layer on the gate by oxidation growth; S300, filling metal in the gate trench to form a self-aligned word line; and S400, forming a drain on the upper part of the silicon surface of the wafer by epitaxial growth process. In the preparation process, the length and diameter of the transistor channel and the height and thickness of the gate word line can be accurately adjusted according to the requirement, meanwhile, the flatness of the bottom of the gate oxide layer and the bit line metal is better, so that the current can be adjusted and the leakage current can be reduced, and due to the overall integration of the bit line, the process flow is simplified and the preparation cost is reduced.

The invention relates to a depth image sensor. Each pixel of the sensor comprises first and second detection nodes and a collection area located above a photosensitive region formed in a substrate; first and second transfer transistors comprising first and second vertical gates and first and second channels, respectively; and a multi-gate photosensitive region initialization transistor comprising a collection channel controllable by the first and second vertical gates. The transistor channels extend between the photosensitive region on one side and the detection nodes and the collection area on the other. The readout circuit is configured to apply first and second electrical signals to the first and second vertical gates, respectively, so as to alternately conduct each of the first channel, the second channel, and the collection channel, independently of the other two channels.Figure for the abbreviation: figure 1A.

Embodiments of the disclosure provide methods of manufacturing electronic devices that meet compressive stress requirements for PMOS transistors and tensile stress requirements for NMOS transistors. Each P-metal stack and P-metal stack: is formed on a top surface of a channel located between a source and a drain on a semiconductor substrate, and comprises nanosheet channel layers and trenches between each nanosheet channel layer, and has at least one side defining a gate trench. Some embodiments include forming a work function layer in the channel and inducing a work function layer strain in the channel. Some embodiments include forming a gate metal fill layer on each of the P-metal stack and the N-metal stack and inducing a gate metal fill layer strain in the channel. The gate metal fill layer covers the at least one side of each of the P-metal stack and the N-metal stack and fills the gate trench.

To provide a display device with a low manufacturing cost, to provide a display device with low power consumption, to provide a display device that can be manufactured on a large-area substrate, to provide a display device with a high numerical aperture of pixels, and to provide a display device with a high reliability.SOLUTION: A display device comprises: a transistor electrically connected with a pixel electrode having light transmissivity; and a capacitive element. The transistor includes: a gate electrode; a gate insulating film provided on the gate electrode; and a first multilayer film provided on the gate insulating film and that includes an oxide semiconductor layer. The capacitive element has: the pixel electrode; and a second multilayer film overlapped with and arranged at a predetermined interval from the pixel electrode, and that has the same layer structure as the first multilayer film. A channel formation region of the transistor is at least one layer not contacted with the gate insulating film, of the first multilayer film.SELECTED DRAWING: Figure 3

A semiconductor memory device comprises trench insulations arranged in the bit line direction, gate structures arranged in the word line direction perpendicular to the bit line direction, and an array of vertical transistor channels arranged in a vertical direction perpendicular to the bit line direction and the word line direction, separated by the trench insulations and gate structures—the upper end of the array of vertical transistor channels in each column is connected to a semiconductor structure line extending in the bit line direction from the rear of the semiconductor memory device—and air gap tunnels along the word line direction—each air gap tunnel crosses below the semiconductor structure line in a first region on the rear of the semiconductor memory device and is located between two adjacent vertical transistor channels.

A display device includes a polycrystalline semiconductor including a channel and electrodes of a driving transistor; a gate electrode of the driving transistor on the channel of the driving transistor; a first storage electrode on the gate electrode of the driving transistor; a light blocking layer of a first transistor and a light blocking layer of a second transistor; an oxide semiconductor including a channel and electrodes of the first transistor, and a channel and electrodes of the second transistor; a gate electrode of the first transistor on the channel of the first transistor; and a gate electrode of the second transistor on the channel of the second transistor. The light blocking layer of the first transistor and the first storage electrode are on a same layer, and the light blocking layer of the second transistor and the gate electrode of the driving transistor are on a same layer.

To provide methods for forming a novel field effect transistor (FET) that includes a center fin region and one or more vertically stacked nanosheets.SOLUTION: A method for forming a non-planar channel region having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first semiconductor layer and the second semiconductor layer. Forming the non-planar channel region includes forming a nanosheet stack over a substrate, forming a trench by removing a portion of the nanosheet stack, and forming the second semiconductor layer in the trench. Outer surfaces of the first semiconductor layer, the second semiconductor layer and the fin-shaped bridge region define an effective channel width of the non-planar channel region.SELECTED DRAWING: Figure 36

A workpiece is measured using multiple-pass spectroscopic ellipsometry and multi-wavelength Raman spectroscopy, which may be performed in the same system. These measurements are combined to form combined measured data. A stress measurement of the workpiece is determined using the combined measured data. The stress measurement can be determined using a model or a machine learning algorithm.

To reduce the consumption power of a liquid crystal display device, suppress the deterioration of display, and suppress the deterioration of display due to an external factor such as a temperature.SOLUTION: As a transistor provided in each pixel, a transistor whose channel formation region is formed of an oxide semiconductor layer is used. When the oxide semiconductor layer has high purity, the off current value of the transistor at a room temperature can be made 10 aA / μm or less and the off current value thereof at 85°C can be made 100 aA / μm or less. Therefore, the consumption power of the liquid crystal display device can be reduced and the deterioration of display can be suppressed. As described above, the off current value of the transistor can be made 100 aA / μm or less even at a temperature as high as 85°C. Therefore, the deterioration of display of the liquid crystal display device due to an external factor such as a temperature can be suppressed.SELECTED DRAWING: Figure 1

The utility model provides a self-clamping protection circuit. A power supply end VS is connected with a drain electrode of a power transistor M0 and a voltage sampling module VS-sns; the voltage sampling module VS-sns is connected with the control end of the voltage-controlled current source I0; on one hand, the voltage sampling module Gate-sns is connected with the grid electrode of the power transistor M0, and on the other hand, the voltage sampling module Gate-sns is connected with the control end of the voltage-controlled current source I1; a grid electrode of the power transistor M0 is connected with the driving module on one hand, and is grounded through the voltage-controlled current source I0 and the voltage-controlled current source I1 on the other hand; the enabling module is connected with the control end of the voltage sampling module VS-sns and the control end of the voltage sampling module Gate-sns through the switching circuit. According to the utility model, the voltage-controlled current source I0 and the voltage-controlled current source I1 complement each other so as to achieve the self-pull-down function that the channel of the power transistor M0 is opened due to different power-on speeds of the power supply end VS, so that the power transistor M0 can be protected when the power supply is rapidly powered on.

A method for producing a semiconductor structure (130) comprising: Providing a multilayer substrate (140) comprising: a base substrate (102), a buried oxide layer (104) over a surface of the base substrate (102), and a strained semiconductor layer (106) over the buried oxide layer (104) on a side thereof opposite the base substrate (102), the strained semiconductor layer (106) comprising crystalline semiconductor material; Implanting ions into a second region of the strained semiconductor layer (106B) without implanting ions into a first region of the strained semiconductor layer (106A) and converting a portion of the crystalline semiconductor material in the second region of the strained semiconductor layer (106B) into amorphous material, such that the second region of the strained semiconductor layer (106B) has an amorphous region and an underlying crystalline region; Recrystallization of the amorphous region; Diffusing elements from a portion of the second region of the strained semiconductor layer (106B) into another portion of the strained semiconductor layer (106) such that a concentration of the diffused elements is enriched in the other portion of the second region of the strained semiconductor layer (106B) and the strain state of the second region of the strained semiconductor layer (106B) is changed such that the second region of the strained semiconductor layer is in a strain state that is different from the strain state of the first region of the strained semiconductor layer (106A); and forming a first plurality of transistor channel structures, each comprising a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures, each comprising a portion of the second region of the semiconductor layer (106B).

A method includes forming a transistor over a substrate, the transistor comprising a channel region, a gate structure over the channel region, and a plurality of source / drain regions on opposite sides of the channel region; forming a source / drain contact over one of the source / drain regions; forming a source / drain via over the source / drain contact, wherein from a top view, the source / drain via has a T-shaped profile, the source / drain via has a first portion extending in a lengthwise direction of the channel region, and a second portion extending in a lengthwise direction of the gate structure.

Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.