34 results about "EDRAM" patented technology

The invention discloses a neural network accelerator based on eDRAM in-memory calculation and a control method thereof, the neural network accelerator comprises a top layer controller and an extensible and reconfigurable SR-CIM macro array, and the extensible and reconfigurable SR-CIM macro array is operated in a global system mode. The method comprises the following steps: acquiring weight data and input activation data; setting a working mode of the extensible and reconfigurable SR-CIM macro array; and according to the working mode of the extensible and reconfigurable SR-CIM macro array, performing operation on the weight data and the input activation data, and transmitting an operation result to the off-chip neural network. According to the embodiment of the invention, the computing efficiency of the neural network can be improved by improving the reuse rate of the data and reducing the access times of the off-chip data in different data flow modes. The method can be widely applied to the technical field of neural network accelerators.

The invention provides an eDRAM-based high-density near-storage calculation and in-storage calculation hybrid architecture and a calculation method. The architecture comprises an eDRAM near-storage and storage calculation hybrid array, a sensitive amplifier, an ADC circuit, a storage calculation result register, a characteristic value updating drive circuit, a controller, a row decoder and a column decoder. According to the calculation method, the architecture is adopted for calculation. By combining a near memory and an in-memory calculation structure, the characteristics of the near memory and the in-memory calculation structure are fully matched to carry out optimization design on an array structure and a basic unit and complement the independent defects of the two architectures, meanwhile, a deep groove capacitor is adopted to replace a plane capacitor, and the advantages of low power consumption, low time delay, high calculation efficiency, high density and the like are achieved; the bandwidth limitation of a traditional near storage circuit and the process limitation of an in-storage computing circuit are effectively overcome, and the method can be applied to a deep learning accelerator computing core and is particularly suitable for edge end hardware deployment with high requirements for the integration level and the power consumption performance.

An eDRAM cell for a CIM according to the present disclosure includes a first transistor which is connected between a read word line and a read bit line and has a gate connected to a storage node; a second transistor which is connected between a write bit line and the storage node and has a gate connected to a write word line; a first capacitor connected between the storage node and a ground; a third transistor which is connected between a local MAC bit line and a fourth transistor and has a gate connected to the storage node; and a fourth transistor which is connected between the third transistor and the ground and has a gate connected to a MAC word line.

A cryogenic quasi-static embedded DRAM (CQS-eDRAM) for energy-efficient computing-in-memory (CIM) is provided. A CQS-eDRAM array includes four-transistor transmission gate gain-cell (4T TGGC) memory cells, and each of the 4T TGGC memory cells includes a P-channel metal oxide semiconductor (PMOS) transistor P1 and three N-channel metal oxide semiconductor (NMOS) transistors N1, N2, and N3. A cryogenic 4T TGGC topology is provided. A quasi-static storage operation is achieved at a cryogenic temperature by fully utilizing advantages of the cryogenic 4T TGGC topology in reducing leakage and a line transmission delay. In addition, a cryogenic write bit line (WBL) bias technology and a dedicated readout circuit are adopted to optimize power consumptions of read and write operations.

The invention discloses a reconstruction task interpretability analysis method based on an encoder-decoder architecture, and the method is called as Encoder-Decoder Recstructionality-Oriented Feature Activity Mapping (EDRAM), and comprises the following steps: loading a pre-training model, constructing an EDRAM class, carrying out image preprocessing, carrying out forward propagation on the model, calculating the EDRAM, fusing an EDRAM result, and carrying out visual analysis. The method is suitable for multi-category reconstruction tasks, and can provide independent interpretability analysis for each category and network hierarchy. Through fusion and visualization of multi-level EDRAM results, the EDRAM method realizes comprehensive and visual interpretation of the encoder-decoder model decision process, and provides an important basis for model optimization and performance improvement.

The invention discloses a storage and calculation integrated hardware accelerator and system based on high-density cache. In the accelerator, a storage unit array comprises a plurality of 2T eDRAM units, and a read word line decoder is used for selecting storage units storing operands to be operated from the storage unit array; the induction amplifier is used for reading an operand to be operated of the storage unit array as a digital signal according to a set reference voltage to obtain a corresponding logical operation result; the shifter is used for performing shifting operation on the logic operation result output by the induction amplifier as required; and the write bit line driving module is used for selecting an operation result from the output end of the induction amplifier or the output end of the shifter and storing the operation result to a corresponding storage unit of the storage unit array through write-back operation. According to the accelerator designed by the invention, an analog-to-digital converter is not needed, relatively high storage density can be achieved, large-scale logic parallel operation can be realized, addition and multiplication can also be realized, and an application scene is expanded.

According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

The invention belongs to the field of artificial intelligence hardware acceleration, and discloses a high-density single-fingered eDRAM storage and calculation integrated macro with bit-level sparse perception and kernel-level weight update, which comprises an input buffer, a weight buffer, a word line decoder, a bit line driver, a single-fingered eDRAM array and an output buffer, the weight buffer is used for writing weights from the off-chip and writing the weights into the single-finger eDRAM array line by line, and each single-finger eDRAM storage unit only stores one bit; the input buffer is used for writing an input activation value and transmitting a multi-bit input activation value into the single-fingered eDRAM array bit by bit from a low bit to a high bit, each row of single-fingered eDRAM is equipped with a bit saliency perception analog-to-digital converter BSA-ADC and is used for executing matrix vector multiplication and transmitting a calculation result to a calculation line CL, the BSA-ADC digitalizes an accumulation result on the calculation line, and the calculation line CL is connected with the input buffer. The result is transmitted to the output buffer; the output buffer is used for outputting the calculation result. The integrated macro has the advantages of high density, low energy consumption and high throughput.

The present invention discloses a high-density and high-reliability in-memory computing circuit based on eDRAM. The circuit includes: an eDRAM storage computing circuit, an ADC circuit, a calculation result register and an integrator capacitor reading circuit. In the calculation mode, the original data and the weight value stored in the eDRAM storage computing circuit complete the multiplication and accumulation operation, and then the multiplication and accumulation result is converted into analog to digital through the ADC circuit, and the conversion result is stored in the output result register. In the capacitor reading mode: the integrator capacitor reading circuit reads the capacitance value of each basic unit of the eDRAM storage computing circuit one by one. The present invention effectively avoids the problems of leakage current of eDRAM units, nonlinear calculation, etc. through the capacitor charging and discharging characteristics, and has the advantages of high density, high reliability, low power consumption, etc., and can be used for the computing core of neuromorphic chips, and is particularly suitable for end-side devices with high requirements for energy consumption and reliability, to achieve large-scale parallel computing.

The technical scheme of the invention discloses a compact type 5T0C eDRAM (Dynamic Random Access Memory) gain unit. According to the other technical scheme, the invention discloses a high-density content addressing circuit adopting the compact 5T0C eDRAM gain unit. Aiming at the problems of large storage unit area and limited density in the traditional CAM design based on SRAM (Static Random Access Memory), the invention provides a novel architecture based on eDRAM (Enhanced Dynamic Random Access Memory), and by optimizing the storage unit structure and a reading circuit, the storage density is obviously improved, and CAM search and in-memory logic operation are supported at the same time. Compared with an existing 6T SRAM, the area of the CAM array based on the eDRAM is reduced by 15%. According to the invention, the highest search and logic operation frequency of the binary CAM (BCAM) of 637 / 658 MHz is realized, and the search power consumption and the logic operation power consumption under the voltage of 1.1 V are respectively 0.91 fJ / search / bit and 27.47 fJ / bit. The method is suitable for data intensive applications such as artificial intelligence accelerators, network routers, genome analysis and the like which need efficient parallel search and near-memory calculation.

Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. For example, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, and both first and second arrays to store data of a processor. The second plurality of memory cells implements a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit is to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

The invention discloses a high-density embedded dynamic random access on-chip cache device and an implementation method. The high-density embedded dynamic random access on-chip cache device comprises an improved read-out current difference enhanced high-density eDRAM storage array and a read-out circuit, the reading circuit comprises a group of two-step power gating sensing amplifiers and a reading time sequence control circuit; threshold voltage selection of an on-chip cache reading transistor is optimized, and the difference proportion of reading current when different values are stored is expanded; by optimizing the structure of the cache memory array, the influence of interference current is eliminated; and a two-step power gating sensing amplifier is designed, and the reading current resolution capability is improved and the power consumption is effectively controlled by accurately controlling the starting time of two stages of circuits with different characteristics in the sensing process. The on-chip cache technical scheme provided by the invention realizes good balance among data retention time, energy efficiency and storage density, and is particularly suitable for edge computing equipment and artificial intelligence application scenes with strict requirements on energy efficiency and storage capacity.

The invention discloses a cross-coupled floating gate type storage and calculation integrated unit and a storage and calculation array, and belongs to the technical field of semiconductors. Each cross coupling floating gate type storage and calculation integrated unit comprises two coupling read-write subunits which are arranged in a conjugate mode and a write-in switch tube, the storage and calculation integrated units store electronic information through a silicon substrate depletion region, compared with a mode that a grid electrode of a traditional eDRAM device stores charges, the structure of the depletion region for storing weights does not have electric leakage between a gate capacitor and a PN junction, and the reliability of the eDRAM device is improved. The weight maintaining capability is higher than that of a traditional 2T 1C eDRAM by more than one order of magnitude, in addition, due to the fact that the cross coupling type storage and calculation integrated device is provided with the floating gate structure, calibration can be carried out by erasing electrons in a floating gate transistor to nonuniformity caused by process deviation, the precision of a storage and calculation unit is higher, and the storage and calculation efficiency is improved. These characteristics provide possibility for some applications requiring large-scale volatile memory array deployment.

The application discloses a cross-coupled floating gate type memory and computing integrated unit and a memory and computing array, and belongs to the technical field of semiconductors. Each cross-coupled floating gate type memory and computing integrated unit comprises two coupled read-write subunits arranged in conjugation and a write switch tube, the memory and computing integrated unit stores electronic information through a silicon substrate depletion region, compared with a traditional eDRAM device gate storage charge mode, the structure of the depletion region storing weights has no leakage between gate capacitance and a PN junction, and the weight maintenance capacity is more than one order of magnitude stronger than that of a traditional 2T 1C type eDRAM. In addition, the cross-coupled memory and computing integrated device provided by the application can calibrate the inconsistency caused by the process deviation of the floating gate transistor, so that the precision of the memory and computing unit is higher due to the floating gate structure, and these characteristics make it possible for some applications requiring large-scale volatile memory and computing array deployment.

An energy-efficient memory for cryogenic computing is provided. The energy-efficient memory includes a plurality of memory banks, where each of the memory banks includes a cryogenic semi-static, dual-port, boost-free gain cell (CSDB-GC) macro module, a universal address decoder, and a different address decoder. The CSDB-GC macro module includes a plurality of columns of local blocks, and each of the local blocks includes a plurality of CSDB-GC memory cells. A final measurement result of a 16 Kb CSDB-eDRAM shows that the 16 Kb CSDB-eDRAM achieves data retention time (DRT) of 16.67 seconds, which is 2.6 times longer than DRT of a state-of-the-art cryogenic eDRAM at a temperature of 4.2 K, and achieves lower refresh power (0.11 pW / Kb). In addition, the 16 Kb CSDB-eDRAM also achieves shorter access time, namely, 710 ps (1.41 GHz). Compared with the state-of-the-art work, the 16 Kb CSDB-eDRAM has a lowest dynamic power consumption overhead, namely, 49.23 uW / Kb.

An integrated circuit includes a substrate, an embedded dynamic random access memory (eDRAM) cell on a portion of the substrate, and a logic device cell disposed on another portion of the substrate. The substrate has a fully depleted silicon-on-insulator (FDSOI) structure that includes an SOI layer over a buried oxide layer. The eDRAM cell includes: at least one access transistor having a gate stack formed on an SOI layer and source / drain regions formed on opposite sides of the gate stack; and a capacitor electrically connected to the at least one access transistor. The eDRAM cell also includes a first back gate bias structure for applying a back gate bias to the at least one access transistor.

One technical scheme of the invention provides a complementary 3T storage unit. Another technical scheme of the invention is to provide a high-density bidirectional content addressable memory and in-memory logic integrated eDRAM macro cell. The invention provides a novel architecture based on an eDRAM (enhanced dynamic random access memory), the storage density is remarkably improved by optimizing a storage unit structure and a reading circuit, and meanwhile, bidirectional CAM (computer-aided memory) search and in-memory logic operation are supported. The technology is suitable for data-intensive applications such as artificial intelligence accelerators, network routers, genome analysis and the like which need efficient parallel search and near-memory calculation.

The disclosed technology herein relates to an on-chip artificial intelligence memory system. The system includes a mixed-memory cell comprising a static random access memory (SRAM) cell and at least one embedded dynamic random access memory (eDRAM) cell. The mixed-memory cell is configured to map a control bit of encoded data to the SRAM cell and to map remaining bits of the encoded data to the at least one eDRAM cell. The system includes an enhancement encoder decoder module configured to receive and encode data for storage in the mixed-memory cell. The system includes a refresh controller configured to refresh at least one data bit stored in the at least one eDRAM cell.

An apparatus for adaptively adjusting refresh timing of a CIM based on eDRAM includes a replica array including a plurality of replica MAC arrays, each having replica cells arranged in a direction and number according to the direction and number in which memory cells performing MAC operations together in a CIM cell array are arranged and a refresh determination module that compares voltage levels of signals output from each of the plurality of replica MAC arrays with MAC operation results according to weights stored in replica cells of the plurality of replica MAC arrays and activates a refresh enable signal for refreshing memory cells of the CIM cell array.

The present invention relates to a gain cell EDRAM with extended capacitance, providing a gain cell memory device including a semiconductor device layer including a silicon-on-insulator substrate of an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region to isolate a first portion of the active region from a second portion of the active region, and a capacitor coupled with the storage transistor. A bottom plate of the capacitor includes the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor includes the gate electrode of the storage transistor and a metal structure over the gate electrode.

The present invention provides a method for forming an eDRAM device, comprising: forming a first oxide layer and a first nitride layer on the surface of a substrate; forming a first deep trench and a second deep trench spaced apart; forming a dielectric layer, a barrier layer and a polysilicon layer in the first deep trench and the second deep trench, wherein the lower part of the polysilicon layer is separated from the lower part sidewall by the barrier layer and the dielectric layer; forming a second oxide layer on the surface of the polysilicon layer and the surface of the first nitride layer, wherein the thickness of the second oxide layer located on the surface of the first nitride layer is less than the thickness of the second oxide layer located on the surface of the polysilicon layer; removing a portion of the thickness of the second oxide layer, and retaining a portion of the thickness of the second oxide layer on the surface of the polysilicon layer; removing the first nitride layer and the first oxide layer; forming a third oxide layer and a second nitride layer in sequence on the surface of the substrate and the surface of the second oxide layer; forming a third trench between the first deep trench and the second deep trench; and forming a linear oxide layer and a dielectric layer in sequence in the third trench.

The first aspect of the technical scheme of the invention is to disclose a low-temperature SF-eDRAM, which is characterized by comprising a write-in tube N1, a read tube P1, a gate tube N2, a gate tube P2 and a capacitor C0. The second aspect of the technical scheme of the invention is to disclose a low-temperature self-adaptive reference voltage generation circuit. Aiming at the problems of large storage unit area and limited density in the traditional SRAM-based ACAM design, the invention provides a novel eDRAM-based architecture, by optimizing the storage unit structure, a reference voltage generation circuit and a reading circuit, the storage density is remarkably improved, and meanwhile, bidirectional ACAM search, in-memory logic operation and matrix transposition are supported. The technology disclosed by the invention is suitable for data-intensive applications such as artificial intelligence accelerators and network routers which can be arranged in a low-temperature environment and need efficient parallel search and near-memory calculation.

An eDRAM and a method for making it are disclosed. In the method, a pad oxide layer and a pad nitride layer are removed after an active area and a deep trench filled with polysilicon are formed, followed by the formation of a re-deposited oxide layer and a re-deposited nitride layer. The re-deposited nitride layer has greater uniformity than the pad nitride layer that has undergone the formation of the deep trench. An isolation recess is then formed at one side of the deep trench and then filled with a first isolation dielectric. In this process, the re-deposited nitride layer can be utilized to control the height and flatness of a top surface of the isolation dielectric. After that, an upper polysilicon recess between a first active sub-region and the first isolation dielectric is filled with a second isolation dielectric.

The application provides an on-chip cache management system, method, medium, program product and terminal for a large model AI chip, the application adopts a 3T GC-eDRAM cache unit structure to improve the storage capacity per unit area on the chip, and compared with a traditional 6T SRAM, the chip area is significantly reduced under the same cache capacity, thereby reducing the production cost. Based on the data heat characteristic parameter of the large model, the application adopts a three-level dynamic refresh strategy to avoid resource waste of unified refresh and reduce refresh power consumption. In the application scenario of large model inference, the application effectively reduces the response delay by combining the on-chip cache hardware structure and the dynamic refresh mechanism, and meets the low-delay inference requirement of the large model. The application adopts a 3T GC-eDRAM cache unit structure to realize on-chip cache on the chip, can be realized based on a standard CMOS process, and can be directly migrated to an advanced process such as 7nm and 5nm, without process modification.

The invention relates to a high-density 4T1C eDRAM (Dynamic Random Access Memory) macro structure for low-temperature true three-valued logic in-memory calculation, which belongs to the technical field of memory and calculation architecture integration, and comprises a reference voltage generation module for providing two key reference levels required by three-valued judgment; a row decoder selecting a target memory cell; the low-temperature three-valued write driving module transmits the three-valued voltage to the selected unit; the low-temperature three-valued storage array is of an array structure formed by a plurality of 4T1C three-valued storage units; a read / compute decoder that reads / computes a level state of the word line; the three-valued sensitive amplifier is used for completing three-valued voltage comparison; the output processing circuit is connected with the output end of the three-value sensitive amplifier; the control module is used for coordinating the working time sequence of each module; wherein the 4T1C three-valued storage unit realizes that one piece of true three-valued data is stored in a single unit through three stable voltage states of a storage node. According to the invention, high-density true three-valued data storage and various true three-valued logic operations under a low-temperature condition are realized.

The application discloses a low-temperature high-energy-efficiency in-memory computing accelerator.The application has the following innovations: a high-retention-time low-temperature 3T memory cell design: the application proposes a low-temperature 3T memory cell design based on eDRAM, which can significantly improve the retention time without any word line voltage boosting scheme, and realize full-swing data transmission during the write operation process; a low-temperature adaptive reconfigurable sensitive amplifier design: the application develops a low-temperature on-chip adaptive reconfigurable sensitive amplifier design, which can realize accurate on-chip Boolean logic calculation by configuring the reference voltage of ARSA; a low-temperature optimized Flash ADC design: the application uses the designed ARSA to adaptively generate 15 ARSA reference voltages on the chip and reconfigure them into 4bit Flash ADCs.Through the adaptive configuration of the reference voltage and the storage mode on the chip, the design can ensure the realization of fast and low-power consumption convolution calculation.

The present invention provides an in-memory computing eDRAM accelerator for convolutional neural networks. The accelerator is characterized by comprising four P2ARAM blocks, each of which includes a 5T1C ping-pong eDRAM bit cell array consisting of 64x16 5T1C ping-pong eDRAM bit cells. Within each P2ARAM block, 64x2 digital-to-time converters convert 4-bit activation values in the row direction into different pulse widths, which are then input into the 5T1C ping-pong eDRAM bit cell array for computation. A total of 16x2 convolution results are output in the column direction of the 5T1C ping-pong eDRAM bit cell array. The convolutional neural accelerator proposed in the present invention utilizes parallel multi-bit storage and convolution in the 5T1C ping-pong eDRAM bit cells. Without adding additional area overhead, the input sampling capacitors of the accumulation bit lines are distributed to the sign-value SAR ADC units of the CDAC array, thus proposing an S2M-ADC solution. In this way, the eDRAM-based in-memory computing neural network accelerator disclosed in the present invention achieves a peak computational density of 59.1TOPS / mm. 2 , which is about 30 times higher than previous work.

Embodiments of the present disclosure provide power to backend memory of an IC device from the back side of the device. An example IC device with back-side power delivery for backend memory includes a frontend layer with a plurality of frontend components such as frontend transistors, a backend layer (that may include a plurality of layers) with backend memory (e.g., with one or more eDRAM arrays), and a back-side power delivery structure with a plurality of back-side interconnects electrically coupled to the backend memory, where the frontend layer is between the back-side power delivery structure and the backend layer.

An eDRAM and a method for making it are disclosed. In the method, a pad oxide layer and a pad nitride layer formed over a surface of a substrate are removed after an active area and a deep trench filled with polysilicon are formed, followed by the formation of a re-deposited oxide layer and a re-deposited nitride layer. The re-deposited nitride layer has greater uniformity than the pad nitride layer that has undergone the formation of the deep trench. An isolation recess and a recess extension are then formed at one side of the deep trench and then filled with an isolation dielectric. In this process, the re-deposited nitride layer can be utilized to control the height and flatness of a top surface of the isolation dielectric, thus ensuring effective isolation of the polysilicon from a word line.

Examples herein provide a memory device comprising an eDRAM memory cell.SOLUTION: The memory device includes a write circuit formed at least partially above the storage capacitor and a read circuit formed at least partially below the storage capacitor, a computational near memory device bonded to the memory device, a processor, and an interface from the memory device to the processor. In some examples, a circuit comprising one or more of a controller, a multiplexer, or a register for providing an output of a memory device is included to emulate an output read rate of an SRAM memory device. The bonding of the surface of the memory device can be to a computational near memory device or other circuitry.SELECTED DRAWING: Figure 4