Semiconductor apparatus and methods for single-ended eDRAM sense amplifier

A semiconductor and device technology, applied in the direction of instruments, static memory, digital memory information, etc., can solve the problems of centering function loss, increased manufacturing cost, uncompetitive design, etc.

Inactive Publication Date: 2014-10-01
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] Loss of centering functionality makes it difficult to design and test eDRAM arrays for high yield, maximum retention and reliability
Inability to perform true signal margin testing
Efforts to compensate for this l...

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  • Semiconductor apparatus and methods for single-ended eDRAM sense amplifier
  • Semiconductor apparatus and methods for single-ended eDRAM sense amplifier
  • Semiconductor apparatus and methods for single-ended eDRAM sense amplifier

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Embodiment Construction

[0027] figure 1 A dynamic random access memory (DRAM) array having a segmented bit line structure, generally designated 111, is shown. figure 1 The structures shown are examples only, and those skilled in the art will understand that the systems and methods described herein may be used with figure 1 Similar arbitrary structures are applied and used together.

[0028] In this example, DRAM array 111 includes multiple DRAM cells integrated on the same die arranged along 64 word lines (WL-WL). As used herein, for embedded DRAM, a DRAM cell may be referred to as eDRAM. Each group of 64-bit cells of DRAM array 111 is connected to a local bit line 118, sometimes referred to herein as an LBL. LBL 118 is coupled to global bit line 125 , sometimes referred to herein as a GBL, through multiplexer device 132 . According to the systems and methods herein, multiplexer device 132 may comprise a CMOS multiplexer.

[0029] For convenience, LBL 118 , group of 64-bit cells, and multiplexer...

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Abstract

Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.

Description

technical field [0001] The present disclosure relates to sensing circuits for semiconductor devices. More specifically, the present disclosure relates to semiconductor devices including voltage compensation devices to center 'high' and 'low' eDRAM bit line signal bands around the transition point of a single-ended sense amplifier. Background technique [0002] In conventional dynamic random access memory (DRAM), the sense signal from the memory cell is generated by sharing the charge stored in the memory cell with the precharged bit line charge, which then precharges the developed sense signal on the bit line. The measured signal is compared to the reference bit line. [0003] DRAM arrays generate bit line voltages that must be interpreted as 'high' or 'low' to differentiate between the digital states of '1' or '0'. Traditional differential sensing schemes use reference voltage levels that can be centered in an expected band between a '0' data voltage level and an expected...

Claims

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Application Information

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IPC IPC(8): G11C11/4063
CPCG11C11/4074G11C11/4091G11C7/067G11C11/4094G11C11/4097
Inventor J·E·小巴尔赫J·A·费菲尔德M·D·杰昆斯基
Owner GLOBALFOUNDRIES INC
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