Semiconductor apparatus and methods for single-ended eDRAM sense amplifier

Abstract

Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.

Description

technical field [0001] The present disclosure relates to sensing circuits for semiconductor devices. More specifically, the present disclosure relates to semiconductor devices including voltage compensation devices to center 'high' and 'low' eDRAM bit line signal bands around the transition point of a single-ended sense amplifier. Background technique [0002] In conventional dynamic random access memory (DRAM), the sense signal from the memory cell is generated by sharing the charge stored in the memory cell with the precharged bit line charge, which then precharges the developed sense signal on the bit line. The measured signal is compared to the reference bit line. [0003] DRAM arrays generate bit line voltages that must be interpreted as 'high' or 'low' to differentiate between the digital states of '1' or '0'. Traditional differential sensing schemes use reference voltage levels that can be centered in an expected band between a '0' data voltage level and an expected...

AI Technical Summary

Problems solved by technology

[0013] Loss of centering functionality makes it difficult to design and test eDRAM arrays for high yield, maximum retention and reliability

Inability to perform true signal margin testing

Efforts to compensate for this loss of signal centering through Vdd regulation or through operating temperature limitations limit customer use and make the design uncompetitive

Tighter production controls improve eDRAM yields but increase manufacturing costs

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