Memory buffers for merging local data from memory modules

Abstract

An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.

Description

FIELD [0001] Embodiments of the invention relate generally to memory, and specifically to merging data from a memory buffer onto serial data channels. BACKGROUND INFORMATION [0002] In memory circuits there is typically a memory read latency that is the time period it takes for valid data to be read out of a memory circuit. A memory write latency is typically also required that is the time period to hold valid data for a memory circuit to write the data into memory. The memory read latency and the memory write latency may sometimes be buffered from a processor by a cache memory. However, there are occasions when the desired data is not found in the cache memory. In those cases, a processor may need to then read or write data with the memory circuits. Thus, the respective memory read latency or memory write latency may be experienced by the processor. If memory circuits differ, the memory read latencies and memory write latency may be inconsistent from one memory circuit to the next. ...

AI Technical Summary

Problems solved by technology

However, there are occasions when the desired data is not found in the cache memory.

If memory circuits differ, the memory read latencies and memory write latency may be inconsistent from one memory circuit to the next.

As there may be a number of memory modules plugged in, the additional parasitic capacitive load may be significant and bog down high frequency memory circuits.

While parallel data bit lines may speed data flow in certain instances, a parallel data bus in a memory may slow the read and write access of data between a memory circuit and a processor.

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