48 results about "High-speed link" patented technology

The invention relates to the technical field of adaptive routing optimization, and particularly discloses a topology self-recognition and routing optimization method and system for a concentrator and a collector, and the method comprises the steps: carrying out the topology modeling of a multi-layer heterogeneous network; executing high-speed link state monitoring based on the initial topological graph; global loop detection and link optimization are completed based on the link state matrix; a weighted robust multi-dimensional path selection method is adopted to configure a main path and a standby path for each node; and monitoring the path state in real time and dynamically switching. In the prior art, a static route, a single protocol path or a fixed main and standby path is mainly adopted, and especially in a cross-protocol, cross-level and dynamic multi-node environment in a smart city, rapid path switching and high-reliability route redundancy guarantee cannot be realized. Due to the fact that the multi-dimensional path selection method and the cross-level and cross-protocol self-adaptive switching strategy are adopted, the problems of routing interruption and performance reduction are avoided, and the reliability of the whole network is improved.

The invention relates to the technical field of digital communication, in particular to an intelligent electric meter dual-mode communication self-adaptive switching method, and provides the following scheme that operation data are divided into a plurality of data units at a sending end, priority evaluation is carried out, and the time delay, the packet loss, the energy consumption and the bandwidth state of two links are combined, so that the intelligent electric meter dual-mode communication self-adaptive switching method is realized. Positioning clearing cut points in the priority sequence so as to realize differentiated distribution of data between a high-speed link and a low-speed link; when the data is distributed to a low-speed link, sparse coding is carried out by adopting a preset dictionary, and differential updating is triggered when an error exceeds a limit, so that decoding consistency is ensured; a receiving end realizes unified analysis of the original message and the sparse message through cross-link association, dictionary updating and residual synthesis; according to the invention, the timeliness of the key message can be guaranteed, the communication energy consumption and cost can be reduced, and the cooperation efficiency of the dual-mode link can be improved.

The invention relates to a vehicle-mounted communication processing method, device and system, a vehicle and a storage medium. The method is applied to a sending end, the sending end comprises a user layer, a middleware layer and a link layer, and the method comprises the following steps: obtaining user layer data of the user layer through the middleware layer; obtaining link selection reference information of the sending link; when it is determined that a link layer has a high-speed link according to the link selection reference information and the high-speed link is enabled, selecting the high-speed link as a sending link; transmitting the user layer data to the link layer; and sending the user layer data to a receiving end at the link layer through the sending link. According to the scheme provided by the invention, the requirement of the end-to-end large model service of the self-driving system for cross-SOC ultra-large flow can be met.

The disclosure relates to freeze commands and restore commands associated with a flag capacity for computing a high speed link (CXL) memory device. A system may include a memory device including a plurality of dynamic capacity devices; and a processing device operably coupled with the memory device. The processing device is configured to perform operations including receiving a host command to freeze first data associated with a first flag associated with a first memory segment of a plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data.

The application discloses a high-speed link signal equalization method based on a three-dimensional memristor type equalizer, which comprises the following steps: obtaining a distorted signal and generating an ideal received signal, and then constructing a data set; training a recurrent neural network by using the data set to obtain a trained weight parameter; obtaining a conductance value matrix in the three-dimensional memristor type equalizer by mapping the weight parameter; deploying the conductance value to the three-dimensional memristor type equalizer according to the conductance value matrix; and finally inputting the distorted signal into the three-dimensional memristor type equalizer to obtain an optimized signal after compensation distortion. Compared with the traditional feedforward equalizer and decision feedback equalizer method, the application effectively reduces the time domain waveform distortion, improves the high-speed signal integrity, has wide applicability, can be used for the training and deployment application of the memristor type equalizer of various complex high-speed links, and deploys the above-mentioned conductance value to the three-dimensional memristor cross array, so as to improve the integrated density and reduce the area occupied by the equalizer.

The present disclosure relates to a computing high speed link (CXL) device configured to protect data by using data encryption and a method of operation thereof. An example CXL device includes a volatile memory connected to a plurality of channels; and a CXL controller. The CXL controller includes: a CXL subsystem controller configured to search a key index table for a first key index based on first host data and a first device physical address; and a memory subsystem controller configured to search for at least one first key in a key table based on the first key index, and generate first encrypted data based on the first data, the first device physical address, the at least one first key, and an encryption algorithm.

A general-purpose flash memory UFS device, a UFS system, and a method of operating the UFS system are provided. In one aspect, the UFS system includes a UFS host and a UFS device. The UFS host includes a first UFS Interconnect UIC layer and a first pin. The UFS device includes a second UIC layer configured to communicate with the first UIC layer and a second pin electrically connected to the first pin. The UFS host drives the voltage of the first pin based on first information indicating whether the High-Speed ​​Link Startup Sequence (HS-LSS) is supported by the UFS host, and the UFS device drives the voltage of the second pin based on second information indicating whether the HS-LSS is supported by the UFS device.

Aspects of the disclosure provide apparatuses and techniques for configuring system resources based on a configurable timeout of a wired communication link (e.g., peripheral component interconnect express (PCIe) link) in a standby mode to balance power and performance of the system. The configurable timeout can be based on a predicted link idle time.

The invention discloses a wireless optical communication system adopting an amplitude limiting amplification method, which relates to the technical field of wireless optical communication and comprises a transmitting subsystem and a receiving subsystem. The transmitting subsystem is used for generating a serial signal, processing the serial signal, converting the serial signal into an optical signal and transmitting the optical signal; and the receiving subsystem is used for receiving and converting the optical signal into a current signal, converting the current signal into a signal in a voltage form, amplifying the signal, performing waveform shaping and effective bandwidth expansion on the amplified signal through the nonlinear amplitude limiting characteristic of a bandwidth expansion module, and decoding and recovering the signal after bandwidth expansion. According to the invention, the bandwidth of the system is directly expanded by using the nonlinear amplitude limiting characteristic of the amplitude limiting amplifier, so that Gbps-level transmission is realized, and the rate bottleneck of the traditional LED system is overcome. Complex transmitting end equalization is not needed, the design is simplified, the robustness is enhanced, and the stability requirement of a satellite-borne environment high-speed link is met.

The invention is suitable for the technical field of automotive electronics, provides a vehicle-mounted diagnosis security access method and system based on heterogeneous computing power transfer, and aims to solve the problems of timeout, blocking real-time control and the like when a low-computing-power edge node executes high-strength asymmetric signature verification. The system is composed of a service interaction layer, a security routing layer, a core computing power layer and a board-level high-speed link. The method comprises the following steps: a target edge node receives a diagnosis request, requests a 32-byte challenge value from a gateway and feeds back the challenge value; after a 64-byte ECDSA signature is received, NRC 0x78 is sent, and data are packaged to initiate computing power transfer; the gateway converts the protocol and transmits the protocol to the SoC; the SoC executes signature verification based on the NIST P-256 and feeds back a result; and the target edge node unlocks the authority. According to the method, edge hardware does not need to be upgraded, the UN R155 compliance requirement is met at low cost, and diagnosis efficiency and vehicle real-time control safety are guaranteed.

A host module configured for insertion into a chassis of a network element includes a Printed Circuit Board (PCB); a plurality of rails disposed on the PCB, for housing one or more universal sub slot modules on the host module, wherein the plurality of rails are for guiding a universal sub slot module during insertion and for stabilization thereof; and a faceplate disposed to the PCB and including one or more openings each for the one or more universal sub slot modules, wherein the PCB communicates to each of the one or more universal sub slot modules via a plurality of high-speed links that are at least 28 Gbps each. At least one of the one or more universal sub slot modules can be a coherent modem or a router.

The invention discloses a high-speed connector. The high-speed connector comprises an insulating body; the conductive contact assembly is arranged on the insulating body, the conductive contact assembly comprises a plurality of first conductive contact pieces and a plurality of second conductive contact pieces, and the plurality of first conductive contact pieces and the plurality of second conductive contact pieces are arranged along the length direction of the insulating body; a first plugging space, a second plugging space and a communication channel are formed between the first conductive contact piece and the second conductive contact piece, the first plugging space and the second plugging space are communicated through the communication channel, and the communication channel is arranged in the first direction. The first plug-in space and the second plug-in space extend along the second direction and are arranged at intervals along the first direction, the first plug-in space is used for being matched with a high-speed connector in a plug-in manner, and the second plug-in space is used for being matched with an OCP card in a plug-in manner; the first direction and the second direction form an included angle. According to the scheme, the integration level is improved, the structure is compact, and a high-speed link is shortened.

1. Name of the product in this design: Switch with real-time status monitoring function. 2. Purpose of this product design: For signal switching, it identifies high-speed links or activity status by emitting blue light around the fiber optic port, enabling rapid identification of trunk ports. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The invention relates to EMI suppression for high speed cables. Disclosed are exemplary embodiments of an EMI absorber operable to suppress and / or absorb relatively high frequency EMI noise of a high speed cable for interconnection from chip to board, integrated circuit package to board, input / output panel to board, board to board, module to board, subsystem to board and supporting high speed interconnect technology standards (e.g., high speed interconnect technology standards, etc. The peripheral components are interconnected with high-speed 5 / 6 / 7 generations and computer high-speed links 3.1 and the like). In one embodiment, the EMI absorber includes a moldable thermoplastic EMI absorber configured to, when the EMI absorber is located on a portion or another component of the cable, e.g., when the EMI absorber completely and / or continuously surrounds a portion or another component of the cable (e.g., disposed 360 degrees, etc. The noise suppression device can be operated to suppress and / or absorb EMI noise from a cable or another component, wherein the EMI noise comprises frequencies of 5 gigahertz to 70 gigahertz.

The invention belongs to the technical field of electronic circuit design, and discloses a differential signal Fanout structure for improving the integrity of a high-speed signal, and the structure comprises a PCB substrate; the differential signal pair is arranged on the PCB substrate, the differential signal pair comprises a P signal wire and an N signal wire, and the P signal wire and the N signal wire are respectively used for connecting chip pins; and a ground shield unit. By adopting layered fan-out and large-spacing decoupling design, crosstalk of high-speed differential signals is remarkably reduced, the limitation that tight coupling wiring must be conducted on the same layer in a traditional Fanout structure is broken through, P signals and N signals are arranged on the surface layer and the inner layer of a PCB respectively, and therefore the signal transmission efficiency is improved. By means of isolation of a vertical space, maximization of horizontal projection spacing is achieved (a decoupling spacing area is formed), inter-line coupling capacitance is remarkably reduced, far-end crosstalk is remarkably reduced through the structure, and the signal-to-noise ratio and eye pattern opening of a high-speed link are improved.

The application discloses a kind of multi-frequency point signal random jitter modulation simulation link and simulation method suitable for high-speed link, mainly solve the problem that prior art relies on special test equipment and entity circuit sample, cannot accurately quantify multi-frequency point signal random jitter modulation amplification effect and cannot early fast complete jitter characteristic prediction.The implementation scheme includes: using simulation link, obtaining the spectrum of the sending end multi-frequency point signal and the corresponding link;Calculate the random jitter modulation coefficient corresponding to each single-frequency component;Establish the expression of the receiving end without jitter and with random jitter signal;Calculate the voltage variation and zero-crossing slope of the receiving end;Calculate the output random jitter value of the multi-frequency point signal after the link, use the value to calculate the random jitter modulation coefficient of the multi-frequency point signal.The application can avoid the dependence on special test equipment and circuit sample, accurately quantify the modulation amplification effect of random jitter itself in the link at the circuit design stage, and can be used for high-speed link jitter analysis and design evaluation.

Embodiments of the present application relate to the technical field of memory capacity expansion systems, and provide a memory capacity expansion system and method, an electronic device, and a storage medium. The method comprises: upon receiving a memory capacity expansion request signal, acquiring presence information for a memory module and a power supply control signal for a memory controller; when it is determined, by means of the presence information, that the memory module is present, and it is determined, by means of the power supply control signal, that the memory controller is in a powered-on state, copying memory data of the memory module; when the copying of the memory data is completed, controlling the memory controller to be powered off, wherein a memory connector is configured to be assembled with a newly added memory module when the copying of the memory data is completed and the memory controller is powered off; and identifying the newly added memory module on the basis of a high-speed communication protocol for a compute express link, thereby realizing non-fixed memory capacity expansion, avoiding fixed memory capacity expansion, and thus improving the memory capacity expansion efficiency.

The application provides a memory exception processing method and an electronic device; the method comprises the following steps: detecting that an exception occurs in a link between a computing high-speed link memory pool and the link, and acquiring link exception information; based on the link exception information, scheduling a fast path for accessing the computing high-speed link memory pool to a slow path for accessing a local memory space; acquiring a memory operation log of the computing high-speed link memory pool, and based on the memory operation log, restoring memory data between a latest checkpoint and the exception to the local memory space; the memory state before the checkpoint has been persisted; and based on the slow path and the memory data, continuing to perform read-write operations on the local memory space.

A system and method for implementing a high speed link between a mobile cache and an edge cache. For example, one embodiment of a system comprises: a mobile cache deployed on a vessel / vehicle, the mobile cache to store multimedia content to be provided to passengers on the vessel / vehicle; a first network device including a first plurality of wireless network antennas communicatively coupled to the mobile cache; an edge cache deployed at a designated location at which the vessel / vehicle is expected; a second network device including a second plurality of wireless network antennas communicatively coupled to the edge cache; wherein upon arrival at the designated location, each of the first plurality of wireless network antennas is paired with at least one of the second plurality of wireless network antennas to establish a plurality of simultaneous wireless links to exchange multimedia content between the edge cache and the mobile cache.

An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

The invention discloses a link state out-of-band monitoring method and a link state out-of-band monitoring product for a peripheral component interconnection high-speed link, and relates to the technical field of data transmission. Processing the unstructured link training and state machine log through a natural language processing technology to generate structured link training state transition information; converting the link training state transition information according to a preset coding rule to generate a preset state transition code; according to the link training state transition information, the preset state transition codes are sequenced according to the time sequence, the time sequence observation set is generated, the problem that link training and state machine log formats are isomerism is solved, and a uniform input format is provided for subsequent steps; and the time sequence observation set is input into the pre-trained link state monitoring model, so that the link state monitoring data can be output, and the problem of link state monitoring failure is solved.

The present disclosure relates to a computing high speed link (CXL) device configured to protect data by using data encryption and a method of operation thereof. An example CXL device includes a volatile memory and a CXL controller. The CXL controller receives first host data and a first host physical address from a first host device, translates the first host physical address into a first device physical address, obtains a first key index based on a key index table, the first host data, and the first device physical address, and transmits the first key index to the first host device. At least one first key is obtained based on the key table and the first key index, and an encryption operation is performed based on the at least one first key and an encryption algorithm.

The invention discloses a remote fault on-line positioning processing method, system and platform based on a floating tap sliding window and a storage medium, and aims to realize instrument-free and on-line automatic positioning of a remote fault of a high-speed link by configuring a floating tap in a decision feedback equalizer into a slidable detection window. The detection limitation that a standard fixed tap is only about 5cm is broken through, the effective diagnosis range is extended to 30cm through a parameter self-adaptive window sliding strategy, and a back plate and a key area at the tail end of a cable are completely covered. The spatial resolution is improved to a submillimeter level by combining energy detection with a centroid algorithm; through an original distance energy double-criterion mechanism, false peak values generated by multiple reflections can be effectively identified and inhibited, and only real physical faults are reported. Existing hardware resources of the chip are utilized in the whole process, external testing equipment or service interruption is not needed, and an efficient and low-cost automatic solution is provided for mass production testing, on-site operation and maintenance and monitoring of the high-speed link.

The invention discloses a transaction persistence method and device. The transaction persistence method comprises the steps of allocating a transaction number to a transaction based on the fact that a structured query language (SQL) list corresponding to the transaction is converted into a key-value pair list comprising at least one key-value pair; assigning a log sequence number (LSN) to each key value pair of the list of key value pairs; storing transaction metadata of the transaction in a metadata list stored in a dynamic random access memory (DRAM) that computes a high speed link (CXL) memory module (CMM-H) memory; and removing a pre-write log (WAL) from the LSM-tree relational database. The transaction metadata includes the transaction number, a first LSN of a first key-value pair of the list of key-value pairs, and one or more LSNs of the list of key-value pairs.

Universal flash storage (UFS) systems are provided. In one aspect, a UFS system includes a UFS host including a first UFS interconnect (UIC) layer and a first pin, and a UFS device including a second UIC layer configured to communicate with the first UIC layer and a second pin electrically connected to the first pin. The UFS host drives a voltage of the first pin based on first information indicating whether a high speed-link startup sequence (HS-LSS) is supported by the UFS host, and the UFS device drives a voltage of the second pin based on second information indicating whether the HS-LSS is supported by the UFS device.

A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

The utility model discloses an OLT equipment based on optical module standard package adopts standard SFP+ / XFP package shell, contain: SC / LC optical interface connection TO package's 1577nm electric absorption modulation laser, 1490nm distributed feedback laser and integrated TIA's 10G / 1.25G APD detector, laser drive unit contains input buffer and pre -drive circuit, burst receiving unit contains burst across resistance amplifier and limiting amplifier circuit, contain the XGSPON / XGPON / GPON MAC processing and management chip of meeting ITU-T G.9807.1, ITU-T G.987.1 and ITU-T G.984.x protocol specification through high -speed SerDes link connection support XGMII / HSGMII / SGMII interface's ethernet switch chip, and the equipment control unit integrates SFP+ / XFP management interface, and the golden finger interface circuit is directly connected switch chip through circuit board transmission line, and each unit is connected through optical fiber channel, circuit wiring and control bus, realizes OLT function modularization integration, reduces the deployment cost and power consumption.

The invention discloses a universal double-circuit mainboard high-speed signal optimization method, and relates to the technical field of mainboard signal optimization, and the method comprises the steps: collecting a power supply network input signal and a high-speed link differential signal error code sequence, calculating the cross spectrum density and coherence degree, and recognizing a dominant coupling peak frequency point with significant correlation between power supply noise and an error code; constructing a power supply integrity and signal integrity feasible action set and generating candidate combinations, and predicting the change effect of each combination on the influence coefficient through a multiplicative model; based on the power supply integrity suppression contribution degree, the signal integrity suppression contribution degree and the error code improvement amount, screening out an optimal parameter combination with the maximum total suppression contribution degree in combination with single-branch optimization and double-branch ratio criteria; and finally, implementing the combination and verifying the optimization effect by retesting the performance index. Accurate collaborative optimization of power supply integrity and signal integrity is realized, high-speed link signal quality and system stability are effectively improved, and the method is suitable for various mainboard configuration and topology scenes.

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.