85 results about "High-speed link" patented technology

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.

The invention relates to the technical field of adaptive routing optimization, and particularly discloses a topology self-recognition and routing optimization method and system for a concentrator and a collector, and the method comprises the steps: carrying out the topology modeling of a multi-layer heterogeneous network; executing high-speed link state monitoring based on the initial topological graph; global loop detection and link optimization are completed based on the link state matrix; a weighted robust multi-dimensional path selection method is adopted to configure a main path and a standby path for each node; and monitoring the path state in real time and dynamically switching. In the prior art, a static route, a single protocol path or a fixed main and standby path is mainly adopted, and especially in a cross-protocol, cross-level and dynamic multi-node environment in a smart city, rapid path switching and high-reliability route redundancy guarantee cannot be realized. Due to the fact that the multi-dimensional path selection method and the cross-level and cross-protocol self-adaptive switching strategy are adopted, the problems of routing interruption and performance reduction are avoided, and the reliability of the whole network is improved.

The invention relates to the technical field of digital communication, in particular to an intelligent electric meter dual-mode communication self-adaptive switching method, and provides the following scheme that operation data are divided into a plurality of data units at a sending end, priority evaluation is carried out, and the time delay, the packet loss, the energy consumption and the bandwidth state of two links are combined, so that the intelligent electric meter dual-mode communication self-adaptive switching method is realized. Positioning clearing cut points in the priority sequence so as to realize differentiated distribution of data between a high-speed link and a low-speed link; when the data is distributed to a low-speed link, sparse coding is carried out by adopting a preset dictionary, and differential updating is triggered when an error exceeds a limit, so that decoding consistency is ensured; a receiving end realizes unified analysis of the original message and the sparse message through cross-link association, dictionary updating and residual synthesis; according to the invention, the timeliness of the key message can be guaranteed, the communication energy consumption and cost can be reduced, and the cooperation efficiency of the dual-mode link can be improved.

The present application relates to the field of data processing, and disclosed are a network card device and a data transmission system, which are used for solving the problem whereby data transmission occupies the access bandwidth of a host memory. The network card device comprises a storage module; a descriptor queue address register; a calculation high-speed link hard core module, which is used for transmitting data sent by a host to a first data storage area, transmitting a descriptor sent by the host to a first descriptor storage area, and transmitting a trigger instruction sent by the host to a network data processing module; and the network data processing module, which is used for acquiring a base address from the descriptor queue address register when receiving the trigger instruction, reading a target descriptor in the first descriptor storage area based on the base address and the trigger instruction, reading target data corresponding to the target descriptor in the first data storage area, and outputting the target data to a network. The present application can reserve the access bandwidth of a host memory for other functions running on the host to use, so that the overall operation efficiency of the host is improved.

The present application relates to the field of accelerated computing. Disclosed are an acceleration device and a computing acceleration system, which aim to solve the problem of large data transmission delays in a computing process. The acceleration device comprises: a compute express link hard-core module, which is used for receiving a computing request sent by a host and forwarding the computing request; and an accelerated computing module configured with an asymmetric encryption algorithm, which accelerated computing module is used for accessing, when the computing request is received and on the basis of the computing request, data to be computed that is generated by the host and is in an address space subjected to unified addressing, performing asymmetric encryption computing on said data on the basis of an asymmetric encryption and decryption algorithm to obtain result data, and writing the result data into the address space subjected to unified addressing, such that the host accesses the result data in the address space subjected to unified addressing. The present application can reduce the frequency of data migration in an acceleration process, thereby shortening the data transmission delay.

The invention discloses an evaluation method of a high-speed link system, an electronic device and a non-transient storage medium, relates to the technical field of high-speed electronic interconnection, and provides a method for setting a cutting plane at the geometric height center of an electrical connection structure as a boundary position of sub-link simulation and cascade. Impedance discontinuity and parasitic effect actually existing in the structure can be completely incorporated into simulation evaluation, the defect that a traditional segmented cascade method cannot reflect actual electromagnetic behaviors of the interconnection structure is overcome, simulation accuracy is improved, modeling efficiency and engineering practicability are taken into consideration, and the method is suitable for large-scale popularization and application. The method can be widely applied to performance evaluation and optimization design of various high-speed packaging interconnection systems.

A method for reducing latency in a peripheral component interconnect express (PCIe) link between a PCIe root complex and a PCIe device is provided. The method includes measuring, by the PCIe device, a throughput of data transmission that is sent to a buffer of the PCIe device. The method includes determining, by the PCIe device, a latency tolerance reporting (LTR) value based on the measured throughput. The method includes transmitting, by the PCIe device, the LTR value to the PCIe root complex at an estimated time point via the PCIe link, wherein the estimated time point is prior to a time at which a buffer switching operation occurs.

The invention relates to a vehicle-mounted communication processing method, device and system, a vehicle and a storage medium. The method is applied to a sending end, the sending end comprises a user layer, a middleware layer and a link layer, and the method comprises the following steps: obtaining user layer data of the user layer through the middleware layer; obtaining link selection reference information of the sending link; when it is determined that a link layer has a high-speed link according to the link selection reference information and the high-speed link is enabled, selecting the high-speed link as a sending link; transmitting the user layer data to the link layer; and sending the user layer data to a receiving end at the link layer through the sending link. According to the scheme provided by the invention, the requirement of the end-to-end large model service of the self-driving system for cross-SOC ultra-large flow can be met.

The invention discloses a heterogeneous networking architecture and method based on an electric red-hong system distributed soft bus, the heterogeneous networking architecture comprises an equipment grading module, a hybrid topology networking module, a main / standby path configuration module and a communication protocol adaptation module, the equipment grading module divides equipment into a rich type and a thin type according to capability, the rich equipment takes the core role of relay and calculation, and the thin equipment takes the core role of relay and calculation; the thin device focuses on the basic function, accurate resource allocation is achieved, and computing power waste is avoided; the hybrid topology networking module enables rich equipment to construct a mesh topology through a high-speed link, and multi-path transmission of key data is guaranteed; the thin device is connected with the rich device in a single-hop mode to form a star topology, connection is simplified, the communication range is expanded by means of the rich device, and efficiency and coverage are both considered; the main and standby path configuration module is used for configuring double paths for equipment, and automatic switching is realized when a main path fails, so that the anti-fault capability is greatly improved, and equipment disconnection caused by a single link fault is completely eradicated; the communication protocol adaptation module dynamically selects a protocol according to needs, breaks the protocol barrier, reduces the conversion delay, and improves the overall communication efficiency and compatibility.

The disclosure relates to freeze commands and restore commands associated with a flag capacity for computing a high speed link (CXL) memory device. A system may include a memory device including a plurality of dynamic capacity devices; and a processing device operably coupled with the memory device. The processing device is configured to perform operations including receiving a host command to freeze first data associated with a first flag associated with a first memory segment of a plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data.

The application discloses a high-speed link signal equalization method based on a three-dimensional memristor type equalizer, which comprises the following steps: obtaining a distorted signal and generating an ideal received signal, and then constructing a data set; training a recurrent neural network by using the data set to obtain a trained weight parameter; obtaining a conductance value matrix in the three-dimensional memristor type equalizer by mapping the weight parameter; deploying the conductance value to the three-dimensional memristor type equalizer according to the conductance value matrix; and finally inputting the distorted signal into the three-dimensional memristor type equalizer to obtain an optimized signal after compensation distortion. Compared with the traditional feedforward equalizer and decision feedback equalizer method, the application effectively reduces the time domain waveform distortion, improves the high-speed signal integrity, has wide applicability, can be used for the training and deployment application of the memristor type equalizer of various complex high-speed links, and deploys the above-mentioned conductance value to the three-dimensional memristor cross array, so as to improve the integrated density and reduce the area occupied by the equalizer.

The present disclosure relates to a computing high speed link (CXL) device configured to protect data by using data encryption and a method of operation thereof. An example CXL device includes a volatile memory connected to a plurality of channels; and a CXL controller. The CXL controller includes: a CXL subsystem controller configured to search a key index table for a first key index based on first host data and a first device physical address; and a memory subsystem controller configured to search for at least one first key in a key table based on the first key index, and generate first encrypted data based on the first data, the first device physical address, the at least one first key, and an encryption algorithm.

A system and method for implementing a high speed link between a mobile cache and an edge cache. For example, one embodiment of a system comprises: a mobile cache deployed on a vessel / vehicle, the mobile cache to store multimedia content to be provided to passengers on the vessel / vehicle; a first network device including a first plurality of wireless network antennas communicatively coupled to the mobile cache; an edge cache deployed at a designated location at which the vessel / vehicle is expected; a second network device including a second plurality of wireless network antennas communicatively coupled to the edge cache; wherein upon arrival at the designated location, each of the first plurality of wireless network antennas is paired with at least one of the second plurality of wireless network antennas to establish a plurality of simultaneous wireless links to exchange multimedia content between the edge cache and the mobile cache.

A general-purpose flash memory UFS device, a UFS system, and a method of operating the UFS system are provided. In one aspect, the UFS system includes a UFS host and a UFS device. The UFS host includes a first UFS Interconnect UIC layer and a first pin. The UFS device includes a second UIC layer configured to communicate with the first UIC layer and a second pin electrically connected to the first pin. The UFS host drives the voltage of the first pin based on first information indicating whether the High-Speed ​​Link Startup Sequence (HS-LSS) is supported by the UFS host, and the UFS device drives the voltage of the second pin based on second information indicating whether the HS-LSS is supported by the UFS device.

The present disclosure provides a CXL structure extension. One aspect of the present application may provide a networked device. The networked device may include a set of compute high speed link (CXL) ports, a set of non-CXL ports, a set of bridge circuits associated with the set of CXL ports, and an interconnect. A respective bridge circuit may include a packet conversion sub-circuit to convert a CXL packet received at a corresponding CXL port to a customized packet, and a protocol conversion sub-circuit to convert a CXL protocol to a customized protocol implemented by a networked device. The interconnect may switch custom packets between the CXL and non-CXL ports based on a custom protocol.

Aspects of the disclosure provide apparatuses and techniques for configuring system resources based on a configurable timeout of a wired communication link (e.g., peripheral component interconnect express (PCIe) link) in a standby mode to balance power and performance of the system. The configurable timeout can be based on a predicted link idle time.

The invention discloses a wireless optical communication system adopting an amplitude limiting amplification method, which relates to the technical field of wireless optical communication and comprises a transmitting subsystem and a receiving subsystem. The transmitting subsystem is used for generating a serial signal, processing the serial signal, converting the serial signal into an optical signal and transmitting the optical signal; and the receiving subsystem is used for receiving and converting the optical signal into a current signal, converting the current signal into a signal in a voltage form, amplifying the signal, performing waveform shaping and effective bandwidth expansion on the amplified signal through the nonlinear amplitude limiting characteristic of a bandwidth expansion module, and decoding and recovering the signal after bandwidth expansion. According to the invention, the bandwidth of the system is directly expanded by using the nonlinear amplitude limiting characteristic of the amplitude limiting amplifier, so that Gbps-level transmission is realized, and the rate bottleneck of the traditional LED system is overcome. Complex transmitting end equalization is not needed, the design is simplified, the robustness is enhanced, and the stability requirement of a satellite-borne environment high-speed link is met.

The invention is suitable for the technical field of automotive electronics, provides a vehicle-mounted diagnosis security access method and system based on heterogeneous computing power transfer, and aims to solve the problems of timeout, blocking real-time control and the like when a low-computing-power edge node executes high-strength asymmetric signature verification. The system is composed of a service interaction layer, a security routing layer, a core computing power layer and a board-level high-speed link. The method comprises the following steps: a target edge node receives a diagnosis request, requests a 32-byte challenge value from a gateway and feeds back the challenge value; after a 64-byte ECDSA signature is received, NRC 0x78 is sent, and data are packaged to initiate computing power transfer; the gateway converts the protocol and transmits the protocol to the SoC; the SoC executes signature verification based on the NIST P-256 and feeds back a result; and the target edge node unlocks the authority. According to the method, edge hardware does not need to be upgraded, the UN R155 compliance requirement is met at low cost, and diagnosis efficiency and vehicle real-time control safety are guaranteed.

A host module configured for insertion into a chassis of a network element includes a Printed Circuit Board (PCB); a plurality of rails disposed on the PCB, for housing one or more universal sub slot modules on the host module, wherein the plurality of rails are for guiding a universal sub slot module during insertion and for stabilization thereof; and a faceplate disposed to the PCB and including one or more openings each for the one or more universal sub slot modules, wherein the PCB communicates to each of the one or more universal sub slot modules via a plurality of high-speed links that are at least 28 Gbps each. At least one of the one or more universal sub slot modules can be a coherent modem or a router.

A receiver including a preamplifier circuit and an amplifier circuit is disclosed. The preamplifier circuit includes first and second input terminals to receive a signal from a transmitter; first and second output terminals that output signals to the amplifier circuit; a first resistor having a first terminal coupled to the first input terminal and a second terminal coupled to a first node; a second resistor having a first terminal coupled to the second input terminal and a second terminal coupled to the first node; a third resistor having a first terminal coupled to the first output terminal and a second terminal coupled to a second node; a fourth resistor having a first terminal coupled to the second output terminal and a second terminal coupled to the second node; and a switch having a first terminal coupled to the first node and a second terminal coupled to the second node.

The invention discloses a high-speed connector. The high-speed connector comprises an insulating body; the conductive contact assembly is arranged on the insulating body, the conductive contact assembly comprises a plurality of first conductive contact pieces and a plurality of second conductive contact pieces, and the plurality of first conductive contact pieces and the plurality of second conductive contact pieces are arranged along the length direction of the insulating body; a first plugging space, a second plugging space and a communication channel are formed between the first conductive contact piece and the second conductive contact piece, the first plugging space and the second plugging space are communicated through the communication channel, and the communication channel is arranged in the first direction. The first plug-in space and the second plug-in space extend along the second direction and are arranged at intervals along the first direction, the first plug-in space is used for being matched with a high-speed connector in a plug-in manner, and the second plug-in space is used for being matched with an OCP card in a plug-in manner; the first direction and the second direction form an included angle. According to the scheme, the integration level is improved, the structure is compact, and a high-speed link is shortened.

The present invention relates to a high-bandwidth EML substrate, comprising a PCB board, a CUW substrate, and an ALN ​​substrate; wherein the PCB board processes high-speed digital signals; the ALN substrate has two sides, front and back, wherein a circuit for processing high-speed analog signals is arranged on the front of the ALN substrate; one side of the back of the ALN substrate has a step-shaped depression in the thickness direction, an EML chip is arranged in the step-shaped depression, the depth of the step-shaped depression is greater than the thickness of the EML chip, so that when the EML chip is soldered to the step-shaped depression in the form of a gold-tin solder ball, the EML chip does not expose the back of the ALN substrate; the non-step-shaped depression part of the back of the ALN substrate is attached to the CUW substrate in a manner that is conducive to heat conduction; the CUW substrate is connected to the PCB board, so that the ALN substrate and the PCB board are not in direct contact with each other. The present invention can optimize the ‑3dB bandwidth of the high-speed link of the EML substrate from the existing 40GHz to more than 70GHz.

1. Name of the product in this design: Switch with real-time status monitoring function. 2. Purpose of this product design: For signal switching, it identifies high-speed links or activity status by emitting blue light around the fiber optic port, enabling rapid identification of trunk ports. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The invention relates to EMI suppression for high speed cables. Disclosed are exemplary embodiments of an EMI absorber operable to suppress and / or absorb relatively high frequency EMI noise of a high speed cable for interconnection from chip to board, integrated circuit package to board, input / output panel to board, board to board, module to board, subsystem to board and supporting high speed interconnect technology standards (e.g., high speed interconnect technology standards, etc. The peripheral components are interconnected with high-speed 5 / 6 / 7 generations and computer high-speed links 3.1 and the like). In one embodiment, the EMI absorber includes a moldable thermoplastic EMI absorber configured to, when the EMI absorber is located on a portion or another component of the cable, e.g., when the EMI absorber completely and / or continuously surrounds a portion or another component of the cable (e.g., disposed 360 degrees, etc. The noise suppression device can be operated to suppress and / or absorb EMI noise from a cable or another component, wherein the EMI noise comprises frequencies of 5 gigahertz to 70 gigahertz.

The embodiment of the invention provides an aging test verification structure and a test method, and relates to the technical field of semiconductor design, and the aging test verification structure comprises at least one high-speed plate layer which is provided with a high-speed link and is used for transmitting a high-speed signal; the at least one low-speed plate layer is positioned on one side of the high-speed plate layer, is provided with a low-speed link and is used for transmitting a low-speed signal; the input end is used for acquiring the low-speed signal or the high-speed signal; and the output end is connected with the input end through the high-speed link or connected with the input end through the low-speed link. According to the aging test board, the problem of high measurement cost often occurs when a high-performance aging test board is adopted, so that the effect of saving the test cost is achieved.

The invention belongs to the technical field of electronic circuit design, and discloses a differential signal Fanout structure for improving the integrity of a high-speed signal, and the structure comprises a PCB substrate; the differential signal pair is arranged on the PCB substrate, the differential signal pair comprises a P signal wire and an N signal wire, and the P signal wire and the N signal wire are respectively used for connecting chip pins; and a ground shield unit. By adopting layered fan-out and large-spacing decoupling design, crosstalk of high-speed differential signals is remarkably reduced, the limitation that tight coupling wiring must be conducted on the same layer in a traditional Fanout structure is broken through, P signals and N signals are arranged on the surface layer and the inner layer of a PCB respectively, and therefore the signal transmission efficiency is improved. By means of isolation of a vertical space, maximization of horizontal projection spacing is achieved (a decoupling spacing area is formed), inter-line coupling capacitance is remarkably reduced, far-end crosstalk is remarkably reduced through the structure, and the signal-to-noise ratio and eye pattern opening of a high-speed link are improved.

Given the potential high data rate and confidentiality of optical wireless communication, Li-Fi proves to be an attractive technology for enabling high-speed wireless data transmission between remote devices. The present invention relates to various methods, systems, and devices for achieving high-speed file transfer between a user-held device (300) and a remote device (400) via a high-speed Li-Fi link (200). When the user-held device (300) receives a trigger command, a trigger signal is sent to the remote device (400) via another communication link (500) having a wide beam width. The remote device (400) provides a human-perceivable indication of a dedicated reception area after receiving the trigger signal to assist the user in aligning the user-held device (300) for the alignment required to enable the high-speed Li-Fi link (200). After determining that the alignment state permits file transfer, or after the user-held device (300) receives a start transmission command, high-speed file transfer begins.

The invention discloses a high-speed link signal equalization method based on a three-dimensional memristor type equalizer, and the method comprises the steps: obtaining a distortion signal, generating an ideal receiving signal, and constructing a data set; training the recurrent neural network by using the data set to obtain a trained weight parameter; performing mapping processing on the weight parameters to obtain a conductance value matrix in the three-dimensional memristor type equalizer; deploying the conductance values to the three-dimensional memristor type equalizer according to the conductance value matrix; and finally, inputting the distorted signal into a three-dimensional memristor type equalizer for processing to obtain an optimized signal after distortion compensation. Compared with a traditional feedforward equalizer and decision feedback equalizer method, the method has the advantages that time domain waveform distortion is effectively reduced, high-speed signal integrity is improved, the method has wide applicability, the method can be used for memristor type equalizer training and deployment application of various complex high-speed links, the conductance value is deployed to a three-dimensional memristor cross array, and the method is suitable for training and deployment application of memristor type equalizers of various complex high-speed links. Therefore, the integration density is improved and the occupied area of the equalizer is reduced.

The present invention relates to the field of radar signal processing, and in particular to a method for quickly detecting the operating frequency of an externally interfered radar. The present invention adopts an AD radio frequency sampling chip, and the front end of the radar receiver only has filtering and amplification links. The broadband signal A / D conversion is placed close to the radio frequency antenna, which can quickly digitize analog signals with larger amplitudes. At the same time, the sampling signal is digitally mixed and filtered and extracted inside the AD chip to reduce the amount of data transmitted and the subsequent data processing time. The FPGA receives the AD sampled I / Q data through the JESD204B high-speed link, and only performs mixing and filtering on the I / Q data to calculate the signal amplitude value, so that the frequency of the interference signal can be determined. The method has a small number of devices, a simple architecture, a small amount of calculation, and low requirements for FPGA chip resources, while greatly shortening the time consumed in interference detection.

The application discloses a kind of multi-frequency point signal random jitter modulation simulation link and simulation method suitable for high-speed link, mainly solve the problem that prior art relies on special test equipment and entity circuit sample, cannot accurately quantify multi-frequency point signal random jitter modulation amplification effect and cannot early fast complete jitter characteristic prediction.The implementation scheme includes: using simulation link, obtaining the spectrum of the sending end multi-frequency point signal and the corresponding link;Calculate the random jitter modulation coefficient corresponding to each single-frequency component;Establish the expression of the receiving end without jitter and with random jitter signal;Calculate the voltage variation and zero-crossing slope of the receiving end;Calculate the output random jitter value of the multi-frequency point signal after the link, use the value to calculate the random jitter modulation coefficient of the multi-frequency point signal.The application can avoid the dependence on special test equipment and circuit sample, accurately quantify the modulation amplification effect of random jitter itself in the link at the circuit design stage, and can be used for high-speed link jitter analysis and design evaluation.