10 results about "High-speed link" patented technology

A general-purpose flash memory UFS device, a UFS system, and a method of operating the UFS system are provided. In one aspect, the UFS system includes a UFS host and a UFS device. The UFS host includes a first UFS Interconnect UIC layer and a first pin. The UFS device includes a second UIC layer configured to communicate with the first UIC layer and a second pin electrically connected to the first pin. The UFS host drives the voltage of the first pin based on first information indicating whether the High-Speed ​​Link Startup Sequence (HS-LSS) is supported by the UFS host, and the UFS device drives the voltage of the second pin based on second information indicating whether the HS-LSS is supported by the UFS device.

Aspects of the disclosure provide apparatuses and techniques for configuring system resources based on a configurable timeout of a wired communication link (e.g., peripheral component interconnect express (PCIe) link) in a standby mode to balance power and performance of the system. The configurable timeout can be based on a predicted link idle time.

An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

Universal flash storage (UFS) systems are provided. In one aspect, a UFS system includes a UFS host including a first UFS interconnect (UIC) layer and a first pin, and a UFS device including a second UIC layer configured to communicate with the first UIC layer and a second pin electrically connected to the first pin. The UFS host drives a voltage of the first pin based on first information indicating whether a high speed-link startup sequence (HS-LSS) is supported by the UFS host, and the UFS device drives a voltage of the second pin based on second information indicating whether the HS-LSS is supported by the UFS device.

The application discloses a high-speed link equalization method based on a time sequence neural network. The method comprises the following steps: constructing a high-speed link simulation system comprising a high-speed link transmission unit and a neural network equalizer unit; the high-speed link transmission unit outputs discrete sampling data corresponding to a distorted signal, the neural network equalizer unit comprises a signal preprocessing module for generating an input vector according to the discrete sampling data, a neural network calculation module for generating an output vector according to the input vector through an equalizer RNN model, a signal post-processing module for serializing the output vector into a single-flow time sequence and a subsystem control module for time sequence control; after the target equalizer RNN model is deployed, simulation is performed to obtain an equalized signal. The long-time memory characteristic of the time sequence neural network can effectively compensate for complex nonlinear distortion and inter-symbol interference in a high-speed channel, and compared with a traditional equalization method, the eye height and the eye width of an output eye diagram are significantly increased, and the signal integrity of a high-speed circuit is improved.

The utility model discloses an OLT equipment based on optical module standard package adopts standard SFP+ / XFP package shell, contain: SC / LC optical interface connection TO package's 1577nm electric absorption modulation laser, 1490nm distributed feedback laser and integrated TIA's 10G / 1.25G APD detector, laser drive unit contains input buffer and pre -drive circuit, burst receiving unit contains burst across resistance amplifier and limiting amplifier circuit, contain the XGSPON / XGPON / GPON MAC processing and management chip of meeting ITU-T G.9807.1, ITU-T G.987.1 and ITU-T G.984.x protocol specification through high -speed SerDes link connection support XGMII / HSGMII / SGMII interface's ethernet switch chip, and the equipment control unit integrates SFP+ / XFP management interface, and the golden finger interface circuit is directly connected switch chip through circuit board transmission line, and each unit is connected through optical fiber channel, circuit wiring and control bus, realizes OLT function modularization integration, reduces the deployment cost and power consumption.

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.

This application relates to the field of prototyping technology, and discloses a rapid prototyping method, device, and storage medium based on a 100G network. In a NoC using a 2D Torus topology, a data synchronization module is set up for each routing node to capture data communication packets in all directions and the node's internal register status in real time, and cache them locally. Multiple routing nodes are grouped together and share a high-speed 100G network module. Through register configuration, the host dynamically selects specific routing nodes, controls the 100G network module to read the cached data of the selected nodes in a round-robin manner, and encapsulates it into network packets with timestamps, node location, and direction markers. These packets are then transmitted in real time to the host via a 100G high-speed link for parsing, visualization, and reconstruction. This solves the problems of insufficient comprehensive monitoring of on-chip network internal signals and insufficient bandwidth of traditional probes in existing large-scale SoC prototyping.

The application discloses a data processing method and device for a front-end electronics module, which comprises the following steps: collecting waveform data from a detector according to channels, merging data of 8 adjacent channels into a group, and storing the group into a first-level FIFO memory; compressing the collected data, compressing the data according to the characteristics of pulse signals, and storing compressed data of 64 adjacent channels into a second-level FIFO memory; dividing a DDR into 16 independent caches, and performing partition cache management; dynamically transferring data between different cache regions according to the storage conditions of the 16 cache regions of the DDR; transferring data between multiple front-end electronics modules through a GT port according to the storage conditions of the multiple front-end electronics modules; and uploading data to a back-end data acquisition system through a high-speed link. The method reduces the waveform data rate and reduces the transmission pressure through segmented compression, layered caching, intra-module balancing and inter-module balancing.