A memory exception processing method and an electronic device

Abstract

The application provides a memory exception processing method and an electronic device; the method comprises the following steps: detecting that an exception occurs in a link between a computing high-speed link memory pool and the link, and acquiring link exception information; based on the link exception information, scheduling a fast path for accessing the computing high-speed link memory pool to a slow path for accessing a local memory space; acquiring a memory operation log of the computing high-speed link memory pool, and based on the memory operation log, restoring memory data between a latest checkpoint and the exception to the local memory space; the memory state before the checkpoint has been persisted; and based on the slow path and the memory data, continuing to perform read-write operations on the local memory space.

Description

Technical Field

[0001] This application relates to the field of memory exception handling technology, and in particular to a method and electronic device for handling memory exceptions. Background Technology

[0002] In the fields of large models, artificial intelligence (AI), and machine learning (ML), data processing demands are growing exponentially, posing unprecedented challenges to memory capacity and performance. Compute Express Link (CXL), as an emerging interconnect technology, offers a key technological path to overcome these memory expansion bottlenecks due to its high-speed, low-latency connectivity. However, with the continuous expansion of CXL memory application scenarios, in CXL memory pooling scenarios, if multiple hosts access a shared memory pool via CXL interconnect and the host experiences an anomaly in the link between the CXL memory pooling and the host, the hosts will be unable to perform normal data read and write operations on the CXL memory, thus reducing the security of CXL memory pooling. Summary of the Invention

[0003] This application provides a method for handling memory exceptions and an electronic device.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides a method for handling memory exceptions, the method including: An anomaly was detected in the link between the high-speed computing link memory pool, and link anomaly information was obtained. Based on link anomaly information, the fast path that accesses the high-speed link memory pool is scheduled to the slow path that accesses the local memory space. Obtain the memory operation log of the high-speed link memory pool. Based on the memory operation log, restore the memory data between the most recent checkpoint and the occurrence of the anomaly to the local memory space; the memory state before the checkpoint has been persisted. Based on the slow path and memory data, continue to perform read and write operations on the local memory space.

[0005] This application provides an electronic device, including: local memory and a processor; The processor is used to detect an anomaly in the link between the high-speed computing link memory pool and obtain link anomaly information; based on the link anomaly information, it schedules the fast path accessing the high-speed computing link memory pool to the slow path accessing the local memory space in local memory; it obtains the memory operation log of the high-speed computing link memory pool, and based on the memory operation log, restores the memory data between the most recent checkpoint and the anomaly to the local memory space; the memory state before the checkpoint has been persisted; based on the slow path and memory data, it continues to perform read and write operations on the local memory space. Attached Figure Description

[0006] Figure 1 This is a flowchart illustrating a memory exception handling method provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a scheduling access path provided in an embodiment of this application. Figure 1 ; Figure 3 This is a schematic flowchart of an exemplary memory data recovery method provided in an embodiment of this application; Figure 4 This is a schematic diagram of an exemplary scheduling access path provided in an embodiment of this application. Figure 2 ; Figure 5 This is a flowchart illustrating an exemplary memory operation log processing method provided in an embodiment of this application; Figure 6 This is a schematic diagram of an exemplary fast path provided in an embodiment of this application; Figure 7 This is a schematic diagram of an exemplary slow path provided in an embodiment of this application; Figure 8 A schematic diagram illustrating an application scenario provided in an embodiment of this application; Figure 9 A schematic diagram of the structure of an exemplary electronic device provided in an embodiment of this application; Figure 10 A flowchart illustrating an exemplary memory exception handling method provided in this application embodiment. Figure 2 ; Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0007] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0008] In the fields of large models, artificial intelligence (AI), and machine learning (ML), data processing demands are growing exponentially, posing unprecedented challenges to memory capacity and performance. Traditional Dynamic Random Access Memory (DRAM) solutions face significant bottlenecks in cost control, capacity expansion, and scalability, making it difficult to scale in sync with application needs. Meanwhile, the prevalent demand for resource overselling in cloud computing scenarios, coupled with applications' continuous demands for increased memory capacity and bandwidth, is driving the rapid iteration of memory expansion technologies.

[0009] As an emerging interconnect technology, CXL offers a key technological path to overcome the aforementioned memory expansion bottlenecks due to its high-speed and low-latency connectivity. Against this backdrop, CXL memory has become the most promising technological direction for solving the memory expansion problem. With the continuous expansion of CXL memory application scenarios, CXL memory pooling technology, through centralized management of distributed memory resources, supports multiple hosts in dynamically allocating and releasing memory resources on demand, effectively improving memory resource utilization.

[0010] However, in a CXL Memory Pooling scenario, when multiple hosts access the shared memory pool via CXL interconnect, if the link between the CXL memory pooling and the host fails, preventing the host from performing normal data read and write operations on the CXL memory, a series of serious problems will arise, as follows: 1. Host crash: When the link between CXL memory pooling and the host is abnormal, the application may trigger a segmentation fault due to the invalidation of CXL memory address during the reading and writing of CXL memory, which may even cause the host to crash.

[0011] 2. Data security risks: Other hosts may access dirty data (incompletely written or incompletely verified data) or invalid data left behind by the crashed host, which will not only affect the accuracy of the data, but may also cause the system to crash in severe cases.

[0012] 3. Memory pool consistency and isolation compromise: Memory regions not released by hosts with broken links may interfere with the normal memory access of other hosts, compromising the consistency and isolation of the memory pool.

[0013] 4. System paralysis risk: In practical applications, the host may malfunction due to various reasons such as power failure of CXL memory pooling, link interruption, or poor line contact. If the host fails to release the memory-shared lock after a link failure, other hosts may be unable to acquire the lock for an extended period and remain in a "frozen" state, ultimately causing the entire business system to malfunction.

[0014] The memory management mechanisms of operating systems in related technologies are not suitable for CXL memory pooling host recovery scenarios. Furthermore, the existing PCIe / CXL specification does not yet provide a complete link anomaly recovery mechanism. Therefore, a new CXL memory host collaborative recovery mechanism is urgently needed to improve the reliability and consistency of shared memory systems and ensure the security and high availability of CXL memory pooling.

[0015] This application provides a method for handling memory exceptions, implemented by an electronic device, such as... Figure 1 As shown, the process includes the following steps S101 to S104: Step S101: An anomaly is detected in the link between the high-speed link memory pool and the computing link, and the link anomaly information is obtained.

[0016] In the embodiments of this application, the electronic device is a device with memory exception handling function. Exemplary electronic devices may be tablet computers, laptop computers, handheld computers, personal digital assistants (PDAs), desktop computers, servers, etc. The exemplary electronic devices are not limited here.

[0017] In the embodiments of this application, there is a link connection between the electronic device and the high-speed computing link memory pool. For example, the electronic device can be directly connected to the CXL memory pool through the CXL root port, or the electronic device can be connected to the high-speed computing link memory pool through the CXL switch port; or, multiple electronic devices (such as CPU, GPU, DPU) can share the CXL memory pool through the CXL switch and Fabric Manager.

[0018] In the embodiments of this application, if an electronic device is connected to the high-speed computing link memory pool via a CXL switch port, the status of the link layer between the electronic device and the CXL switch port can be detected to determine whether the electronic device has experienced a power outage or malfunction. If the status of the link layer between the electronic device and the CXL switch port is detected and it is determined that the electronic device has experienced a power outage or malfunction, then it is determined that the link between the electronic device and the high-speed computing link memory pool is abnormal.

[0019] In the embodiments of this application, if the electronic device is directly connected to the CXL memory pool through the CXL root port, the status of the link layer between the electronic device and the CXL root port can be detected to determine whether the electronic device has lost power or is malfunctioning.

[0020] Step S102: Based on the link anomaly information, schedule the fast path that accesses the high-speed link memory pool to the slow path that accesses the local memory space.

[0021] In embodiments of this application, an electronic device can switch from a fast path to a slow path to a local memory space based on link anomaly information, which is used to access the high-speed link memory pool.

[0022] For example, switching the fast path to access the high-speed memory pool of the computing link to the slow path to access the local memory space can be achieved by disabling Remote Direct Memory Access (RDMA) support in the distributed framework and forcing the use of Transmission Control Protocol (TCP) / Internet Protocol (IP) or local memory communication.

[0023] For example, disabling NVLink bridging in the Basic Input / Output System (BIOS) or Graphics Processing Unit (GPU) driver settings forces the GPU to use local memory.

[0024] Step S103: Obtain the memory operation log of the high-speed link memory pool. Based on the memory operation log, restore the memory data between the most recent checkpoint and the occurrence of the anomaly to the local memory space; the memory state before the checkpoint has been persisted.

[0025] In the embodiments of this application, after the electronic device detects an anomaly in the link between itself and the high-speed computing link memory pool, it can obtain the memory operation log corresponding to the high-speed computing link memory pool. The memory operation log stores the content of each step of the electronic device's operation on the CXL memory, and the memory operation log will serve as the basis for data recovery when the link is abnormal.

[0026] In the embodiments of this application, after obtaining the memory operation log, the electronic device can restore the content data between the most recent checkpoint and the occurrence of the anomaly to the local memory space based on the memory operation log.

[0027] In the embodiments of this application, the persistence of the memory state before the checkpoint is essentially achieved by solidifying the dynamic data in memory to persistent storage when the checkpoint is created, ensuring that the correct state at the checkpoint can be restored after an anomaly. In this way, the electronic device can re-execute the operations performed on the high-speed link memory pool after the most recent checkpoint in the memory operation log, and store the executed data in the local memory space, so that the operations that were in progress before the anomaly can continue.

[0028] Step S104: Based on the slow path and memory data, continue to perform read and write operations on the local memory space.

[0029] In the embodiments of this application, after restoring memory data to the local memory space, the electronic device can perform read and write operations on the memory data in the local memory space based on the slow path.

[0030] Thus, after an anomaly occurs in the link between the high-speed computing link memory pool, the memory data after the checkpoint is replayed to the local memory space based on the memory operation log, and read and write operations are performed on the local memory space to continue the operations executed when the link was abnormal. This enables lossless data recovery, uninterrupted host services, and system-level high availability in the event of a link anomaly.

[0031] In some embodiments, anomalies include at least an abnormal state of the compute high-speed link port read, or a hardware error; abnormal state includes at least no signal detected, negotiation failure, or link disabled; hardware errors include at least an excessive number of checksum errors, signal loss, or link reset timeout.

[0032] For example, the electronic device can periodically read the LTSSM register status of the physical port of the CXL switch through the Fabric Manager of the CXL switch. If the link remains in an active state (L0) or a low-power state (L0s), the link status is considered normal. If the status is "Detect," "Polling," or "Disabled," it is directly determined that the link is faulty (the physical link has failed). At the same time, the Fabric Manager will periodically read the error status register. If hardware errors such as "SerDes signal loss (LOS)," "CRC check error accumulation exceeds the limit," or "link reset timeout" are detected, an alarm will be immediately triggered to the upper-layer scheduling module, that is, it is determined that the link between the electronic device and the high-speed computing link memory pool is abnormal.

[0033] In this way, by monitoring the physical port of the CXL switch, it is possible to determine whether any abnormalities have occurred, thereby improving the efficiency of anomaly detection.

[0034] In some embodiments, the link anomaly information includes at least one or more of the following: host identification information, physical port identification information, anomaly code representing the anomaly type, and a timestamp of the anomaly occurrence.

[0035] In the embodiments of this application, when the CXL link anomaly detection module reports a link anomaly, it obtains the link anomaly information and then reports the link anomaly information. The reported content may include: MSG_LINK_ERROR{ uint8_t host_id; uint8_t port_id; uint16_t error_code; uint64_t timestamp; } In the embodiments of this application, when a CXL link anomaly is detected, the CXL link anomaly detection module reports the anomaly. The reported link anomaly information may include: host identification information, an anomaly code (error code) indicating the type of anomaly, and a timestamp of the anomaly occurrence. Alternatively, the reported link anomaly information may include: port identification information, an anomaly code (error code) indicating the type of anomaly, and a timestamp of the anomaly occurrence. There is a correspondence between ports and electronic devices; for example, one electronic device may correspond to one port.

[0036] In the embodiments of this application, after obtaining the link anomaly information, the link anomaly information can be reported to the upper-layer scheduling module to trigger an alarm, and then the link anomaly information can be provided to the target object to calculate the recovery of the link between the high-speed link memory pool based on the information included in the link anomaly information.

[0037] In the embodiments of this application, after obtaining link anomaly information, the link anomaly information can also be reported to the upper-layer scheduling module to trigger an alarm. Based on the link anomaly information, a target recovery method matching the preset anomaly and recovery method correspondence is searched, and then recovery is performed based on the target recovery method. The preset anomaly and recovery method correspondence is determined based on after-sales issues or an issue knowledge base.

[0038] In the embodiments of this application, if the problem is determined to be non-software based on the link anomaly information, an alarm can be triggered. For example, the alarm information may be: the port connection is loose, etc., so that the target object can restore the link between the high-speed link memory pool and the target object based on the alarm information.

[0039] In this way, the link between the high-speed link memory pool and the link anomaly information can be restored in a timely manner, improving the timeliness of link recovery.

[0040] In some embodiments, the data structure of the local memory operation log includes at least one or more of the following: global log sequence number, host identifier, transaction identifier, memory address, data length, operation identifier, data checksum, and data content.

[0041] Exemplary data structures: struct log_record{ uint64_t seq_id; / / Global log sequence number uint64_t host_id; / / Host identifier uint64_t txn_id; / / Transaction identifier uint64_t addr; / / Memory address uint32_t len; / / Data length uint32_t flags; / / Operation flags (PREPARE / COMMIT / ABORT) uint32_t checksum; / / Data checksum uint8_t data[len]; / / Data content } In the embodiments of this application, each operation of the electronic device on the high-speed link memory pool is recorded in the memory operation log in the manner described above, so that the memory data can be recovered later based on the corresponding data.

[0042] The global log sequence number is the sequence number of the electronic device when it is stored in the high-speed memory pool of the computing link. It provides a globally ordered view to represent write operations from different hosts (electronic devices), thereby ensuring the consistency of concurrent write operations across multiple hosts.

[0043] The host identifier is the identification information of an electronic device, which can be the device number of the electronic device or other information that uniquely identifies the device.

[0044] A transaction identifier represents the target application for executing the transaction. For example, the target application could be an application such as Office or a browser.

[0045] The memory address is the memory location corresponding to the storage operation log.

[0046] The data length is the length of the memory address corresponding to each operation in the storage operation log.

[0047] Operation identifiers are the core operation identifiers in transaction processing. For example, PREPARE, COMMIT, and ABORT are used in scenarios such as databases, distributed systems, and message queues.

[0048] Data checksums are fixed-length values ​​generated by performing specific mathematical operations (such as addition, XOR, polynomial division, etc.) on the original data. They are used to verify whether errors or tampering have occurred in the data during transmission, storage, or processing.

[0049] The data content represents the specific operations performed on the high-speed link memory pool.

[0050] In embodiments of this application, the data structure of the local memory operation log may include a transaction identifier, memory address, data length, operation identifier, data checksum, and data content; or, it may include a global log sequence number, transaction identifier, memory address, data length, operation identifier, data checksum, and data content; or it may include a transaction identifier, operation identifier, data checksum, and data content, or other data structures.

[0051] In this way, memory data after the checkpoint can be replayed based on the memory operation log, providing data basis for continuing to execute read and write operations on the high-speed computing link memory pool.

[0052] In some embodiments, when the electronic device performs the step S102 above, "schedules the fast path accessing the high-speed memory pool to the slow path accessing the local memory space," it may also perform the following steps S201 and S202: Step S201: Allocate a memory space in the local memory to obtain the local memory space.

[0053] In the embodiments of this application, if the electronic device detects an anomaly in the link between itself and the high-speed computing link memory pool, it can allocate a memory space in its local memory as a space to store the memory data originally stored in the high-speed computing link memory pool.

[0054] In embodiments of this application, a block of memory space allocated locally by an electronic device can be a contiguous memory space.

[0055] For example, allocating memory space in local memory can be achieved using the following code: void *local_shadow = alloc(size_of_pool).

[0056] For example, the implementation of allocating memory space in local memory can be as follows: under the Windows system, use VirtualAlloc (such as VirtualAlloc(NULL, size, MEM_COMMIT, PAGE_READWRITE)) to allocate readable and writable memory.

[0057] For example, on Linux / Unix systems, the data segment size can be adjusted via brk / sbrk, or anonymous memory pages can be mapped using mmap.

[0058] Step S202: Modify the address mapped to the high-speed link memory pool in the memory page table to the address in the local memory space.

[0059] In the embodiments of this application, the memory page table stores the mapping relationship between virtual addresses and physical addresses. When accessing the high-speed link memory pool, the virtual address corresponds to the address of the high-speed link memory pool. That is, the mapping relationship between the virtual address and the address of the high-speed link memory pool constitutes a fast path for accessing memory data. If it is necessary to switch the fast path for accessing the high-speed link memory pool to the slow path for accessing the local memory space, the implementation method can be: modify the virtual address stored in the memory page table that maps to the physical address of the high-speed link memory pool to the physical address that maps to the local memory space. In this way, the mapping relationship between the virtual address in the memory page table and the address in the local memory space constitutes a slow path for accessing memory data.

[0060] For example, modifying the address mapped to the high-speed link memory pool in the memory page table to an address in the local memory space (so that all accesses will be automatically redirected to access local_shadow) can be implemented using the following code: pte.fast_path = 0; pte.cxl_paddr → local_ram_paddr; In the embodiments of this application, the address mapped from the memory page table to the high-speed link memory pool is modified to the address of the local memory space. In this way, when storing memory data to the high-speed link memory pool based on the memory allocation strategy, the physical address corresponding to the local memory space can be found directly based on the virtual address. The upper-layer application does not need to know about this, and the memory data can be written to the local memory space. That is, for the upper-layer application or the memory allocation strategy, no changes are needed to achieve the conversion from a fast path to a slow path.

[0061] In this way, by changing the mapping of the virtual address in the memory page table from the address of the high-speed link memory pool to the address of the local memory space, the upper layer can achieve seamless path switching.

[0062] In some embodiments, when the electronic device performs the above step S103, "based on the memory operation log, restore the memory data between the most recent checkpoint and the occurrence of the anomaly to the local memory space," as follows: Figure 3 As shown, it may also include the following steps S301 to S304: Step S301: Obtain the checkpoint closest to the current time from the local memory operation log.

[0063] In the embodiments of this application, the electronic device periodically persists the log during the process of generating local memory operation logs, and generates checkpoints during the persistence process.

[0064] For example, the structure of the checkpoint is defined as follows: struct checkpoint { uint64_t seq_id; uint64_t bitmap_valid[...]; uint8_t snapshot[]; } Here, `seq_id` is the sequence ID, a globally unique, incrementing identifier used to sort checkpoint versions; `bitmap_valid` is the valid bitmap, marking which data blocks / pages have been persisted (e.g., 0x01 indicates the first block is valid). An example value 0xFFFFFFFF indicates that the first 32 blocks are all valid; `snapshot` is snapshot data, storing actual state data (e.g., memory pages, file content).

[0065] In embodiments of this application, the electronic device can obtain the nearest checkpoint based on the above definition.

[0066] Step S302: Determine the operation logs after the checkpoint in the local memory operation log as the target operation log.

[0067] In the embodiments of this application, the local memory operation log records each step of computing the high-speed link memory pool. After obtaining the checkpoint, the operation log after the checkpoint can be determined as the target operation log.

[0068] In the embodiments of this application, the target operation log is the memory data of the high-speed computing link memory pool that needs to be restored to the local memory space.

[0069] For example, the scope of the target operation log can be the operation records between the checkpoint sequence identifier and the last log identifier.

[0070] Step S303: Execute the operations recorded in the target operation log to restore the high-speed link memory data after the checkpoint.

[0071] In the embodiments of this application, each operation recorded in the target operation log is recalculated to obtain the high-speed link memory data after the checkpoint.

[0072] For example, the code for memory operation log recovery could be: for seq from last_checkpoint_seq_id to last_log_seq_id: apply(log_record[seq],local_shadow) This allows for the recovery of operations corresponding to each log from the checkpoint sequence identifier to the last log identifier.

[0073] Step S304: Calculate the high-speed link memory data and store it in the local memory space.

[0074] In the embodiments of this application, the high-speed link memory data recovered based on the target operation log is stored in the local memory space, as indicated in the code in step S303, where the recovered data is replayed in the local memory space (local_shadow).

[0075] An exemplary implementation of replaying memory data is as follows: read the latest checkpoint, load seq_id and bitmap_valid; replay the operation logs after the checkpoint to reconstruct the system state. The validity of data blocks is verified using bitmap_valid to avoid redundant recovery.

[0076] In this way, the data after the checkpoint is restored to the local memory space, so that read and write operations can continue to be performed based on the data restored in the local memory space, avoiding the interruption caused by the disconnection from the high-speed computing link memory pool.

[0077] In some embodiments, such as Figure 4 As shown, the electronic device can also perform the following steps S401 to S403: Step S401: Detecting that the link between the high-speed link memory pool and the computing link has returned to normal, schedule the slow path to the fast path.

[0078] In the embodiments of this application, if it is detected that the link between the computing high-speed link memory pool has returned to normal, the slow path can be scheduled to the fast path.

[0079] In the embodiments of this application, the electronic device determines the link status between the electronic device and the high-speed computing link memory pool by detecting the link layer status between the electronic device and the CXL switch port.

[0080] For example, if the LTSSM register status of the CXL switch physical port read by the electronic device indicates that the link is maintained in an active state (L0) or a low-power state (L0s), then the link status is determined to be normal. In this way, it can be determined that the link between the electronic device and the computing high-speed link memory pool has been restored to normal, and the slow path can be scheduled to the fast path for access.

[0081] For example, switching from a slow path that accesses the high-speed memory pool to a fast path that accesses the local memory space can be achieved by enabling Remote Direct Memory Access (RDMA) support in the distributed framework.

[0082] For example, enable NVLink bridging in the Basic Input / Output System (BIOS) or Graphics Processing Unit (GPU) driver settings.

[0083] Step S402: Call the interface function to synchronize the data stored in the local memory space to the high-speed computing link memory pool.

[0084] In the embodiments of this application, after the electronic device detects that the link between it and the high-speed computing link memory pool has been restored to normal, it calls an interface function to synchronize the data stored in the local memory space to the high-speed computing link memory pool.

[0085] For example, the CXL.mem protocol is used to directly access memory through load / store instructions, combined with hardware atomic operations (such as atomicAdd) to achieve low-latency updates; the CXL.cache protocol is used to ensure cache consistency across multiple devices and avoid software polling overhead; memory interleaving or NUMA binding is used to optimize batch transmission bandwidth.

[0086] Step S403: Based on the fast path, continue to perform access operations on the high-speed link memory pool.

[0087] In the embodiments of this application, after the electronic device switches from a slow path to a fast path, it continues to perform access operations on the high-speed link memory pool based on the fast path.

[0088] This ensures uninterrupted access even if the link between the electronic device and the high-speed computing memory pool fails, thus improving access continuity.

[0089] In some embodiments, when performing step S401 above, the electronic device may also perform the following step: modify the address mapped to the local memory space in the memory page table to the address of the high-speed link memory pool.

[0090] In the embodiments of this application, the memory page table stores the mapping relationship between virtual addresses and physical addresses. When accessing local memory space, the mapping relationship between virtual addresses and local memory space addresses constitutes a slow path for accessing memory data. If it is necessary to switch the slow path for accessing local memory space to a fast path for accessing the high-speed memory pool, the implementation method can be: modify the virtual addresses stored in the memory page table that are mapped to physical addresses in local memory space to physical addresses mapped to the high-speed memory pool. In this way, the mapping relationship between virtual addresses in the memory page table and addresses in the high-speed memory pool constitutes a fast path for accessing memory data.

[0091] For example, modifying the addresses mapped to local memory space in the memory page table to addresses of the compute high-speed linked memory pool (so that all accesses will be automatically redirected to access the compute high-speed linked memory pool) can be implemented using the following code: pte.fast_path = 1; pte.local_ram_paddr →cxl_paddr; In the embodiments of this application, the address mapped from the memory page table to the local memory space is modified to the address of the high-speed computing link memory pool. In this way, when storing memory data to the high-speed computing link memory pool based on the memory allocation strategy, the physical address corresponding to the high-speed computing link memory pool can be found directly based on the virtual address. The memory data can be written back to the high-speed computing link memory pool without the need for the upper-layer application to know. That is, for the upper-layer application or the memory allocation strategy, no changes are needed to realize the transformation from slow path to fast path.

[0092] In this way, by changing the mapping of the virtual address in the memory page table from the address in the local memory space to the address in the high-speed link memory pool, the upper layer can achieve seamless path switching.

[0093] In some embodiments, such as Figure 5 As shown, the electronic device can also perform the following steps S501 and S502: Step S501: Based on the operation performed on the high-speed link memory pool, trigger log events and record each operation to obtain local memory operation logs.

[0094] In the embodiments of this application, in the CXL shared memory scenario, the logging mechanism of this module is not a traditional database log, but a "consistency guarantee mechanism of 'first accounting, then disk writing' for memory write operations". When the electronic device performs operations on the computing high-speed link memory pool, it will trigger log events to record each operation performed on the computing high-speed link memory pool, thereby obtaining local memory operation logs.

[0095] In the embodiments of this application, the local memory operation log is used to implement write loss protection. When the CXL memory link fails, the uncommitted memory data can be fully recovered through the log.

[0096] Step S502: Periodically write the local memory operation log to the local disk and then set the transaction commit flag.

[0097] In the embodiments of this application, the local memory operation log is periodically written to the disk. The writing of the log is asynchronous with the storage path of the memory data of the high-speed link memory pool, and does not block input / output I / O.

[0098] For example, the read / write process is as follows: Host application → CXL memory (load / store) → Log Manager append log_record → Log commit flag. Log writing is performed asynchronously and does not interfere with normal I / O.

[0099] In the embodiments of this application, storing local memory operation logs to local disks periodically can effectively release log resources. Furthermore, during the recovery process, after a checkpoint, the logs of committed transactions can be truncated or archived (such as PostgreSQL's WAL archiving), reducing log volume and supporting "point-in-time recovery," which means that the point at which data is written to disk is the checkpoint.

[0100] This enables data persistence, frees up log resources, and reduces log backlog.

[0101] In the embodiments of this application, if the link between the electronic device and the high-speed computing link memory pool is normal, the fast path for accessing the high-speed computing link memory pool is used as the normal default data transmission path, which is suitable for most normal memory access scenarios. This path allows the electronic device to directly access CXL memory without triggering global coordination operations. The core objective is to achieve the lowest latency and the highest throughput, ensuring the efficient operation of business applications.

[0102] For example, the normal operation process of the link between the electronic device and the high-speed computing memory pool is as follows: Figure 6As shown, steps S601 to S604 are included: Step S601: Quick state ready.

[0103] Here, a fast state-ready approach could be for the electronic device to map the page frame number (PFN) of the CXL memory to the user virtual address space. For example, the page table entry format is: struct pte_cxl { uint64_t cxl_paddr : 52; uint8_t rw : 1; uint8_t valid: 1; uint8_t fast_path : 1; / / Fast-path flag uint8_t reserved : 9; }; In this way, the virtual addresses in the memory page table are mapped to CXL memory, enabling electronic devices to perform read and write operations on CXL memory.

[0104] Step S602: Quick path activation.

[0105] Here, after mapping the virtual address in the memory page table to the CXL memory, the electronic device can perform read and write operations on the CXL memory.

[0106] Step S603: CXL memory loading / storage, and CXL memory log recording.

[0107] Here, electronic devices initiate read / write operations directly through PCIe / CXL.mem, without any exception scheduling or logging of memory read / write operations. CXL memory loading / storage and CXL memory logging are performed asynchronously, without interfering with normal I / O.

[0108] Step S604: Suspend the fast path.

[0109] Here, if an error is detected in the link to the high-speed memory pool, the fast path can be suspended and switched to the slow path. The triggering conditions and explanations for the Fast-Path error switching are shown in Table 1. Table 1 condition illustrate LTSSM state enters Detect / Polling / Disabled This indicates a link interruption or physical link failure. SerDes LOS Loss of signal but physical link is normal, data delay Recovery timeout Switch recovery failed, but the physical link is normal; no data is being received. If the above penalty conditions are met, the fast path will be suspended and the system will switch to the slow path.

[0110] The slow path serves as a protection and recovery path in case of link failures. It automatically triggers a switchover when a CXL memory link failure or an LTSSM error is detected. This path first suspends normal memory or serialization access operations, while simultaneously allocating a new local memory block on the host side. Data is then recovered from the CXL memory operation log to this new memory area, and the addresses mapped to CXL memory in the page tables are modified to map to the new memory addresses, thereby ensuring data consistency and recoverability. Its core objective is to ensure the correctness of upper-layer application reads and writes to CXL memory and the validity of memory addresses in link failure scenarios, allowing for a certain degree of latency to support complex recovery processes.

[0111] For example, the workflow when the link between the electronic device and the high-speed computing memory pool fails is as follows: Figure 7 As shown, steps S701 to S704 are included: Step S701: Slow path initialization.

[0112] Here, following step S604 above, the electronic device switches the fast path for accessing the high-speed memory pool to the slow path for accessing the local memory space, and initializes the slow path.

[0113] Step S702: Slow path recovery.

[0114] Here, recovery begins from the checkpoint, and the log to be recovered is read from the memory operation log.

[0115] Step S703: Slow path activation.

[0116] Here, after restoring the memory data to the local memory space based on the memory operation log, the slow path is activated.

[0117] Step S704: Load / store in local memory.

[0118] Here, data is loaded and stored based on local memory space, that is, the business process reads and writes to local memory. At this time, the host runs stably in local memory, and the memory operation log continues to be recorded; the reading is fully synchronized, waiting for the link to recover.

[0119] Step S705: Synchronize the status of the slow path.

[0120] Here, if the link between the local memory space and the high-speed memory pool is detected to have returned to normal, the data is copied to the high-speed memory pool and then switched to the fast path.

[0121] In this way, when the link between the high-speed computing link and the memory pool fails, the business process can be switched to the local memory space to continue running, avoiding interruption and ensuring high availability.

[0122] like Figure 8 The diagram illustrates an exemplary connection between an electronic device and a high-speed computing link memory pool. Figure 8 As shown, electronic devices 81 and 82 are connected to CXL switch 84 port via CXL cable 83. CXL switch 84 port is connected to CXL memory pool 85 (including memory array).

[0123] In every electronic device, the core module that executes memory exception handling methods, such as Figure 9 As shown, electronic device 81 includes core modules such as link anomaly detection module 91, anomaly scheduling module 92, link anomaly recovery (not shown in the figure), memory operation log recording (not shown in the figure), checkpointing (not shown in the figure), and fast-path / slow-path switching module (not shown in the figure), constructing a comprehensive collaborative recovery system to fully ensure the high availability and security of CXL memory pooling. The operating system involves application layer 93 (including APP931, memory allocator 932, and anomaly scheduling module 92), kernel layer 94 (including link anomaly detection module 91, and pages 9411 and 9412 in memory page table 941), and hardware layer 95 (including local memory 951), as well as CXL memory pool 85.

[0124] like Figure 10 This demonstrates the implementation flow of a memory exception handling method, including the following steps S1001 to S1010: This combination Figure 9 To elaborate: Step S1001, Quick Path: CXL Memory Load / Storage.

[0125] Here, electronic device 81 performs allocation, read and write operations on CXL memory 85 through fast-path; at the same time, each operation on CXL memory 85 is recorded in real time in the memory operation log, which will serve as the basis for data recovery in case of link failure.

[0126] Step S1002, Link error.

[0127] Here, electronic device 81 detects an error in the link with the high-speed link memory pool through link anomaly detection module 91.

[0128] Step S1003: Report link anomalies.

[0129] Here, after detecting an anomaly, the electronic device 81 reports to the anomaly scheduling module 92. For example, when the link anomaly detection module 91 reads that the LTSSM register status of the CXL port is abnormal (Detect, Polling, or Disabled), or detects a specified hardware error, it immediately reports the anomaly information to the upper-level anomaly scheduling module 92.

[0130] Step S1004: Replay memory operation log.

[0131] Here, after receiving an exception report, the exception scheduling module 92 creates a new memory region in the Host's local RAM, replays the CXL memory operation log into the new memory region, and completes the data recovery.

[0132] Step S1005: Switch to the slow path.

[0133] Here, the exception scheduling module 92 calls the kernel's fast-path / slow-path switching module. Subsequent read and write operations of the upper-layer business application on CXL memory 85 will be automatically switched to the local memory 951 (local RAM) corresponding to the slow-path, ensuring continuous operation of the business.

[0134] Step S1006, Slow path: Local memory loading / storage.

[0135] Here, electronic device 81 directly initiates a read (load) / write (store) operation to local memory 951. Step S1007: Report link recovery.

[0136] Here, CXL memory pool 85 reports link recovery to electronic devices (81 / 82). MSG_LINK_UP reports link recovery. Step S1008: Report link recovery.

[0137] Here, electronic device 81 reports link recovery to abnormal scheduling module 92.

[0138] Step S1009: Copy local memory to CXL memory pool.

[0139] Here, when the CXL memory pooling link returns to normal, the abnormal scheduling module 92 calls the interface function of the fast-path / slow-path module to synchronously copy the data in the local RAM 951 to the CXL memory 85.

[0140] Step S1010: Switch to the fast path.

[0141] Here, after data synchronization is complete, the slow-path is switched back to the fast-path, and the upper-layer business application's read and write operations on memory are transferred back to CXL memory, restoring normal operation.

[0142] By introducing a fast-path / slow-path dynamic switching mechanism in CXL memory pooling scenarios, combined with memory operation logs and checkpoint consistency recovery technology, this solution achieves lossless data recovery in case of link anomalies, uninterrupted host services, enhanced cross-host memory isolation, and system-level high availability. This solution overcomes the limitation of existing PCIe / CXL architectures lacking cross-host consistency recovery mechanisms and is suitable for environments with extremely high memory reliability requirements, such as data centers, AI training, and multi-host scenarios.

[0143] This application provides a method for handling memory anomalies. The method detects an anomaly in the link between the high-speed computing link memory pool and obtains link anomaly information. Based on the link anomaly information, it schedules the fast path accessing the high-speed computing link memory pool to a slow path accessing the local memory space. It obtains the memory operation log of the high-speed computing link memory pool and, based on the memory operation log, restores the memory data between the most recent checkpoint and the anomaly to the local memory space. The memory state before the checkpoint is persisted. Based on the slow path and the memory data, it continues to perform read and write operations on the local memory space. The memory anomaly handling method provided by this application, after an anomaly occurs in the link between the high-speed computing link memory pool and the high-speed computing link memory pool, replays the memory data after the checkpoint to the local memory space based on the memory operation log and performs read and write operations on the local memory space to continue the operations performed when the link anomaly occurred. This enables lossless data recovery, uninterrupted host services, and system-level high availability in the event of a link anomaly.

[0144] like Figure 11 As shown, this application embodiment provides an electronic device 81, including: local memory 951 and processor 111; Processor 111 is used to detect an anomaly in the link between the high-speed computing link memory pool and obtain link anomaly information; based on the link anomaly information, schedule the fast path to access the high-speed computing link memory pool to the slow path to access the local memory space in local memory 951; obtain the memory operation log of the high-speed computing link memory pool; based on the memory operation log, restore the memory data between the most recent checkpoint and the anomaly to the local memory space; the memory state before the checkpoint has been persisted; based on the slow path and memory data, continue to perform read and write operations on the local memory space.

[0145] In one embodiment of this application, the anomaly includes at least the read status anomaly of the computing high-speed link port, or a hardware error; the status anomaly includes at least no signal detected, negotiation failure, or link disabled; the hardware error includes at least the cumulative check error exceeding the limit, signal loss, or link reset timeout.

[0146] In one embodiment of this application, the link anomaly information includes at least one or more of the following: host identification information, physical port identification information, anomaly code representing the anomaly type, and a timestamp of the anomaly occurrence.

[0147] In one embodiment of this application, the data structure of the local memory operation log includes at least one or more of the following: global log sequence number, host identifier, transaction identifier, memory address, data length, operation identifier, data checksum, and data content.

[0148] In one embodiment of this application, the processor 111 is further configured to allocate a memory space in local memory 951 to obtain local memory space; and modify the address mapped to the high-speed link memory pool in the memory page table to the address of the local memory space.

[0149] In one embodiment of this application, the processor 111 is further configured to obtain the checkpoint closest to the current time from the local memory operation log; determine the operation log after the checkpoint in the local memory operation log as the target operation log; execute the operation content recorded in the target operation log to restore the computational high-speed link memory data after the checkpoint; and store the computational high-speed link memory data into the local memory space.

[0150] In one embodiment of this application, the processor 111 is further configured to detect that the link between the processor and the high-speed memory pool has returned to normal, schedule the slow path to the fast path; call an interface function to synchronize the data stored in the local memory space to the high-speed memory pool; and continue to perform access operations on the high-speed memory pool based on the fast path.

[0151] In one embodiment of this application, the processor 111 is further configured to modify the address mapped to the local memory space in the memory page table to the address of the high-speed link memory pool.

[0152] In one embodiment of this application, the processor 111 is further configured to trigger a log event based on the operation performed on the high-speed link memory pool, record each operation step to obtain a local memory operation log, and periodically write the local memory operation log to the local disk and then set a transaction commit flag.

[0153] This application provides an electronic device that detects an anomaly in the link between itself and a high-speed computing link memory pool, and obtains link anomaly information. Based on the link anomaly information, it schedules a fast path accessing the high-speed computing link memory pool to a slow path accessing the local memory space. It obtains the memory operation log of the high-speed computing link memory pool, and based on the memory operation log, restores the memory data between the most recent checkpoint and the anomaly to the local memory space. The memory state before the checkpoint is persisted. Based on the slow path and the memory data, it continues to perform read and write operations on the local memory space. The electronic device provided in this application, after an anomaly occurs in the link with the high-speed computing link memory pool, replays the memory data after the checkpoint to the local memory space based on the memory operation log, and performs read and write operations on the local memory space to continue the operations performed when the link anomaly occurred. This enables lossless data recovery, uninterrupted host services, and system-level high availability in the event of a link anomaly.

[0154] This application provides a computer-readable storage medium storing one or more computer programs, which can be executed by one or more processors to implement the aforementioned method for locating memory exceptions. The computer-readable storage medium can be transient or non-transient.

[0155] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described memory exception handling method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0156] In some embodiments, the storage medium may be a computer-readable storage medium, which may be volatile memory, such as random-access memory (RAM); or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), ferromagnetic random access memory (FRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disk, or compact disk-read-only memory (CD-ROM); or it may be various devices that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0157] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0158] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0159] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0160] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0161] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0162] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file containing other programs or data, for example, in one or more scripts within a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple co-located files (e.g., files storing one or more modules, subroutines, or code sections). As an example, executable instructions may be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0163] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0164] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not performed.

[0165] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for handling memory exceptions, the method comprising: An anomaly was detected in the link between the high-speed computing link memory pool, and link anomaly information was obtained. Based on the link anomaly information, the fast path accessing the high-speed computing link memory pool is scheduled to the slow path accessing the local memory space. Obtain the memory operation log of the high-speed link memory pool, and based on the memory operation log, restore the memory data between the most recent checkpoint and the occurrence of the anomaly to the local memory space; The memory state prior to the checkpoint has been persisted; Based on the slow path and the memory data, read and write operations continue to be performed on the local memory space.

2. The memory anomaly handling method according to claim 1, wherein the anomaly includes at least an anomaly in the read state of the high-speed computing link port, or a hardware error; the anomaly includes at least no signal detected, negotiation failure, or link disabled; and the hardware error includes at least an excess of checksum errors, signal loss, or link reset timeout.

3. The memory anomaly handling method according to claim 1, wherein the link anomaly information includes at least one or more of the following: host identification information, physical port identification information, anomaly code representing the anomaly type, and a timestamp of the anomaly occurrence.

4. The memory exception handling method according to claim 1, wherein the data structure of the local memory operation log includes at least one or more of the following: global log sequence number, host identifier, transaction identifier, memory address, data length, operation identifier, data checksum, and data content.

5. The method for handling memory anomalies according to claim 1, wherein scheduling the fast path accessing the high-speed memory pool to the slow path accessing the local memory space includes: Allocate a memory space in the local memory to obtain the local memory space; The address mapped to the high-speed link memory pool in the memory page table is modified to the address in the local memory space.

6. The method for handling memory anomalies according to claim 1, wherein restoring the memory data between the most recent checkpoint and the occurrence of the anomaly to the local memory space based on the memory operation log includes: Obtain the checkpoint closest to the current time from the local memory operation log; The operation logs after the checkpoint in the local memory operation log are identified as the target operation logs. Execute the operations recorded in the target operation log to restore the high-speed link memory data after the checkpoint; The calculated high-speed link memory data is stored in the local memory space.

7. The method for handling memory exceptions according to any one of claims 1 to 6, the method further comprising: If the link between the high-speed computing link memory pool and the network is detected to have returned to normal, the slow path is rescheduled to the fast path. Call the interface function to synchronize the data stored in the local memory space to the high-speed computing link memory pool; Based on the fast path, access operations continue to be performed on the high-speed computing link memory pool.

8. The method for handling memory exceptions according to claim 7, wherein scheduling the slow path to the fast path comprises: The address mapped to the local memory space in the memory page table is modified to the address of the high-speed computing link memory pool.

9. The method for handling memory exceptions according to any one of claims 1 to 6, the method further comprising: Based on the operation triggered by the computation high-speed link memory pool, each operation is recorded to obtain the local memory operation log; Periodically write the local memory operation log to the local disk and then set the transaction commit flag.

10. An electronic device, comprising: Local memory and processor; The processor is used to detect an anomaly in the link between the high-speed computing link memory pool and to obtain link anomaly information. Based on the link anomaly information, the fast path that accesses the high-speed computing link memory pool is scheduled to the slow path that accesses the local memory space in the local memory. Obtain the memory operation log of the high-speed link memory pool, and based on the memory operation log, restore the memory data between the most recent checkpoint and the occurrence of the anomaly to the local memory space; The memory state prior to the checkpoint has been persisted; Based on the slow path and the memory data, read and write operations continue to be performed on the local memory space.

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