480results about "Faulty hardware testing methods" patented technology

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

A method for processing faulty memory module and apparatus, and an electronic device and a non-transitory readable storage medium are provided. The method for processing faulty memory module includes: acquiring a first power-down command, the first power-down command being used for instructing a baseboard management controller of a memory resource pool to perform power-down processing on a faulty memory module in the memory resource pool; and in response to the first power-down command, when a first memory module in the memory resource pool is in a fault state and is allowed to be powered down, sending a second power-down command to a target memory expander controller to which the first memory module belongs, the second power-down command being used for instructing the target memory expander controller to perform power-down processing on the first memory module.

The invention discloses a system and method for improving data configuration efficiency of a test machine, and relates to the technical field of board card testing, the system comprises an FPGA PCIE module, a DMA address data analysis module and a data transmission module, a general data frame is divided into an independent 32b address field and an independent 32b data field through the arranged DMA address data analysis module, then bit [31] and 0 of an 32b address are analyzed to represent write operation, and the data transmission module is connected with the FPGA PCIE module. 1 represents read operation, an identifier is independently extracted and embedded into a subsequent instruction packet, then a bit [27: 0] of a 32b address is extracted, a target daughter card number is determined according to a preset address mapping table, and data is packaged after determination, so that data distribution of different address fields is realized, the data transmission module receives the data and then sends the data to each post-stage daughter card module in parallel, and data read-write is realized. Therefore, the read-write speed of the test machine is greatly increased, and the read-write efficiency is further improved.

The invention provides a memory channel detection circuit, device and method and a storage medium. The memory channel detection circuit comprises an interface, a signal acquisition module, a power supply module and a control module, the input end of the signal acquisition module is connected with the interface and the output end is connected with the control module; the power supply module is connected with the power end of the signal acquisition module and the power supply end of the control module and used for providing power voltage. Each memory channel is connected in series with a preset resistor; the interface is used for accessing a CPU or a memory bank; the signal acquisition module responds to a test instruction output by the control module, acquires partial voltage values corresponding to a plurality of memory channels, and outputs the partial voltage values to the control module; and the control module is used for determining whether the plurality of memory channels have faults or not according to the divided voltage values corresponding to the plurality of memory channels. According to the method, whether each memory channel is abnormal or not is judged by acquiring the partial voltage values corresponding to the plurality of memory channels, so that a large amount of time consumed by a traditional solution is saved.

The present application relates to the technical field of peripheral component interconnect express (PCIe) devices, and discloses a PCIe device detection system, method and apparatus, and a product. The PCIe device detection system at least includes a complex programmable logic device (CPLD), where the CPLD includes a control unit, configured to obtain presence information transmitted by a PCIe device during a detection cycle, the presence information including presence signals of all presence detection pins on the PCIe device; a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the PCIe device based on the presence signals; and a determination unit, configured to determine whether the PCIe device tilts according to a preset bandwidth and the actual bandwidth.

The invention relates to the technical field of data storage, and discloses a solid state disk compatibility and reliability testing method which comprises the steps of initializing a testing environment, installing an operating system, compiling and executing a testing script and configuring a compiling environment. Basic information of the solid state disk is recognized and classified, an automatic script is written, the classified basic information of the solid state disk is created into file clusters of different sizes according to the automatic script, continuous / random reading and writing are conducted, and file integrity is verified; and performing performance test on the classified basic information of the solid state disk by using a Fio tool and recording performance indexes of the solid state disk, wherein the performance indexes comprise sequential read-write speed, random IOPS and response delay, compiling an automatic script, and simulating a database load to perform small block random read-write operation. According to the invention, a plurality of modules for basic function and compatibility test, performance test, power management and reliability test, safety characteristic test and the like are integrated into a complete and automatic test scheme.

The invention discloses a PCBA aging test method and system, and belongs to the technical field of aging test. The method specifically comprises the following steps: S1, historical data acquisition: acquiring PCBA aging related historical data, including but not limited to voltage parameters, current parameters, core area temperature, operation duration, environment humidity, fault types and fault occurrence time during PCBA operation; s2, preprocessing the historical data: preprocessing the historical data, including removing abnormal values, filling missing values and normalizing; 24-72-hour long-time power-on loading of a traditional aging test is not needed, the test period of a single PCBA is shortened to the minute level, the production takt is greatly improved, the large-scale batch production requirement is met, and aging fault recognition is more comprehensive; and recessive aging precursors such as capacitance attenuation and welding spot microcracks can be captured, and the sudden failure risk after the product leaves the factory is reduced.

An AI decision based multiple telecommunication endpoints system is provided, including a telecommunication endpoint device and an artificial intelligence decision controller. The telecommunication endpoint device performs a communication test with the radio frequency communication device under test. The artificial intelligence decision controller is electrically connected to the telecommunication terminal device to control the communication test, and performs an efficiency analysis on the result of the communication test, and generates a decision instruction according to the result of the efficiency analysis. The artificial intelligence decision controller can centrally control, replace and analyze multiple artificial intelligence modules and generate a large number of telecommunication endpoints device signal sending and receiving behaviors, providing a telecommunication endpoints system with self-adaptive adjustment process, parameters, result analysis and reasonable cost as a test for the development phase, deployment phase, or maintenance phase of the telecommunications equipment product development process.

The invention provides a multifunctional channel detection system based on a Zynq chip. The multifunctional channel detection system is characterized in that a system main control module is deployed at an ARM processor end of the Zynq chip; the protocol analysis control module, the fault-tolerant detection excitation module and the bottom hardware adaptation module are deployed at the FPGA programmable logic end of the Zynq chip; the system main control module communicates with each module of the FPGA programmable logic end through an AXI bus; the underlying hardware adaptation module receives the configuration from the system main control module and completes electrical adaptation and dynamic switching of various bus interfaces; the protocol analysis control module receives an instruction from the system main control module, and performs protocol analysis and feature verification on at least one of an SPI bus, an IIC bus and a 1553B bus; the fault-tolerant detection excitation module receives the trigger from the system main control module and injects a controllable fault into the tested bus interface; and the system master control module integrates the verification result and the injection feedback to complete the performance and reliability evaluation of the bus channel.

The invention relates to an SPD hub chip testing method and device, equipment and a storage medium. The method comprises the steps that if it is determined that a to-be-tested SPD hub chip is placed in a replaceable limiting frame of a test seat and communication connection is established with an upper computer, target environment parameters are set, the to-be-tested SPD hub chip is initialized, the upper computer is in communication connection with the test seat, preset test data are written into an EEPROM of the SPD hub chip based on the target environment parameters, then read-back comparison is carried out, and the to-be-tested SPD hub chip is initialized; the static verification data is used for judging the static storage reliability of the to-be-tested SPD hub chip in the current environment, executing continuous read-write operation on the to-be-tested SPD hub chip to obtain a dynamic pressure test data set, and generating a test result of the to-be-tested SPD hub chip based on the static verification data and the dynamic pressure test data set.

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

The invention relates to the technical field of NVMe storage, in particular to an NVMe Verify robustness and data consistency testing method and system fused with multi-dimensional verification and a medium. A real and diversified storage environment is simulated through configuration of test parameters covering different protection types, error injection, power-on and power-off and the like, and meanwhile, a verify test result is read by using PCIe (Peripheral Component Interconnect Express). According to the method, all-around verification is carried out on the NVMe verify through a plurality of different testing, verification indexes and analysis means. By comprehensively considering the verification information from different dimensions and performing mutual verification and deep analysis, whether the data consistency of the NVMe verify in various application scenes is reliable or not can be more accurately judged. The test accuracy is improved, and whether the function can stably and continuously guarantee data consistency and reliable operation in a long-time, high-load and multi-interference scene or not can be truly and reliably verified.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

The invention discloses an STDF file offline generation method and system suitable for various ATEs. The method comprises the steps that the composition sequence of STDF files is determined; acquiring a configuration file, wherein the configuration file comprises batch information, wafer information, test site configuration information, pin configuration information, hardware Bin definition and software Bin definition; analyzing ATE native test data, and obtaining a chip test start mark, multiple types of test item results and a chip test result; checking whether the first test site information is consistent with the second test site information or not, and checking whether hardware Bin information and software Bin information in a chip test result accord with a hardware Bin definition and a software Bin definition in a configuration file or not; and when all the verification results pass, generating an STDF file according to a composition sequence based on the configuration file, the chip test start mark, the test item result and the chip test result. The test efficiency can be improved, and the supply chain cost can be reduced.

The invention discloses a semiconductor chip test information automatic analysis system and method, and relates to the technical field of information analysis, and the method comprises the steps: calculating a parameter reference value according to a standardized test data set, carrying out the multi-dimensional discrimination feature extraction based on the parameter reference value, generating a test feature vector, and carrying out the analysis of the test feature vector; injecting the test feature vectors into the parameter influence network model, analyzing a dynamic interaction relationship among test parameters through an anomaly propagation simulation algorithm, performing root cause sorting and influence path tracking based on the dynamic interaction relationship, generating an anomaly analysis report, calling an intelligent diagnosis mechanism according to the anomaly analysis report, and performing fault diagnosis on the test parameters according to the intelligent diagnosis mechanism. Generating a structured conclusion through historical case library matching, and synchronously activating a visualization function to perform interactive presentation on the structured conclusion; according to the method, comprehensive representation of multi-dimensional discrimination information is realized through multi-dimensional feature extraction, the defect that an existing method is limited to single-parameter statistics is overcome, and the test feature vector expression capability is improved.

The invention provides a multi-dimensional hierarchical verification test method, equipment and device, and the device comprises a business layer which generates a business-level instruction, transmits the business-level instruction to a channel layer, and receives first response information returned by the channel layer; the channel layer generates a channel-level instruction, sends the channel-level instruction to the driving adaptation layer, and generates first response information based on the service-level instruction and second response information returned by the driving adaptation layer; the driving adaptation layer is used for generating an interface-level instruction, sending the interface-level instruction to the driving layer, and generating second response information based on the channel-level instruction and third response information returned by the driving layer; the driving layer is used for driving the interface-level instruction to the to-be-tested equipment and receiving third response information returned by the to-be-tested equipment; wherein the first response information, the second response information and the third response information are used for determining a test result of the to-be-tested equipment. The verification work of the to-be-tested device with complex interaction is layered and simplified, and the flexibility and expansibility of the device are improved.

The invention discloses an SSD (Solid State Disk) back-end anomaly detection method and system. The method comprises the following steps: after a master control core releases reset of a rear-end core, starting a timer and monitoring a state flag, and synchronously monitoring a progress flag sequence written by the rear-end core; based on the sequence analysis execution time consumption, calculating the time consumption increase proportion of continuous steps to judge the health degree; triggering a predictive boot flow when a plurality of consecutive proportions exceed a threshold; the master core then executes an exception handling program to degrade the identified exceptional channels and chip enable units, including switching to a low speed mode, limiting write operations, and updating system resource mapping. According to the method, conversion from passive timeout to active prediction is realized, hardware exceptions can be found and isolated in an early stage, and the storage capacity is reserved to the maximum extent while the availability of the system is guaranteed.

The application relates to the technical field of AMD X86 server, and specifically provides a server restart test optimization method, a server restart test optimization system, a terminal and a storage medium, which comprise the following steps: a BMC judges whether a server restart is stuck in a CPU initialization interface based on a potential signal state of a target pin or a communication state with a BIOS; if the server restart is stuck in the CPU initialization interface, the CPU initialization interface is skipped by repeatedly training the target pin or switching a BIOS running state control system. The application can assist in skipping a stuck PSP interface to enter a BIOS system, and the problem of being stuck in the PSP interface in a restart test process is avoided.

Embodiments of the present application provide a mainboard and a debugging method, and relate to the technical field of computing devices, which can effectively reduce the debugging cost and improve the efficiency of fault debugging. The mainboard comprises a BMC and an identification circuit, the BMC is coupled with the identification circuit; the identification circuit is configured to identify the type of a central processing unit (CPU) to be debugged, and send indication information to the BMC; the indication information is used to indicate the type of the CPU to be debugged; the BMC is configured to receive the indication information from the identification circuit, and based on the type of the CPU to be debugged, simulate output of a debugging signal matching the type of the CPU; wherein the debugging signal comprises a first debugging signal sent by the BMC and a second response signal sent by the CPU to be debugged; the second response signal is a response signal output by the CPU to be debugged in response to the first debugging signal; the first debugging signal and the second response signal satisfy the signal characteristics of a debugging tool corresponding to the CPU to be debugged. The embodiments of the present application can be used in the process of CPU fault debugging.

The application discloses a device pressure test method, device, storage medium and program product, relates to the technical field of pressure test, and comprises the following steps: constructing a pressure test strategy of a first system and a second system in a to-be-tested device, and performing corresponding pressure test operations; collecting first test data of the first system and second test data of the second system, and extracting first feature data of the first test data and second feature data of the second test data; generating target features based on the first feature data and the second feature data; generating a diagnosis result based on the target features by using a diagnosis model constructed based on an expert system and a machine learning model, and generating a diagnosis report based on a target report template. The application can collect pressure test data of each operating system, extract features for fusion, perform correlation analysis and automatic diagnosis by using a fusion expert system and a machine learning model, realizes automatic and accurate positioning of a performance bottleneck, and improves diagnosis comprehensiveness and accuracy.

The present disclosure provides a business test data extraction method applied to U shield testing, which can be applied to the fields of big data technology and artificial intelligence technology. The business test data extraction method applied to U shield testing comprises: generating a high-frequency data set and a low-frequency data set corresponding to a plurality of test U shields according to the historical use frequency of each test U shield in the plurality of test U shields corresponding to a business category; updating the high-frequency data extraction rule corresponding to the business category at the current time through the high-frequency data features corresponding to the high-frequency data set and the low-frequency data features corresponding to the low-frequency data set; and extracting the corresponding business test data based on the high-frequency data extraction rule to realize the U shield testing. The present disclosure also provides a business test data extraction device, equipment, storage medium and program product applied to U shield testing.

The invention discloses an automatic computer mainboard aging and port comprehensive test system and method, and the system comprises a front-end test management module which is used for task configuration, real-time monitoring and log display, a background execution service which is operated by a common user authority, receives a front-end instruction and executes a test command, and is operated by a root authority. The permission risk of the test tool is solved by a sub-permission architecture; the front-end program comprises the following steps: a station identification module automatically identifies a test station number; the task configuration and scheduling module records task parameters, time and execution states; the system information acquisition module automatically acquires mainboard and port information; the resource monitoring module collects information in real time, detects resource fluctuation and evaluates performance; the data uploading module uploads a test result; the graphical interface module displays a system state, a task progress and a result in real time; according to the method, a front-end and back-end authority layered framework is adopted, and full-process automation from task configuration, execution, monitoring and result uploading to tracing is achieved.

The invention discloses a signal transmission method, an IJTAG circuit and a chip, and the signal transmission method is applied to the IJTAG circuit: under the condition that a TAP controller receives a transmission instruction, a control signal and a target TDI signal are transmitted to a plurality of first SIB nodes through the TAP controller, and the control signal comprises a first selection signal and a second selection signal; under the condition that the first selection signal indicates the IJTAG circuit to select a plurality of first SIB nodes and the second selection signal indicates the IJTAG circuit to select a broadcast target TDI signal, determining a plurality of target SIB nodes in the plurality of first SIB nodes at least according to a storage value of a first register in the plurality of first SIB nodes, the target SIB nodes being in a broadcast mode; and broadcasting the target TDI signals to the TDRs respectively mounted on the plurality of target SIB nodes through the plurality of target SIB nodes. Therefore, TDI signal broadcasting is realized based on the parallel transmission link of the IJTAG circuit and the broadcasting mode of the DIB node, and the signal transmission efficiency of the IJTAG circuit is improved.

The application discloses a software and / or hardware similarity detection method and device. The software and / or hardware similarity detection method comprises the following steps: preparing the same detection environment for software and / or hardware as a reference target and software and / or hardware as a comparison target; inputting the same at least one group of test excitation to the reference target and the comparison target respectively, triggering the detection environment and obtaining power consumption data; comparing and analyzing the power consumption data corresponding to the reference target and the comparison target, and judging the power consumption data similarity of the reference target and the comparison target, and if the power consumption data similarity of the reference target and the comparison target meets a preset range, it is determined that the reference target and the comparison target are similar. The application judges the software and / or hardware similarity by detecting the power consumption of a gate circuit, and the implementation manner is simple, and the application is not limited by source code and other conditions.

The invention belongs to the technical field of vehicle control, and particularly provides a vehicle-mounted peripheral stability test method, a medium and a vehicle, and the method comprises the steps: obtaining target identification information in a vehicle-mounted system, and positioning a to-be-tested target external device based on the target identification information; starting an automatic loop test for the target external equipment, wherein the automatic loop test comprises alternately executing equipment mounting operation and equipment unloading operation; monitoring the running state of the target external equipment and the resource state of the vehicle-mounted system in real time in the automatic cycle test process; and generating a test log based on the running state and the resource state, and determining a stability evaluation result of the target external equipment according to the test log. Through the technical scheme provided by the invention, the stability testing efficiency of the vehicle-mounted peripheral can be improved.

The embodiment of the invention provides a configuration information processing method and a program product, and relates to the technical field of computers, in the method, weights are allocated to optional values of to-be-verified configuration items of to-be-verified objects based on verification requirements. Generating configuration information based on the weight of the optional value of each to-be-verified configuration item, and verifying the to-be-verified object based on the configuration information; the configuration information comprises a value selected from the selectable values of the to-be-verified configuration items, and the probability that the selectable values are selected is positively correlated with the weights of the selectable values. And increasing the weight of the unselected selectable value of each to-be-verified configuration item. Therefore, the weight is allocated to the selectable value according to the verification demand, and the selectable value is selected based on the weight, so that the selectable value which better meets the verification demand is selected at a higher probability, the generated configuration information is more targeted, and the generation effect of the configuration information can be improved to a certain extent.

The embodiment of the present application discloses a kind of test method and related device of storage chip, it is related to integrated circuit technical field, can test multiple types of storage chip, effectively expand the applicable scope of test object, to greatly reduce test cost.The method comprises: according to the pin type of the preset chip pin in the storage chip to be measured, the data transmission pin of test machine is configured, so that the data transmission pin is adapted to signal transmission with the preset chip pin;Wherein, the pin type includes control class, and the preset chip pin of the control class is used to transmit control class signal;The test machine is used to test the storage chip to be measured.The present application is applicable to the test of storage chip.

The embodiment of the present application provides a method and device for detecting the failure of the on-board hard disk applied to a server. In the embodiment, the identification of the on-board hard disk currently in the server is obtained by reading through the I2C bus of the server, the current on-board hard disk information file (containing the information of each on-board hard disk currently in the server) is obtained by the BIOS of the server, the obtained identification of the on-board hard disk currently in the server is compared with the identification of each on-board hard disk contained in the current on-board hard disk information file, so as to detect whether the on-board hard disk of the server has the failure of missing and / or the failure of device disable. The failure detection mode without relying on the storage card to transmit the out-of-band information can detect the failure of the on-board hard disk without connecting the storage card, so that the failure of the on-board hard disk is detected, and the alarm can be sent in time when the on-board hard disk fails.

The invention provides a firmware testing method, device and equipment for a memory and a medium, and the firmware testing method comprises the following steps: identifying a physical address of a global variable related to a function test in a memory space of the memory according to a preset address mapping table; performing function test on the memory, and detecting the running state of the memory; after the to-be-tested firmware of the memory enters an assertion processing flow due to triggering of the assertion code, sending a parameter reading command to the memory; and receiving a parameter value of a global variable fed back by the memory according to the parameter reading command, and determining fault information in the firmware to be tested according to the parameter value of the global variable. According to the firmware testing method and device for the memory, the equipment and the medium provided by the invention, the technical problem that the parameter value of the global variable is difficult to quickly obtain when a fault occurs is solved.

This invention relates to the field of computer storage technology, specifically to a method, system, device, and storage medium for interval checking with a bus interface. The method includes: initializing an array memory; wherein, after initialization, all values ​​in the array memory are 0; acquiring required data, generating message configuration information based on the required data, and configuring the message based on the message configuration information; reading from the array memory, comparing the message with data read from the array memory, and checking for overlap; further processing the message based on the message configuration information and the comparison result between the message and the data read from the array memory: deleting or adding; and outputting message processing completion information. This invention can determine whether overlap exists in LBAs and, by checking overlapping areas, perform addition and deletion of logical intervals.