1674results about "Faulty hardware testing methods" patented technology

The invention relates to the technical field of hard disk testing and verification, in particular to a multi-thread-based solid state disk reliability automatic testing method and system.The method comprises the steps that firstly, SMART information is deeply analyzed through microsecond-level high-granularity continuous performance monitoring, and multi-thread parallel processing is assisted; according to the method, fine performance fluctuation of the solid state disk under the concurrent load can be quickly captured, a fault mode can be identified, then early warning is realized by utilizing the extracted multi-dimensional features and a machine learning model, and a detailed fault diagnosis report is generated; and through dynamic error correction code strength verification and data integrity verification under pressure, an internal error correction mechanism of the solid state disk is actively detected and optimized. And finally, in combination with prediction reliability modeling, the system can estimate the remaining service life and predict faults, and provides product optimization suggestions for design, manufacturing and firmware optimization of the solid state disk, so that automation, intelligence and full life cycle management of the fault detection reliability of the solid state disk are realized.

The invention discloses a hardware fault real-time detection method and system based on cooperation of a CPU (Central Processing Unit) and a BMC (Baseboard Management Controller), and the method comprises the following steps: respectively collecting high-frequency state data and tendency indexes by establishing a communication mechanism between the CPU and the BMC; the processor uses a CUSUM algorithm to carry out abrupt change analysis on the periodically collected operation state to generate an abrupt change event; and the management controller uses an EWMA algorithm to model the trend data, and extracts abnormal changes. And the system performs fusion analysis on the mutation event and the trend anomaly to form a fusion anomaly vector. The risk assessment module calculates a risk score based on a preset rule, determines a fault level, positions a target component, and outputs a processing strategy. And triggering a response action according to the strategy and recording an execution state. And the fusion data and the response record are input into the adaptive module together for dynamically adjusting CUSUM and EWMA parameters, so that adaptive updating of the algorithm is realized, and finally a fault detection signal is generated.

The invention relates to the technical field of deep learning, in particular to an AI chip test parameter adaptive optimization method based on deep learning, which comprises the following steps: acquiring historical test data of an AI chip, and calculating correlation strength among different failure modes based on the historical test data; identifying a failure coupling matrix according to the edge weight, and converting a preset static detection parameter constraint boundary into a dynamic constraint space changing along with a failure detection state; a multi-level optimization framework is constructed, the upper layer executes failure type correlation analysis and generates constraint propagation information, the middle layer optimizes a parameter cluster based on the constraint propagation information, and the lower layer adjusts a single detection parameter and outputs a parameter optimization result; establishing a neural network mapping model, and obtaining a nonlinear mapping relationship between the detection parameters and the failure types; based on the physical state parameters, the nonlinear mapping relation is adjusted, the dynamic constraint space is updated, parameter optimization is executed again, a parameter optimization result is output, and an optimal test parameter combination is output.

The multi-ECU simulation test method includes: obtaining a pre-developed application applied to a target ECU; inputting the application into a pre-built multi-ECU simulation environment; querying a simulated vehicle-mounted ECU having a unique identifier the same as the target ECU from a plurality of simulated vehicle-mounted ECUs in the multi-ECU simulation environment as a target simulated ECU; and simulating a communication process of the target simulated ECU via a simulated controller area network or a simulated Internet network in the multi-ECU simulation environment, running the application based on the target simulated ECU, and outputting a running result of the application.

The invention discloses a transmission link fault detection method for a multi-stage cascade scene and a program product, and relates to the technical field of fault detection. Acquiring real-time link information of a multi-stage cascade expander in the target equipment and an instruction receiving and transmitting condition of at least one target port; when it is detected that the real-time link information is abnormal, executing a corresponding first link fault detection program to determine a first fault detection result; when it is detected that the instruction receiving and sending condition fails, the failure type of the instruction receiving and sending condition is detected, and the second link fault detection program corresponding to the failure type is executed to determine the second fault detection result, so that the technical problem that whether a transmission link fault or a hard disk fault cannot be detected is solved; the technical effects that the fault device or the fault link or the hard disk fault on the transmitting and receiving instruction transmission path is accurately positioned and alarmed, false alarms on the hard disk are avoided, and the fault positioning efficiency is improved are achieved.

The invention provides a hard disk testing method, a hard disk fault early warning method and a hard disk fault early warning device, which can be applied to the technical field of storage equipment. The hard disk testing method comprises the following steps: processing a to-be-tested hard disk to enable the to-be-tested hard disk to reach a steady state condition; executing an advanced formatting operation on the to-be-tested hard disk reaching the steady state condition to obtain the to-be-tested hard disk after the advanced formatting operation is completed; based on a plurality of preset overwriting proportions, testing operation is executed on the to-be-tested hard disk after the advanced formatting operation is completed, performance testing data are obtained, and the overwriting proportions are proportions of the overwriting area space in the to-be-tested hard disk space after the advanced formatting operation is completed; according to the performance test data corresponding to the multiple preset overwriting proportions, a performance test result is obtained, and the performance test result represents the performance recovery capability of the to-be-tested hard disk after the advanced formatting operation is completed.

The invention discloses an SSD (Solid State Disk) testing method, which relates to the technical field of SSDs, and comprises the following steps: an SSD is connected to testing equipment, and the testing equipment comprises a controller, a data generation module, a data transmission module, a data storage module and a performance monitoring module; specific types of test data are generated through a data generation module, the specific types of test data comprise sequential read-write data, random read-write data and mixed read-write data, the file size of the sequential read-write data is within the range of 1GB-10GB, the operation block size of the random read-write data is within the range of 4KB-64KB, and the file size of the mixed read-write data is within the range of 4KB-64KB. The ratio of sequential read-write to random read-write in the mixed read-write data ranges from 1: 1 to 3: 1, the test data further comprises multiple file formats including but not limited to text files, image files, video files and audio files, and the data size of each file format accounts for 10%-30% of the total test data size; the SSD performance can be accurately evaluated, and the performance evaluation standard is perfected.

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

The invention discloses a memory test method and device based on an AI technology and a medium, and the method comprises the following steps: 1) obtaining structure analysis data and memory type description information of a to-be-tested memory, and generating a test intention vector used for expressing a test target; 2) taking the test intention vector as an input to generate a test excitation sequence; 3) executing the test excitation sequence, and performing multi-cycle test on the storage array to form a multi-modal response feature set; 4) inputting the multi-modal response feature set into a graph neural network, performing fault type identification and causal path reasoning, and generating a fault tag sequence and a reasoning path graph; 5) based on the characteristic difference between the inference path diagram and the test excitation sequence, weight parameter updating of the depth generation model is carried out; and 6) generating a test excitation sequence based on the updated depth generation model to test the memory. The intelligent level and the test coverage rate of the memory test can be effectively improved.

The invention belongs to the technical field of cloud computing and software testing, and particularly discloses an automatic fault injection and recovery testing method based on cloud native, which comprises the following steps: acquiring test basic data of a to-be-tested cloud native system; constructing a fault test execution model according to the test basic data; according to the fault test execution model, executing an automatic fault injection operation; generating an abnormal alarm log according to the system running state after the fault injection operation, and synchronously recording a fault injection operation log; according to the abnormal alarm log, executing automatic fault recovery operation; and generating a fault test report according to the fault injection operation log, the system monitoring data and the recovery operation process log. The invention aims to solve the problems of low automation degree, narrow scene coverage, weak monitoring evaluation and passive recovery in cloud native system fault test in the prior art, and provides a comprehensive, automatic, monitorable and evaluable fault injection and recovery test scheme.

The invention discloses a memory test system and method, a board card and a server. The memory test system comprises an out-of-band management unit and a target chip, the out-of-band management unit sends a pressure test instruction to the target chip through the preset communication interface, the pressure test instruction comprises dynamically adjusted test strength parameters, and the pressure test instruction is generated based on a preset instruction set; the target chip performs calibration verification on the target memory in response to the pressure test instruction; after the calibration verification is passed, a test load is applied to the target memory according to the test strength parameter, and a cyclic pressure test is executed; the target chip collects test data generated in the pressure test process and transmits the test data back to the out-of-band management unit through the preset communication interface, and the out-of-band management unit generates structured test data according to the test data. Compared with the prior art, the situation that normal services are interrupted due to testing in a traditional testing method can be avoided, and the availability and stability of the system in the testing process are guaranteed.

The invention relates to the technical field of data processing, and provides a dynamic load test method and device for a chiplet, and the method comprises the steps: collecting transient heat flux data generated by the chiplet in a multi-frequency load switching process to generate a thermal dynamic behavior map, calculating a thermal coupling interference index map according to the thermal dynamic behavior map, and carrying out the testing of the dynamic load of the chiplet according to the thermal coupling interference index map. And inputting the thermal coupling interference index diagram into a preset thermal stability mapping matrix, and generating a small chip dynamic load behavior evaluation parameter group. By inputting the transient heat flux data into the preset thermal stability mapping matrix to generate the small chip dynamic load behavior evaluation parameter group, the thermal stability and the overall performance of the small chip are improved, and the problem that in practical application, the prior art depends on single thermal monitoring data, and thus the reliability of the small chip is improved is solved. And when the load switching frequency is relatively high or the load disturbance is relatively large, the potential thermal coupling interference and the influence of the potential thermal coupling interference on the system performance cannot be accurately identified.

The invention discloses a chip prototype verification method and device, a medium and a product, and relates to the technical field of integrated circuit verification, and the method comprises the steps: dynamically dividing a central processing unit core of a multi-core chip into a first core group and a second core group in a chip prototype verification platform; performing data interaction on the first core group and the second core group through the inter-core communication agent to obtain a verification control instruction; converting the test case into a chip register operation instruction or a real-time operating system drive call instruction based on the verification control instruction; distributing the chip register operation instruction to the first core group to execute a hardware real-time verification process, and distributing the real-time operation system drive calling instruction to the second core group to execute a multi-task scheduling verification process so as to respectively obtain a corresponding register snapshot and a task scheduling log; and aligning the register snapshot with the task scheduling log according to a time axis so as to generate a chip function verification result report based on the alignment data. Cooperative verification of bare computer verification and real-time operating system verification is realized.

An eye-diagram index analytic method includes: calculating a transfer function of multiple coupled lines; converting the transfer function into a pulse response; calculating an eye-diagram index according to the pulse response; and correcting the eye-diagram index according to peak distortion analysis.

The invention provides a chip testing method and device, equipment, a storage medium and a program product. The method comprises the steps that operator codes, comprising multiple chip interface instructions, of a target operator are obtained, the target operator and a reference operator have the same calculation function, the chip interface instructions are used for achieving at least one hardware operation of a chip, and the hardware operations combining the multiple chip interface instructions are used for achieving the calculation function; analyzing the operator code to obtain a machine code file of the chip; test data are obtained, the test data and the machine code file are transmitted to chip simulation equipment, the chip simulation equipment is used for executing the machine code file on the test data, and a simulation calculation result of the target operator for the test data is obtained; obtaining a simulation calculation result from chip simulation equipment, and obtaining a reference calculation result of the reference operator for the test data; and generating a test result of the chip based on the simulation calculation result and the reference calculation result. According to the invention, the chip test progress can be accelerated.

The invention aims to provide a method and a system for realizing a built-in self-test code of a PCIE (Peripheral Component Interface Express) physical layer. The method comprises the following steps of: integrating PCIE BIST GEN module packaging data in a controller layer and sending the data to a physical coding sub-layer; the physical coding sub-layer codes the packaged data and sends the coded data to the physical medium adaptation layer; and the physical medium adaptation layer converts the coded data into serial data and transmits the serial data back to the controller layer. According to the invention, the BIST test assembly meeting the PIPE protocol requirement is embedded in the PCS layer, and compared with a traditional BIST test scheme, through early-stage simulation and post-silicon test data result analysis, not only can the electrical performance test requirement of an original analog circuit be met, but also the test coverage of the PCS layer is increased. And the full-stack coverage test from the physical signal to the protocol logic is realized.

The invention relates to the technical field of storage, in particular to a test method, device, equipment, system, medium and product, and the method comprises the steps: obtaining a test management command of an input and output management command representing error injection in a real working environment of a disk array controller chip; the command is analyzed to obtain the error injection test type and the corresponding related parameters, and the error processing mode is changed according to the error injection test type, so that the exception is only reported and not processed when encountering the exception in the test, the interference of exception processing on the test process is avoided, and the test can be smoothly carried out according to the preset error injection scene; and according to the error injection test type and the related parameters, constructing analog input and output and injecting the analog input and output into the target hardware unit to perform an execution behavior test, thereby realizing accurate test of the specific hardware unit in a specific error scene in an environment of performing input and output test based on a read-write input and output test program, so that the test is more comprehensive, and the test efficiency is improved. And the test precision is higher.

The invention discloses a comprehensive performance evaluation device and method for domestic credit and creativity platform hardware, and the method comprises the implementation steps: constructing a hybrid load task, generating a hybrid load task description file adaptive to the characteristics of domestic hardware, analyzing and executing a dynamic test task, and collecting hardware performance data in real time. And carrying out quantitative scoring by adopting a reference comparison method, generating a radar map portrait, and carrying out multi-dimensional performance evaluation on a domestic processor, a memory, storage and network equipment. According to the method, based on customized instruction extension characteristics of a domestic credit and creativity platform, evaluation deviation caused by mismatching of a traditional evaluation architecture is eliminated through domestic hardware load adaptation; a dynamic hybrid load technology is introduced, so that response robustness and resource cooperation efficiency meeting dynamic load requirements in a high-complexity scene are realized; a hardware performance quantification algorithm and a visualization technology are combined, and an intuitive and practical performance analysis tool is provided.

The invention discloses a test method and device, electronic equipment and a storage medium, and relates to the technical field of computers, the method comprises the following steps: in response to a preset test instruction, obtaining a drive program corresponding to a graphics processor and a toolkit supporting operation of a centralized communication library to be tested, and deploying the drive program and the toolkit into a plurality of host machines; the host machine comprises a plurality of graphics processors; installing a centralized communication library to be tested and a centralized communication library test tool set in the host machine; acquiring hardware configuration information and hardware topology information of the host machine, and determining test parameters according to the hardware configuration information and the hardware topology information; and testing the centralized communication library to be tested by using the test parameters and the communication library test tool set. According to the method and the device, the testing efficiency of the centralized communication library can be improved, errors caused by manual operation can be reduced, and the testing accuracy is improved.

The invention provides a full-platform detection system and an identification method, and relates to the field of data detection systems, and the full-platform detection system and the identification method comprise a USB interface module, an analysis and judgment module, a dynamic adjustment module, a driving adaptation module, a data management module, a data interaction module and a security encryption module. By means of the technology, full-process automatic processing from device insertion to final data transmission is achieved, by means of the technology, the storage device can be comprehensively compatible with Windows, Android, iOS, Mac OS and Linux systems, iOS and Mac OS of apple ecology or Windows, Android and Linux of non-apple ecology can easily deal with the conditions, data safe storage and transfer become convenient, and the method is suitable for large-scale popularization and application. The universality and convenience of the storage device are improved, the operation steps of a user are simplified, the interoperability and safety between the device and different operation systems are improved, and the method is suitable for wide application scenes, so that the requirements of the user for backing up and transferring data between different platforms are met.

The invention relates to the technical field of solid state disks, and provides a solid state disk data storage security test method and device, and the method comprises the steps: generating original test data of a solid state disk in a preset test environment; performing a simulation attack on the solid state disk according to a preset strength grade and preset duration, and obtaining a data block after the simulation attack of the original test data after the simulation attack is finished; recovering the data block after the simulation attack based on the verification data, and obtaining a primary data recovery rate, a secondary data recovery rate and a data error rate of the data block after the simulation attack in the recovery process; calculating a data storage security score of the solid state disk according to the primary data recovery rate, the secondary data recovery rate and the data error rate; and determining a data storage security level of the solid state disk according to the data storage security score. According to the method, the data storage security of the solid state disk under various complex environments and security threats can be comprehensively, systematically and deeply evaluated.

The invention discloses a server hardware testing terminal and method, and relates to the technical field of server hardware testing, and the method comprises the steps: obtaining server hardware configuration parameters and storage equipment specification information, collecting the number of processor cores, memory capacity and storage equipment read-write speed reference data through a system monitoring interface, building a hardware performance baseline file, and storing the baseline file in a server; obtaining a complete hardware resource list and a performance index range; the method comprises the following steps: constructing a multi-dimensional workload model according to information retrieval scene features, creating query request sets of different scales by adopting a random number generator, simulating a mixed load mode of full-text retrieval and database query, and determining resource consumption weights and execution time distribution of various query operations; and analyzing query request distribution characteristics in the workload model through a dynamic load balancing algorithm, if query requests are concentrated in a specific time period, adjusting a load distribution strategy, obtaining a uniformly distributed test load sequence, and judging the impact degree of a load peak value on hardware resources.

A chip testing method, an electronic device and a computer-readable medium. The method comprises: receiving a testing starting instruction sent by a testing upper computer, wherein the testing starting instruction specifies corresponding testing script data, and the testing script data is pre-stored in a testing lower computer; on the basis of the testing script data corresponding to the testing starting instruction, testing a target chip, so as to obtain a testing result; and sending the testing result to the testing upper computer.

The invention belongs to the technical field of display screens, and mainly provides a model construction method, a display screen uniformity correction method, a display screen uniformity correction device and display screen uniformity correction equipment. Inputting the brightness information and the chromaticity information of the display area to be corrected into a pre-established display screen RGB gain prediction model to obtain an estimated RGB gain output by the display screen RGB gain prediction model, and performing brightness and chromaticity uniformity correction on the display area to be corrected based on the estimated RGB gain. The brightness and chromaticity uniformity correction of the to-be-corrected display area is realized by one key based on the brightness information and chromaticity information of the to-be-corrected display area and the pre-established display screen RGB gain prediction model, and the problems that a traditional display screen brightness and chromaticity uniformity correction method is low in correction efficiency and needs to consume relatively high manpower and time are solved; and frequent implementation is difficult.

The invention discloses a test method and device for automatically checking BMC information and a storage medium. The test method and device are used for solving the problem that a traditional interface test cannot prevent information messy codes on a web. The method comprises the following steps: logging in a BMC login page by using an automatic tool according to configuration file data to obtain a BMC user page; processing the BMC user page to obtain a user page screenshot; calling Tesseract-OCR (Optical Character Recognition) to perform character recognition on the user page screenshot according to preset position data so as to obtain page data; judging whether the page data conforms to a preset verification rule or not; and if yes, executing the next BMC test.

The invention relates to a fault simulation method, a test method, equipment and a system for a Flexray bus. The fault simulation method for the Flexray bus comprises the following steps of: determining bus time information of the Flexray bus, the bus time information at least comprises information used for describing a period of the Flexray bus and time slots in the period; and based on the bus time information, performing fault simulation in a specified time slot of a specified period of the Flexray bus.

The invention relates to a multi-dimensional aging test data analysis system and method, and aims to realize real-time acquisition and intelligent analysis of multiple performance indexes in the aging process of electronic products. The system comprises an information acquisition module, a test scheduling module, a data processing module, an analysis module, an abnormity judgment module, a report module and a communication module. Cooperative work among the modules is realized based on task driving and data circulation, accurate association of test data is realized through bar code binding, and unified analysis is performed in combination with multi-source information such as USB read-write performance, network transmission state and display resolution. The system realizes multi-task concurrent acquisition through a resource-aware scheduling strategy, and the analysis module identifies performance abnormity and outputs a structured report by combining preprocessing, feature extraction and time sequence prediction. According to the method, the test automation level and the anomaly recognition accuracy are improved.

The invention relates to a storage performance test method, equipment and a medium, which are used for testing storage performance data of a distributed storage system in various test scenes. The method comprises the following steps: in response to a test mode selected by a user, when it is determined that the selected test mode is a specified time delay mode, obtaining a target time delay and an adjustment coefficient input by the user; executing at least one pre-test in a test object at an initial queue depth, and determining a target queue depth according to the test delay of the pre-test, the target delay and the adjustment coefficient; and executing a storage performance test in the test object by using the target queue depth to obtain storage performance data of the test object.

The invention discloses a computer self-check cycle optimization method based on the Internet of Things in the technical field of server maintenance, and relates to the technical field of server maintenance. Server node operation state data is collected in real time, a dynamic load evaluation model is constructed, and a comprehensive load index is calculated; and dynamically dividing performance states based on the threshold values L1 and L2, and adjusting a self-checking period and a module priority. Calculating a single-node risk index Ri by adopting a fault risk model, generating a fault generalization risk factor R1 through a probability graph model in combination with network topology, and triggering a linkage mechanism; dividing and dynamically adjusting a self-checking period according to the early warning level; during advanced early warning, redundant resources are distributed to preferentially process key faults, edge calculation is combined to carry out data cleaning and standardization, distributed management is realized through a consistent Hash algorithm, and finally, a visual interface is used for displaying an optimized scheduling result, so that a closed-loop optimization system of data acquisition, risk prediction and resource scheduling is formed.

According to the automatic test error-proofing detection method and detection system disclosed by the invention, after a test instruction is received, verification requests generated by bar codes of a needle bed upper mold and a needle bed lower mold are received; sending to a selected product test program to judge whether the needle bed upper die and the needle bed lower die and whether the needle bed name is matched with the current product test program or not; if not, stopping the test, otherwise, after the to-be-tested product is placed in place, receiving a serial number of the to-be-tested product generated by the bar code of the to-be-tested product, and querying and obtaining internal card binding information of the corresponding to-be-tested product; controlling the test tool to start and electrify the to-be-tested product, acquiring identity information of an internal clamping piece actually mounted in the to-be-tested product, comparing the identity information with inquired binding information of the internal clamping piece, if the identity information is consistent with the binding information of the internal clamping piece, carrying out subsequent function test, otherwise, sending error information of the internal clamping piece, and controlling the test tool to pull open an upper die and a lower die of the needle bed; therefore, automatic error-proofing detection of each module test of the industrial control system is realized.