1163results about "Faulty hardware testing methods" patented technology

The invention relates to the technical field of hard disk testing and verification, in particular to a multi-thread-based solid state disk reliability automatic testing method and system.The method comprises the steps that firstly, SMART information is deeply analyzed through microsecond-level high-granularity continuous performance monitoring, and multi-thread parallel processing is assisted; according to the method, fine performance fluctuation of the solid state disk under the concurrent load can be quickly captured, a fault mode can be identified, then early warning is realized by utilizing the extracted multi-dimensional features and a machine learning model, and a detailed fault diagnosis report is generated; and through dynamic error correction code strength verification and data integrity verification under pressure, an internal error correction mechanism of the solid state disk is actively detected and optimized. And finally, in combination with prediction reliability modeling, the system can estimate the remaining service life and predict faults, and provides product optimization suggestions for design, manufacturing and firmware optimization of the solid state disk, so that automation, intelligence and full life cycle management of the fault detection reliability of the solid state disk are realized.

The invention discloses a hardware fault real-time detection method and system based on cooperation of a CPU (Central Processing Unit) and a BMC (Baseboard Management Controller), and the method comprises the following steps: respectively collecting high-frequency state data and tendency indexes by establishing a communication mechanism between the CPU and the BMC; the processor uses a CUSUM algorithm to carry out abrupt change analysis on the periodically collected operation state to generate an abrupt change event; and the management controller uses an EWMA algorithm to model the trend data, and extracts abnormal changes. And the system performs fusion analysis on the mutation event and the trend anomaly to form a fusion anomaly vector. The risk assessment module calculates a risk score based on a preset rule, determines a fault level, positions a target component, and outputs a processing strategy. And triggering a response action according to the strategy and recording an execution state. And the fusion data and the response record are input into the adaptive module together for dynamically adjusting CUSUM and EWMA parameters, so that adaptive updating of the algorithm is realized, and finally a fault detection signal is generated.

The invention relates to the technical field of deep learning, in particular to an AI chip test parameter adaptive optimization method based on deep learning, which comprises the following steps: acquiring historical test data of an AI chip, and calculating correlation strength among different failure modes based on the historical test data; identifying a failure coupling matrix according to the edge weight, and converting a preset static detection parameter constraint boundary into a dynamic constraint space changing along with a failure detection state; a multi-level optimization framework is constructed, the upper layer executes failure type correlation analysis and generates constraint propagation information, the middle layer optimizes a parameter cluster based on the constraint propagation information, and the lower layer adjusts a single detection parameter and outputs a parameter optimization result; establishing a neural network mapping model, and obtaining a nonlinear mapping relationship between the detection parameters and the failure types; based on the physical state parameters, the nonlinear mapping relation is adjusted, the dynamic constraint space is updated, parameter optimization is executed again, a parameter optimization result is output, and an optimal test parameter combination is output.

The invention provides a hard disk testing method, a hard disk fault early warning method and a hard disk fault early warning device, which can be applied to the technical field of storage equipment. The hard disk testing method comprises the following steps: processing a to-be-tested hard disk to enable the to-be-tested hard disk to reach a steady state condition; executing an advanced formatting operation on the to-be-tested hard disk reaching the steady state condition to obtain the to-be-tested hard disk after the advanced formatting operation is completed; based on a plurality of preset overwriting proportions, testing operation is executed on the to-be-tested hard disk after the advanced formatting operation is completed, performance testing data are obtained, and the overwriting proportions are proportions of the overwriting area space in the to-be-tested hard disk space after the advanced formatting operation is completed; according to the performance test data corresponding to the multiple preset overwriting proportions, a performance test result is obtained, and the performance test result represents the performance recovery capability of the to-be-tested hard disk after the advanced formatting operation is completed.

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

The invention discloses a memory test method and device based on an AI technology and a medium, and the method comprises the following steps: 1) obtaining structure analysis data and memory type description information of a to-be-tested memory, and generating a test intention vector used for expressing a test target; 2) taking the test intention vector as an input to generate a test excitation sequence; 3) executing the test excitation sequence, and performing multi-cycle test on the storage array to form a multi-modal response feature set; 4) inputting the multi-modal response feature set into a graph neural network, performing fault type identification and causal path reasoning, and generating a fault tag sequence and a reasoning path graph; 5) based on the characteristic difference between the inference path diagram and the test excitation sequence, weight parameter updating of the depth generation model is carried out; and 6) generating a test excitation sequence based on the updated depth generation model to test the memory. The intelligent level and the test coverage rate of the memory test can be effectively improved.

The invention belongs to the technical field of cloud computing and software testing, and particularly discloses an automatic fault injection and recovery testing method based on cloud native, which comprises the following steps: acquiring test basic data of a to-be-tested cloud native system; constructing a fault test execution model according to the test basic data; according to the fault test execution model, executing an automatic fault injection operation; generating an abnormal alarm log according to the system running state after the fault injection operation, and synchronously recording a fault injection operation log; according to the abnormal alarm log, executing automatic fault recovery operation; and generating a fault test report according to the fault injection operation log, the system monitoring data and the recovery operation process log. The invention aims to solve the problems of low automation degree, narrow scene coverage, weak monitoring evaluation and passive recovery in cloud native system fault test in the prior art, and provides a comprehensive, automatic, monitorable and evaluable fault injection and recovery test scheme.

The invention discloses a memory test system and method, a board card and a server. The memory test system comprises an out-of-band management unit and a target chip, the out-of-band management unit sends a pressure test instruction to the target chip through the preset communication interface, the pressure test instruction comprises dynamically adjusted test strength parameters, and the pressure test instruction is generated based on a preset instruction set; the target chip performs calibration verification on the target memory in response to the pressure test instruction; after the calibration verification is passed, a test load is applied to the target memory according to the test strength parameter, and a cyclic pressure test is executed; the target chip collects test data generated in the pressure test process and transmits the test data back to the out-of-band management unit through the preset communication interface, and the out-of-band management unit generates structured test data according to the test data. Compared with the prior art, the situation that normal services are interrupted due to testing in a traditional testing method can be avoided, and the availability and stability of the system in the testing process are guaranteed.

The invention discloses a chip prototype verification method and device, a medium and a product, and relates to the technical field of integrated circuit verification, and the method comprises the steps: dynamically dividing a central processing unit core of a multi-core chip into a first core group and a second core group in a chip prototype verification platform; performing data interaction on the first core group and the second core group through the inter-core communication agent to obtain a verification control instruction; converting the test case into a chip register operation instruction or a real-time operating system drive call instruction based on the verification control instruction; distributing the chip register operation instruction to the first core group to execute a hardware real-time verification process, and distributing the real-time operation system drive calling instruction to the second core group to execute a multi-task scheduling verification process so as to respectively obtain a corresponding register snapshot and a task scheduling log; and aligning the register snapshot with the task scheduling log according to a time axis so as to generate a chip function verification result report based on the alignment data. Cooperative verification of bare computer verification and real-time operating system verification is realized.

The invention provides a chip testing method and device, equipment, a storage medium and a program product. The method comprises the steps that operator codes, comprising multiple chip interface instructions, of a target operator are obtained, the target operator and a reference operator have the same calculation function, the chip interface instructions are used for achieving at least one hardware operation of a chip, and the hardware operations combining the multiple chip interface instructions are used for achieving the calculation function; analyzing the operator code to obtain a machine code file of the chip; test data are obtained, the test data and the machine code file are transmitted to chip simulation equipment, the chip simulation equipment is used for executing the machine code file on the test data, and a simulation calculation result of the target operator for the test data is obtained; obtaining a simulation calculation result from chip simulation equipment, and obtaining a reference calculation result of the reference operator for the test data; and generating a test result of the chip based on the simulation calculation result and the reference calculation result. According to the invention, the chip test progress can be accelerated.

The invention discloses a comprehensive performance evaluation device and method for domestic credit and creativity platform hardware, and the method comprises the implementation steps: constructing a hybrid load task, generating a hybrid load task description file adaptive to the characteristics of domestic hardware, analyzing and executing a dynamic test task, and collecting hardware performance data in real time. And carrying out quantitative scoring by adopting a reference comparison method, generating a radar map portrait, and carrying out multi-dimensional performance evaluation on a domestic processor, a memory, storage and network equipment. According to the method, based on customized instruction extension characteristics of a domestic credit and creativity platform, evaluation deviation caused by mismatching of a traditional evaluation architecture is eliminated through domestic hardware load adaptation; a dynamic hybrid load technology is introduced, so that response robustness and resource cooperation efficiency meeting dynamic load requirements in a high-complexity scene are realized; a hardware performance quantification algorithm and a visualization technology are combined, and an intuitive and practical performance analysis tool is provided.

The invention discloses a test method and device, electronic equipment and a storage medium, and relates to the technical field of computers, the method comprises the following steps: in response to a preset test instruction, obtaining a drive program corresponding to a graphics processor and a toolkit supporting operation of a centralized communication library to be tested, and deploying the drive program and the toolkit into a plurality of host machines; the host machine comprises a plurality of graphics processors; installing a centralized communication library to be tested and a centralized communication library test tool set in the host machine; acquiring hardware configuration information and hardware topology information of the host machine, and determining test parameters according to the hardware configuration information and the hardware topology information; and testing the centralized communication library to be tested by using the test parameters and the communication library test tool set. According to the method and the device, the testing efficiency of the centralized communication library can be improved, errors caused by manual operation can be reduced, and the testing accuracy is improved.

The invention discloses a server hardware testing terminal and method, and relates to the technical field of server hardware testing, and the method comprises the steps: obtaining server hardware configuration parameters and storage equipment specification information, collecting the number of processor cores, memory capacity and storage equipment read-write speed reference data through a system monitoring interface, building a hardware performance baseline file, and storing the baseline file in a server; obtaining a complete hardware resource list and a performance index range; the method comprises the following steps: constructing a multi-dimensional workload model according to information retrieval scene features, creating query request sets of different scales by adopting a random number generator, simulating a mixed load mode of full-text retrieval and database query, and determining resource consumption weights and execution time distribution of various query operations; and analyzing query request distribution characteristics in the workload model through a dynamic load balancing algorithm, if query requests are concentrated in a specific time period, adjusting a load distribution strategy, obtaining a uniformly distributed test load sequence, and judging the impact degree of a load peak value on hardware resources.

A chip testing method, an electronic device and a computer-readable medium. The method comprises: receiving a testing starting instruction sent by a testing upper computer, wherein the testing starting instruction specifies corresponding testing script data, and the testing script data is pre-stored in a testing lower computer; on the basis of the testing script data corresponding to the testing starting instruction, testing a target chip, so as to obtain a testing result; and sending the testing result to the testing upper computer.

The invention belongs to the technical field of display screens, and mainly provides a model construction method, a display screen uniformity correction method, a display screen uniformity correction device and display screen uniformity correction equipment. Inputting the brightness information and the chromaticity information of the display area to be corrected into a pre-established display screen RGB gain prediction model to obtain an estimated RGB gain output by the display screen RGB gain prediction model, and performing brightness and chromaticity uniformity correction on the display area to be corrected based on the estimated RGB gain. The brightness and chromaticity uniformity correction of the to-be-corrected display area is realized by one key based on the brightness information and chromaticity information of the to-be-corrected display area and the pre-established display screen RGB gain prediction model, and the problems that a traditional display screen brightness and chromaticity uniformity correction method is low in correction efficiency and needs to consume relatively high manpower and time are solved; and frequent implementation is difficult.

The invention relates to a multi-dimensional aging test data analysis system and method, and aims to realize real-time acquisition and intelligent analysis of multiple performance indexes in the aging process of electronic products. The system comprises an information acquisition module, a test scheduling module, a data processing module, an analysis module, an abnormity judgment module, a report module and a communication module. Cooperative work among the modules is realized based on task driving and data circulation, accurate association of test data is realized through bar code binding, and unified analysis is performed in combination with multi-source information such as USB read-write performance, network transmission state and display resolution. The system realizes multi-task concurrent acquisition through a resource-aware scheduling strategy, and the analysis module identifies performance abnormity and outputs a structured report by combining preprocessing, feature extraction and time sequence prediction. According to the method, the test automation level and the anomaly recognition accuracy are improved.

The invention discloses a computer self-check cycle optimization method based on the Internet of Things in the technical field of server maintenance, and relates to the technical field of server maintenance. Server node operation state data is collected in real time, a dynamic load evaluation model is constructed, and a comprehensive load index is calculated; and dynamically dividing performance states based on the threshold values L1 and L2, and adjusting a self-checking period and a module priority. Calculating a single-node risk index Ri by adopting a fault risk model, generating a fault generalization risk factor R1 through a probability graph model in combination with network topology, and triggering a linkage mechanism; dividing and dynamically adjusting a self-checking period according to the early warning level; during advanced early warning, redundant resources are distributed to preferentially process key faults, edge calculation is combined to carry out data cleaning and standardization, distributed management is realized through a consistent Hash algorithm, and finally, a visual interface is used for displaying an optimized scheduling result, so that a closed-loop optimization system of data acquisition, risk prediction and resource scheduling is formed.

The invention discloses a fault prediction and self-repairing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. According to the method, the function of dynamically monitoring various data of processor hardware for the target node can be realized, the dynamically monitored hardware state data is input, the fault probability is predicted by a method of weighting and combining key indexes through a bidirectional long-short-term memory model and an attention mechanism, the possible faults are intelligently predicted, and the fault prediction efficiency is improved. And when the target node has a test fault in advance, the target node is repaired in a gradual load reduction mode, so that the effects of real-time monitoring, accurate prediction and rapid self-regulation are achieved. Manual intervention is reduced, the intelligent decision-making capability is achieved, operation and maintenance automation and intelligentization are achieved, resource self-adaptive repairing can be integrated, the self-adaptive capability is improved, and the complex scene fault sensing capability is improved.

A method for processing faulty memory module and apparatus, and an electronic device and a non-transitory readable storage medium are provided. The method for processing faulty memory module includes: acquiring a first power-down command, the first power-down command being used for instructing a baseboard management controller of a memory resource pool to perform power-down processing on a faulty memory module in the memory resource pool; and in response to the first power-down command, when a first memory module in the memory resource pool is in a fault state and is allowed to be powered down, sending a second power-down command to a target memory expander controller to which the first memory module belongs, the second power-down command being used for instructing the target memory expander controller to perform power-down processing on the first memory module.

The invention relates to the technical field of intelligent detection of board cards, in particular to a multichannel board card detection method and system, electronic equipment and a storage medium. The detection method comprises the following steps: inputting a standard test signal to each channel of the multi-channel board card in a normal environment, analyzing the output signal accuracy, the signal triggering time punctuality and the anti-crosstalk level of adjacent channel pairs, and judging the signal transmission performance; when the signal transmission performance is qualified, environments with different temperatures and vibration conditions are simulated, testing is repeated, performance data in the normal environment and performance data in the simulated environment are compared, and an applicable environment set is determined; and comparing with a corresponding allowed use environment set, and judging the environment adaptation performance. The anti-crosstalk capability quantitative detection and multi-environment adaptation evaluation of the multi-channel board card are realized, so that the signal independence of the multi-channel board card is ensured, the system operation stability is improved, and the reliability of the board card in a complex scene is ensured.

A computer-implemented method for testing an instruction cache logic circuit of an integrated circuit, comprising: storing in the cache logic circuit a sequence of instructions including M instructions; reading an initial counter value of a cache access counter; executing the sequence of instructions and, for each instruction executed from the cache logic circuit, incrementing the current counter value of the counter; reading a final counter value of the counter; blocking an execution of instructions unintended by the test for a period lasting from reading the initial counter value until reading the final counter value; subtracting the initial counter value from the final counter value, and comparing the result of said subtraction with the value M.

The invention discloses integrated electronic brake system PCBA program burning and detecting equipment which comprises a whole machine frame and a burning and testing mechanism, and a burning and testing machine base and a burning and testing upper tool are arranged on the lower portion in the frame of the burning and testing mechanism. A clamping block is slidably arranged at the upper end opening of a butt joint through hole in the burning test upper tool, a hydraulic fluid channel is annularly distributed, and the upper end opening is in linkage with the clamping block through a sleeve spring piston. A reciprocating lead screw in a lead screw box on the rear side is connected with a plate unloading motor and a grabbing clamp through a driving seat, path sliding blocks on the two sides of the grabbing clamp are matched with a downward pressing sliding way on the surface of an upper tool to achieve lifting, the lower portion of the lead screw box is communicated with a liquid pipe through a spring piston, and a toothed plate in a burning frame is meshed with a driving gear; pCBA automatic feeding, discharging, overturning and discharging are achieved through linkage of a grabbing clamp and a transmission mechanism, and the productivity is improved through synchronous operation of a front station and a rear station; the clamping blocks are hydraulically driven to form annular flexible support for the test probe, the posture of the probe is self-adaptively corrected through the arc-shaped clamping blocks, and probe inclination caused by PCBA positioning deviation is avoided.

The invention discloses a fault early warning detection system for a notebook mainboard, and relates to the technical field of electronic detection. The signal acquisition module is used for acquiring temperature and vibration acceleration signals of a main board BGA welding spot; the damage characteristic calculation module is used for calculating the heat effect index and the vibration intensity of the welding spot; the crack prediction module is used for constructing a crack dynamic function based on the thermal effect index and the vibration intensity and calculating the crack growth degree; the risk assessment module is used for calculating a comprehensive risk prediction value according to the crack growth degree in combination with the temperature and the vibration sudden change rate; the root cause analysis module is used for identifying dominant failure factors through a gradient analysis method and outputting failure mode classification; and the dynamic suppression module is used for dynamically adjusting heat, vibration or creep coping measures of the welding spots based on failure mode classification. Through thermal-mechanical coupling damage extraction, crack dynamic modeling and multi-parameter risk grade assessment capabilities, welding spot early damage identification and operation risk early warning can be realized.

The embodiment of the invention provides a core particle, a core particle testing method, a chip and a computer program product, and relates to the technical field of semiconductor testability design, and the core particle comprises a channel switching module; wherein the channel switching module comprises at least one input interface used for receiving a plurality of test data; the at least one output interface is used for forming at least one transmission channel with the input interface so as to respectively send the test data to the core particle or other core particles, the position of the core particle is different from that of the other core particles, and the test data comprises a test signal or a test result corresponding to the test signal. According to the method and the device, the problem of low test efficiency of the core particles in related technologies is solved, and the effect of improving the test efficiency of the core particles is further achieved.

The invention discloses a server power supply board testing method and system, electronic equipment and a storage medium, and relates to the technical field of server power supply board testing, and the method comprises the steps: inputting a testing power supply signal to a server power supply board, and verifying the triggering accuracy of overvoltage protection and undervoltage protection functions of the server power supply board; after a preset power supply signal is converted by a solid-state relay, voltage loading and detection are carried out on a power supply input interface one by one channel, and after it is verified that a power supply protection function and an input interface state are normal, multi-type load fluctuation and communication protocol interaction requirements of a server are dynamically reproduced through a function analog signal. The output stability and protocol compatibility of the server power supply board are evaluated by combining an electronic load dynamic discharge test with a digital signal collaborative feedback mechanism, so that the technical problems of relatively low test efficiency and relatively high test cost of the server power supply board in related technologies are solved, and the purposes of reducing the test cost, improving the test efficiency and improving the test efficiency are achieved. And the test coverage rate is increased.

The invention discloses a test failure root cause diagnosis method, which relates to the technical field of electric digital data processing, and is characterized in that after a test failure signal is captured, comprehensive analysis is carried out in combination with multi-source log information of a test case and test environment configuration data, so that the influence of environment configuration on a test is fully considered, and information in a log is fully mined; according to the method, a more accurate diagnosis result is obtained, and a corresponding solution is matched according to a test failure root cause to solve the problem of test failure, so that the problems of low efficiency and high misjudgment probability of manual analysis, neglect of the influence of a test environment on the test failure, difficulty in identifying implicit connection between texts in a log and difficulty in testing failure in the prior art can be solved. Therefore, the technical problem that the obtained analysis result is difficult to be used for accurate root cause diagnosis is solved, the diagnosis efficiency of test failure root causes is improved, the diagnosis precision is improved, and the overall test period is shortened.

The invention discloses a register model and register transfer level generation and test method, device, equipment and medium, and relates to the technical field of integrated circuit design verification, and the method comprises the following steps: analyzing a comma separation value table file by using a register generation platform to generate a register model, a register transfer level and a register test vector; the comma separation value table file is a file used for describing register information; generating a general verification methodology environment by using a test environment generation platform, and integrating the general verification methodology environment based on the register model, the register transfer level and the register test vector to obtain a corresponding integrated test environment; and compiling the integrated test environment, if the compiling is successful, running the register test vector in the integrated test environment which is successfully compiled, and outputting a corresponding test result. Therefore, the automation degree of register model verification can be improved, and the verification efficiency of front-end verification is improved.

The invention discloses a testing device, a testing method and a testing system for an integrated circuit communication bus, and relates to the technical field of computer communication and electronic testing, the testing device comprises a microcontroller and a bus expansion module which are electrically connected, the microcontroller sends a test control signal to the bus expansion module, the bus expansion module generates a bus abnormal signal, and the bus abnormal signal is sent to the microcontroller. The microcontroller receives a bus abnormal signal and inputs the bus abnormal signal into the to-be-tested device, the to-be-tested device generates test data according to the bus abnormal signal, the bus abnormal signal at least comprises an abnormal interrupt signal, and the microcontroller dynamically adjusts the test control signal according to the test data fed back by the to-be-tested device so as to continue the test. By introducing the multi-channel bus expansion module with special programmable control capability and combining the intelligent interpretation capability of the microcontroller, the multi-channel polling test is realized, and various bus abnormal signals, especially interrupt signals, can be accurately generated and injected in real time, so that the robustness and other characteristics of equipment to be tested are comprehensively evaluated.

The invention relates to the technical field of hardware testing, and discloses a test board card, a test system and a test method for a hard disk backplane, and a server-side first transceiving interface in the test board card is used for receiving a control command sent by a server; the test instruction simulation module is used for generating a first test instruction according to the control command; the server side second transceiving interface is used for receiving a second test instruction sent by the server; and the controller is used for sending the first test instruction or the second test instruction to the hard disk backboard side transceiving interface, receiving first feedback information or second feedback information of the hard disk backboard, and feeding back the first feedback information or the second feedback information to the server. Therefore, under the two conditions that the VPP and the I2C of the server can not directly communicate with the hard disk backboard, the hard disk backboard can be tested, the test board card can be suitable for various types of servers, and the server can be reused when the test board card is used for testing the hard disk backboard.

The invention relates to the technical field of power supply testing, in particular to a power supply testing system and method. Comprising the following steps: performing power supply demand simulation based on a load transition mechanism: performing deep analysis on a correlation relationship among components of a load by using demand analysis, and performing power supply demand simulation according to a deep analysis result; and constructing a power supply response state set based on the power supply demand simulation result and in combination with the load response characteristics, and carrying out the adaptability test of the power supply behavior through a power supply adaptability clustering algorithm according to the distribution characteristics of the load states under different configurations. According to the method, the instantaneous peak value, the stable power consumption and the load transition characteristics are extracted, the power supply response model is constructed in combination with the load state, and the fitting degree of the real power supply demand of each component is improved; and through a multi-round clustering center iteration verification and adjustment mechanism, it is ensured that the test covers the power supply threshold of all components, and the comprehensiveness and reliability of the power supply test are improved.