Chip software and hardware simulation environment based on UVM and FPGA

Abstract

The invention discloses a chip software and hardware simulation environment based on the UVM and the FPGA. The simulation environment comprises an FPGA verification platform, a UVM verification platform and an IP standard model. The IP standard model is connected with the FPGA verification platform, and the FPGA is driven to perform simulation verification and sends the FPGA verification result as scene environment configuration to the UVM verification platform. The UVM verification platform is connected with the IP standard model and calls an algorithm in the IP standard model to perform UVM simulation verification to the FPGA verification result. According to the chip software and hardware simulation environment based on the UVM and the FPGA, the IP standard model is connected with the FPGA verification platform and the UVM verification platform, and the software and hardware simulation environment which performs FPGA verification and UVM verification simultaneously is prepared. The FPGA verification focuses on the chip application layer and completes verification of a chip code to a lot of random excitation scenes; the UVM verification focuses on the chip bottom layer and performs further verification to the FPGA verification result by directly calling the algorithm in the IP standard model; the two kinds of verification are mutually matched, the verification period of the chip is accelerated, and the chip verification quality is improved.

Description

technical field [0001] The invention relates to the field of chip simulation verification, in particular to a chip software and hardware simulation environment based on UVM and FPGA. Background technique [0002] In recent years, with the emergence of large-scale SOC and multi-core designs, the design of application-specific integrated chips (ASICs) has become more and more complex, and the functional complexity of chips has increased greatly, making the verification requirements of chips more and more high. How to complete the chip function verification in a short time and ensure the correct logic function puts forward higher requirements for the completeness, automation and reusability of the verification environment. [0003] FPGA verification uses hardware description language to write test cases for the design under test. After simple simulation, the netlist is synthesized and downloaded to the target board for debugging. By observing the output waveform, it is judged w...

AI Technical Summary

Problems solved by technology

However, due to the limited simulation speed, UVM verification cannot traverse too many scenarios, which is suitable for small and complex chip verification

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