16 results about "Design under test" patented technology

This application relates to the field of chip verification technology, and in particular to a method for constructing a verification platform for flexible GPU interconnection. It includes: obtaining a topology information description file; the topology information description file includes interconnection information of several topologies and topology information of each design under test (DUT) included in each topology; the DUT is a functional module in the GPU that is interconnected with external systems; instantiating the DUT according to the topology information description file; constructing a verification environment in the test platform that matches the topology in the topology information description file according to a dynamic configuration file; the dynamic configuration file is obtained by parsing the topology information description file; and implementing connections between DUTs and between the DUTs and the verification environment according to the dynamic configuration file. This invention can solve the problems of existing methods, such as fixed verification environment structure, insufficient reusability and scalability, and difficulty in supporting verification of multiple types of DUTs and various interconnection topologies and interconnection modes.

This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastable states cannot be simulated in EMU simulation verification environments before chip design. This application adds a metastable state simulation circuit after the trigger synchronization circuit constructed based on a multi-level trigger cascade mode. The metastable state simulation circuit simulates cross-clock domain metastable data output scenarios. The technical solution provided in this application complements the CDC simulation method in the DV design verification environment, effectively identifying potential problems in the design under test under CDC scenarios in the early stages of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the chip development process.

This disclosure provides a method and system for large-scale model-assisted logic function simulation and verification for hardware design, relating to the fields of artificial intelligence and hardware design technology. The method includes: performing logical perception analysis on hardware design specifications to generate a structured design analysis report; based on the design analysis report and design specifications, using a generator agent to initially generate a testbench, obtaining an initial test platform and a reference design under test set; simulating the initial test platform and the reference design under test set, and verifying the initial test platform using a consensus verification mechanism based on confidence levels; iteratively refining the test platform using a corrector agent based on a structured reflection report to obtain the final optimal test platform; and automatically generating a retrieval knowledge base precisely aligned with hardware semantics using a reflexive domain knowledge mining method, achieving fully automated construction of the hardware domain knowledge base. This disclosure achieves fully automated system-level hardware design testbench generation and verification.

The application discloses a method for modifying RTL source code files and an electronic device, the method comprising: obtaining all RTL source code files of a design under test and a file name of a top RTL source code of the design under test, associating instantiation names of each module in each RTL source code file with the file name, and saving the association result as a tree type data structure; obtaining all signal names corresponding to each module in each RTL source code file one by one, and position information of each RTL source code file corresponding to the data structure, adding a prefix before the signal name to obtain a complete signal name according to the position information; selecting at least one signal to be observed from all complete signals, detecting each signal to be observed in a list of signals to be observed one by one to obtain a detection result, and modifying the RTL source code file corresponding to the signal to be observed based on the detection result. The application solves the technical problem of low efficiency of adaptive modification of a design under test in the prior art.

The application relates to the technical field of chip verification, in particular to a cross-domain verification bridging system for system-level chip verification, which comprises a configuration file acquisition module, a server, a transaction-level protocol transmitter and a client. The configuration file acquisition module is used for acquiring a configuration file. The server is used for connecting a corresponding target client based on the configuration file, adapting a corresponding target transaction-level protocol transmitter for the target client, receiving a request of the target client, distributing the request to the corresponding target transaction-level protocol transmitter, returning a response of the target transaction-level protocol transmitter to the target client, accessing a design under test based on the corresponding request, and receiving a response of the design under test. The client is used for generating and running an application program, a driver program or a test case, and sending a request to the server by calling a corresponding preset application programming interface. The application reduces the complexity of cross-domain verification of system-level chip verification and improves the cross-domain verification efficiency of system-level chip verification.

The application relates to the technical field of integrated circuits and provides a verification platform, a verification method, electronic equipment and a medium. The verification platform comprises: an application layer bus function level model, which comprises a customized interface for a design under test for interaction with the design under test, wherein the design under test is a PCIe protocol interface and protocol compliance test suite, the PCIe protocol interface and protocol compliance test suite supports verification requirements of a physical layer intellectual property core and supports verification requirements of PCIe controller plus physical layer subsystem level protocol consistency; and the design under test interacts with the application layer bus function level model through the customized interface. In this way, the integration and through-flow debugging cost of subsystem protocol consistency verification is reduced, the verification period of PCIe subsystem protocol standardization interface testing is shortened, and the completeness of PCIe subsystem full-quantization protocol interface verification and the platform reuse efficiency are improved.

This application relates to a read / write cache verification method, an electronic device, a computer-readable storage medium, and a program product. The method includes: acquiring the request-response result corresponding to an input request generated by the design under test (DUT) module in each clock cycle according to a preset hardware description language; acquiring the response reference result corresponding to the input request output by a white-box model in each clock cycle according to the hardware description language; sequentially comparing the request-response result and the response reference result in each clock cycle to obtain a white-box verification result; acquiring the output reference result corresponding to the input request output by a black-box model based on a preset read / write cache logic; acquiring the request processing result corresponding to the input request output by the DUT module, comparing the request processing result with the output reference result to obtain a black-box verification result; and comparing the white-box verification result with the black-box verification result to obtain the read / write cache verification result of the DUT module. This method can improve the verification correctness.

This application provides a chip functional verification method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: decomposing the design under test (DUT) into multiple first sub-modules; and decomposing a reference model of the DUT into multiple second sub-modules corresponding to the functions of the first sub-modules; simultaneously using the output of the current first sub-module as the input of the next first sub-module downstream of the data stream and the input of the second sub-module corresponding to the next first sub-module; and determining the functional verification result of the DUT based on the comparison results of the outputs of each first sub-module and the corresponding second sub-modules. The method and apparatus provided in this application synchronously decompose the DUT and the reference model and establish a co-simulation mechanism that drives the reference model execution using hardware simulation results. This can quickly and accurately locate chip design defects, improving chip verification efficiency and debugging convenience.

The present disclosure provides a transaction life cycle phase-aware conflict verification method, device and equipment, relating to the technical field of computers, which comprises: obtaining transaction timing phase tracking data of a target transaction request in a design under test; wherein the transaction timing phase tracking data carries a timestamp and a phase label corresponding to a transaction life cycle phase; determining a target conflict strategy from a preset conflict strategy set based on the phase label and the timestamp; wherein the target conflict strategy corresponds to a conflict sensitive point subsequent to the current transaction life cycle phase; generating a conflict transaction request sequence according to the target conflict strategy and sending the conflict transaction request sequence to the design under test for verification. This method can improve the coverage of conflict scenario verification, overcome the problems of test space explosion and constraint loss effective sequence, and improve verification efficiency and convergence speed.

This disclosure relates to the field of computer technology, and more particularly to a verification system, method, electronic device, and storage medium for chip design, comprising: a first verification module that generates a first stimulus of a first interface protocol and sends it to a second verification module; the second verification module that converts the first stimulus into a second stimulus of a second interface protocol and drives it to the design under test (DUT); the second verification module that receives a second response of the second interface protocol from the DUT and sends it to an inspector; the inspector that converts the second response of the second interface protocol into a first response of the first interface protocol and verifies the first response based on the first interface protocol. Embodiments of this disclosure can effectively improve verification efficiency.

The application discloses a method and device for back pressure testing of a design under test, and electronic equipment, and belongs to the computer field. The method comprises the following steps: applying a first excitation signal to the design under test; performing back pressure testing on a plurality of first-in-first-out data buffers in the design under test based on the first excitation signal to obtain a back pressure testing result; wherein the data write operation performed on the plurality of first-in-first-out data buffers is controlled by the first excitation signal during the back pressure testing, and the first excitation signal is obtained based on a same packet sending strategy.

This application provides a verification system, a design verification method, and related equipment. The verification system includes: a slave device module, a listening filter module, and a reference model connected to each other. The slave device module sends a normalized address to the listening filter module to query the corresponding cache line status information. The listening filter module queries the cache line status information based on the normalized address and compares it with the output of the reference model to determine the verification result. The listening filter module includes a design under test (DUT), which includes a local node monitoring unit storing the cache line directory within the corresponding processor node and a remote node monitoring unit storing a cache line directory shared among the processor nodes. Based on the local node monitoring unit and the remote node monitoring unit, the DUT provides different directory query modes. The reference model is a model that performs co-simulation with the DUT to verify the accuracy of the design.

This invention discloses a UVM verification method and system for processor core bus protocol to AXI protocol conversion. The method includes: extending the general interface UVC to obtain a directional interface UVC adapted to both the processor core bus protocol and the AXI protocol; inputting an excitation sequence to the design under test (DUT) through the directional interface UVC, acquiring the signals output by the DUT and converting them into data frames; processing the original bus protocol request, outputting a reference data frame, and comparing the acquired data frame with the reference data frame; performing data coherence detection on the DUT using a storage model; and determining whether the verification passes by combining the comparison result and the data coherence detection result. This invention effectively solves the technical problems of the lack of a dedicated verification method for the processor core bus protocol to AXI protocol conversion module, the difficulty of data coherence verification, and the long verification convergence period.

The application discloses a kind of chip atomic characteristic verification system, method, device and storage medium, it is related to chip design and chip test field, the system includes: atomic characteristic excitation device is used to send random excitation signal to atomic test model device and chip design under test;Atomic test model device is used to obtain the expected output data corresponding to random excitation signal;Output monitoring device is used to obtain the actual output data of chip design under test for random excitation signal;Function result comparison device is used to obtain the function verification result of chip design under test according to actual output data and expected output data;Behavior consistent monitoring device is used to concurrently obtain the behavior consistency verification result of chip design under test.The technical scheme of the embodiment of the application simultaneously obtains the function verification result and the behavior consistency verification result by parallel monitoring mode, not only improves test efficiency, and ensures the comprehensiveness of atomic characteristic verification result of chip.