109 results about "Design under test" patented technology

Embodiments of the present disclosure include a software solution for generating a connectivity file that forms the connections between signals in a design under test (DUT) and signals in a verification IP (VIP) interface. The connecting signals from the DUT may form a DUT interface and the DUT interface may follow a protocol. The software solution may utilize a generative AI-based tool to identify example connections that also follow the protocol. These example connections may be included in a query to a large language model (LLM) for purposes of improving the results generated by the LLM.

The present disclosure provides a verification system, a verification method, an electronic device and a storage medium. The verification system includes a simulation verification device, a first portion and a second portion. The first portion includes a first master module and a second slave module. The second slave module includes a memory unit connected to a memory access interface at a periphery of a design under test. The second portion includes a first direct programming interface, a second direct programming interface, a function library module, and a test case module. The first direct programming interface communicates with the first master module and is configured to call a first function to implement front door access to a register of the design under test. The second direct programming interface communicates with the memory unit and is configured to call a second function to implement back door access to the memory unit.

The embodiment of the invention discloses an input excitation completeness detection method, system and device and a storage medium, relates to the technical field of semiconductor verification, and aims to improve the efficiency of port signal excitation completeness verification. The method comprises the following steps: analyzing a signal attribute of an input port in a tested design file; based on the signal attributes, generating a function coverage rate file covering all input signals, the function coverage rate file including value coverage logic detection assertions corresponding to different signal attributes and function coverage rates; and monitoring and detecting the function coverage state of the current input excitation signal according to the function coverage file. The method is suitable for verification scenes of semiconductors such as chips and the like.

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

The invention provides a simulation method for message deduplication in a VRA mode and a related device, and relates to the technical field of chip verification. The method comprises the steps that whether a first serial number of a current message is larger than a second serial number or not is judged, the second serial number is the maximum serial number of a sent message in a target table item, the target table item is a table item corresponding to a target flow to which the current message belongs in a lookup table, and the table item of the lookup table further comprises a message record corresponding to the flow; the message record is used for indicating that the processing state corresponding to the serial number of the sent message is sent; if yes, calculating to obtain a difference value between the first serial number and the second serial number; according to the size of the acceptable window, the size of the sliding window and the difference value, a target processing mode of the current message is determined, the lookup table is updated, and the target processing mode indicates that the current message is discarded or sent. Therefore, simulation of message sliding window de-duplication in the VRA mode in FERE can be realized, and function verification of the to-be-tested design can be quickly carried out.

The invention relates to the field of function verification of digital integrated circuits, and discloses an atomic-scale computing chip verification method based on a UVM. The method comprises the following steps: firstly, building a UVM simulation verification platform comprising each core component; then, a software program is used for generating test excitation with physical significance, wherein the test excitation comprises information such as configuration, functional, pseudo potential and track files; then respectively inputting the test excitation into the established UVM verification platform and the software reference model; the UVM verification platform applies the test excitation to the to-be-tested design and outputs a calculation result; the reference model also correspondingly generates a reference result; and finally, comparing the output of the to-be-tested design with the output of the reference model, and verifying the correctness of the function of the atomic calculation chip through visual auxiliary analysis and quantitative error analysis. Through excitation generation based on physical constraints and an effective error evaluation method, the function verification problem of the atomic-scale computing chip can be solved.

A method for data center switching fabric path emulation in an electronics design automation (EDA) environment includes generating emulated data center traffic. The method further includes, at a path emulation element, modifying the emulated data center traffic to emulate passing of the emulated data center traffic through a data center switching fabric. The method further includes outputting, by the path emulation element, the modified emulated data center traffic to an EDA emulator emulating an electronics design under test. The method further includes receiving and storing a response of electronics design under test to the modified emulated data center traffic.

The embodiment of the invention discloses a method and system for generating a function coverage file, electronic equipment and a storage medium, relates to the technical field of semiconductor verification, and can effectively improve the efficiency and accuracy of generating the function coverage file. The method comprises the steps that a tested design file is analyzed, and signal feature information in the tested design file is extracted; the signal feature information comprises a signal name, a bit width attribute and a logic association relationship between signals; generating a table file based on the signal feature information, wherein the table file comprises a signal name field and a corresponding coverage point field; and analyzing the table file, and converting and generating a function coverage rate file according to the signal name field and the corresponding coverage point field. The method is suitable for verification scenes of semiconductors such as chips and the like.

The invention discloses a verification method and device for accelerating function coverage rate convergence, a medium and equipment, the method is applied to a verification platform, the verification platform comprises a directional excitation generator, a function coverage rate model and a to-be-tested design, and the verification platform is provided with a simulation switch. Comprising the following steps: analyzing a code file of a function coverage rate model by utilizing a preset cross use case script file to extract coverage bin information corresponding to a cross function coverage point, and configuring a simulation switch according to the coverage bin information to generate a boundary use case file; and reading switch configuration information in the boundary case file by using a directional excitation generator, generating a directional excitation flow based on the directional instruction sequence according to the switch configuration information, and sending the directional excitation flow to the design to be tested to execute verification work. By adopting the technical scheme of the invention, the boundary use case of the cross function coverage point can be automatically generated, so that the convergence time consumption of the function coverage rate is effectively reduced, and the convergence rate of the function coverage rate is improved.

The invention provides an AXI interconnection module verification platform and electronic equipment, and relates to the technical field of chip verification. The invention discloses an AXI interconnection module verification platform. The verification platform comprises a test module, an interface module, a test case configuration module and a transmission transaction router, the test module comprises an agent cluster, a scoreboard unit, a parameter configuration unit and a virtual sequence transmitter; an interface in the interface module is used for connecting the design to be tested with each agent in the agent cluster; the test case configuration module is used for generating a corresponding test case; and the transmission transaction router is used for distributing the request transaction or the response transaction sent or received by the proxy to the scoreboard in the scoreboard unit. Therefore, according to the AXI interconnection module verification platform in the application, flexible adaptation to a complex topological structure is realized, and verification challenges caused by complexity of the AXI interconnection module are effectively solved.

The invention discloses a software and hardware co-simulation field recovery method and device, equipment and a medium. Comprising the steps of defining a recording starting point and a storage time point of a simulation site; from the recording starting point to the storage time point, capturing transaction flow and causal metadata from the hardware simulation environment of the simulation site to the software test platform, and meanwhile, storing a state snapshot of the verified design in the hardware simulation environment; and when a recovery instruction is received, performing simulation field recovery based on the transaction flow, the causal metadata and the state snapshot. By defining the time range of data capture, a clear boundary is delimited for subsequent data storage, and pertinence and integrity of data records are ensured. A basis is provided for semantic reconstruction of a software test platform by capturing a transaction flow and causal metadata, a state snapshot ensures that the verified design hardware state can be accurately restored, and complete storage of recovery data on the two sides of software and hardware is achieved. And the system does not need to be restarted from the starting point during recovery, so that a redundancy initialization process is avoided, and the simulation debugging efficiency is improved.

The embodiment of the invention provides a chip verification method, system and device and a storage medium, a chip comprises a core particle group, the core particle group is formed by coupling a plurality of core particles, and the method comprises the following steps: based on a core particle verification environment, performing a verification test on a to-be-tested designed core particle; after the core particles pass the verification test, a core particle group verification environment is generated, the core particle group verification environment comprises a plurality of core particle verification sub-environments, and the core particle verification sub-environments are obtained based on instantiation of the core particle verification environment; and based on the core particle group verification environment, carrying out verification test on a to-be-tested designed core particle group. According to the chip verification method in the embodiment of the invention, complete verification of the core particle group can be realized.

The invention discloses an RoCEv2 protocol RC service type basic primitive function verification system based on a UVM. The system comprises a test case class used for configuring verification parameters, initializing a verification environment and driving a primitive execution process; the verification environment is used for packaging a plurality of agent components, a reference model, a register model and a scoreboard and carrying out data interaction through a TLM interface; the agent components are used for driving or monitoring an interface designed to be tested, comprise but are not limited to a register read-write agent, a work queue element WQE reading agent, a load data reading and receiving agent, a data packet sending and receiving agent, a complete queue element CQE receiving agent and a register model component, and are constructed based on a register abstraction layer RAL modeling method; and front-door and back-door access paths are supported. The method is high in automation degree, integrates constraint randomization, comparison verification and coverage rate analysis, and realizes full automation of the verification process.

The invention discloses a direct memory access module verification method and device, equipment and a medium, and relates to the field of integrated circuit verification. Respectively converting each data transmission parameter in the first transaction into each second transaction under an advanced high-performance bus protocol by using a bridge; executing a corresponding data transmission operation based on each second transaction through any direct memory access module, and sending an operation result to a verification component; and obtaining the first transaction and the operation result through the verification component, and verifying any direct memory access module based on the first transaction and the operation result. According to the invention, when the data transmission parameter changes, the verification of the direct memory access module can be realized only by modifying the first transaction under the advanced extensible interface protocol, so that the reusability of the verification platform is realized, and the verification difficulty and complexity are reduced.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

The embodiment of the invention discloses a PCIe interrupt verification method and device, hardware simulation equipment and a medium, and relates to the field of chip verification. The method is executed by a hardware simulation device, the hardware simulation device runs a to-be-tested design and an interrupt processing engine, the to-be-tested design is an RTL code of a PCIe controller, and the method comprises the following steps: generating an interrupt signal triggered by a PCIe interrupt trigger event through the to-be-tested design; determining an interrupt processing mode of the interrupt signal through an interrupt processing engine; and performing interrupt processing on the interrupt signal according to the interrupt processing mode through an interrupt processing engine to obtain an interrupt processing result which is used for determining a verification result of the to-be-tested design. By adopting the PCIe interrupt verification method provided by the invention, the resource bottleneck caused by a host and a Speed Bridge in related technologies is eliminated, the verification efficiency and the test throughput are improved, and the feasibility of large-scale pressure test is realized.

The invention provides a USB measurement and control system collaborative verification platform building method based on the combination of System Verilog and a C language, and relates to the technical field of FPGA testing, the method is based on a Cadence IES simulation environment to build a verification platform of a layered tree topology architecture, the verification platform is independent of a tested design project file, a three-level system structure is adopted, and the verification platform is provided with a three-level architecture; the rtl design layer is used for storing a source code file of a to-be-tested USB measurement and control system baseband processing FPGA (Field Programmable Gate Array) described by adopting a register transmission level; and the tb test platform layer adopts a modular design and comprises a dutif interface definition module, a dutrap design packaging module, a tb test control module and a tbtop top layer integration module. According to the USB measurement and control system collaborative verification platform building method based on the combination of the System Verilog and the C language, intelligent generation of a verification environment is achieved through an automatic script, and the configuration complexity is remarkably reduced; and a parameterized configuration mechanism is adopted, so that different types of USB measurement and control systems can be quickly adapted, and excellent adaptability is shown.

This application relates to the field of chip verification technology, and in particular to a method for constructing a verification platform for flexible GPU interconnection. It includes: obtaining a topology information description file; the topology information description file includes interconnection information of several topologies and topology information of each design under test (DUT) included in each topology; the DUT is a functional module in the GPU that is interconnected with external systems; instantiating the DUT according to the topology information description file; constructing a verification environment in the test platform that matches the topology in the topology information description file according to a dynamic configuration file; the dynamic configuration file is obtained by parsing the topology information description file; and implementing connections between DUTs and between the DUTs and the verification environment according to the dynamic configuration file. This invention can solve the problems of existing methods, such as fixed verification environment structure, insufficient reusability and scalability, and difficulty in supporting verification of multiple types of DUTs and various interconnection topologies and interconnection modes.

An embodiment of the present invention provides a signal control method, apparatus, electronic device, and storage medium. The method includes: configuring each interface in a test program according to the configuration method of each interface in a design under test, and specifying the signals included in the interface; obtaining a first configuration parameter of a first signal in a first interface of the test program; determining a mapping strategy corresponding to the first signal according to the first configuration parameter; determining a second signal in the design under test that matches the first signal based on the mapping strategy; and mapping the first signal and the second signal according to the first configuration parameter and a second configuration parameter of the second signal. By means of dynamic mapping, the signal mapping efficiency is improved, and thus the signal control efficiency is enhanced.

The invention relates to the technical field of nonvolatile memory chips, and discloses a verification method and device for a FLASH memory and a universal verification platform, and the simulation verification method comprises the steps: carrying out the modeling of a signal time sequence in the form of an executable task of a hardware description language based on the time sequence requirement of an operation manual of a target FLASH memory, defining a key time interval between the signals as a configurable parameter; performing parameter configuration on the executable task and the key time interval according to a parameter value input by a user for adapting to the target FLASH memory; according to the configured executable task and the key time interval, generating simulation data, and according to the simulation data, simulating the to-be-tested design of the target FLASH memory model; in the simulation process, a time sequence signal, a voltage signal and a decoding logic signal in a to-be-tested design are checked according to parameterized time sequence requirements. According to the invention, the accuracy and efficiency during simulation verification can be improved.

The present application relates to the technical field of chip verification, and more particularly to a verification system based on a shared register address, comprising: a design under test including a plurality of register groups; a register model for generating register access request information and sending it to an adapter; the adapter for decoding a target logical address, obtaining target PFVF information and a target register address, and generating target transaction information and sending it to a bus agent module; the bus agent module for driving the design under test based on the target transaction information; the design under test is also used to determine a target register group based on the target register address, determine a target register in the target register group based on the target PFVF information, and then execute target access information based on the target register. The present application can be applied to verification of a shared register address, simplifies the verification environment, and improves the efficiency and accuracy of verification.

This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastable states cannot be simulated in EMU simulation verification environments before chip design. This application adds a metastable state simulation circuit after the trigger synchronization circuit constructed based on a multi-level trigger cascade mode. The metastable state simulation circuit simulates cross-clock domain metastable data output scenarios. The technical solution provided in this application complements the CDC simulation method in the DV design verification environment, effectively identifying potential problems in the design under test under CDC scenarios in the early stages of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the chip development process.

An embodiment of the present invention provides a chip reset verification method, device and equipment supporting multiple spatial domains. The method includes: in a verification platform, encapsulating an independent and reusable general verification component for a reset signal; during simulation, driving the reset signal to the reset signal input port of a design under test in the reset_phase stage to reset the design under test, and monitoring the state of the reset signal by using a verification component related to the reset signal; jumping back to the reset_phase stage when the simulation is about to end; using a factory overloading mechanism to overload and replace the verification platform, so that after jumping back to the reset_phase, restarting the execution of a random test sequence; obtaining the actual response of the design under test to the random test sequence, and comparing the actual response with a predicted response to verify the reset function of the design under test. The present invention solves the problem of reset scenario testing for multiple clocks and their corresponding reset spatial domains that may exist in a DUT.

This invention proposes a cloud native method and system for FPGA-based hardware logic emulation, including: building a hardware logic emulation platform based on a loosely coupled FPGA cluster, and partitioning each FPGA node into a static logic region and a plurality of dynamic logic regions. Specifically, with a custom design tool, such an FPGA-based emulation platform obtains multiple cloud tenants'hardware logic Design Under Tests (DUTs) wraps an emulation control circuit to each DUT. Then FPGA configuration bitstream files that are deployable in each dynamic logic region are generated with the toolset. An emulation software is also employed on a tightly coupled general-purpose microprocessor in each FPGA node to control emulation operation of the DUT and to receive circuit status of DUTs in each dynamic logic region as emulation results for each tenant.

Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

The present invention relates to the technical field of chip verification, and in particular to a chip system-level verification system based on the Python language, including: a preset Python script set in a first verification module, and a design under test set in a second verification module; the preset Python script sets the first verification module as the master device party and the second verification module as the slave device party; the first verification module generates a main thread of the Python script, sends a command to start the verification platform simulation thread to the second verification module, starts the verification platform simulation thread, and establishes a connection between the main thread of the Python script and the verification platform simulation thread; the main thread of the Python script controls the first verification module to send a verification request command to the second verification module, and the verification platform simulation thread controls the second verification module to process the verification request command. The present invention simplifies the chip system-level verification process, improves the verification efficiency, and reduces the verification cost.

A method to generate a hardware design for an electronic device wherein a digital hardware design under test (DUT) for the electronic device is received in a test environment, the digital hardware DUT having an input with a connected buffer; receiving assertions relating to the digital hardware DUT and the buffer; inputting watched data into the buffer; using a state machine to verify the assertions; detecting a deadlock or livelock in the digital hardware DUT in dependence on the verification; and in response to detecting a deadlock or livelock in the digital hardware, providing an output indicative of a deadlock or livelock state detected in the digital hardware DUT. The method may be used in simulation verification or formal verification, e.g. dynamic simulation, particularly for system-on-chip (SoC) designs where computing elements are connected by a fabric or a bus. The DUT may be a high-level language description of a component of a SoC. The buffer may be part of the DUT or a test bench and the watched data may be symbolic data. Assertions may be provided in SystemVerilog Assertions (SVA), Property Specification Language (PSL) or Open Verification Language (OVL). The state machines may be finite state machines (FSM).

The invention relates to the technical field of chip verification, and discloses a to-be-tested design verification method, a verification environment building method, a verification environment and a chip verification device. The verification method comprises the steps that under the condition that a test excitation identifier is received, a target configuration file corresponding to the test excitation identifier is acquired through an excitation generation component; performing parameter analysis on the target configuration file through an analysis component to obtain a target configuration parameter set; and generating a test data packet based on the target configuration parameter set through the excitation generation component, and storing the test data packet to the memory model component, so that the to-be-tested design can use the test data packet to perform verification. Therefore, the target configuration parameter set corresponding to the test excitation is dynamically loaded by utilizing the excitation generation component, and the configuration parameters are stripped from the logic of hard generation excitation codes, so that the verification efficiency of the to-be-tested design is greatly improved.

An apparatus to facilitate floating point compliance verification is disclosed. The apparatus includes processing circuitry to load a design under test (DUT) into a formal equivalence checking tool; define a floating point (FP) component of interest of the DUT; based on the DUT and a reference specification, produce a set of verification properties for the FP component of interest, wherein the set of verification properties is generated for each flag having no freedom, each flag having freedom, for output data having multiple allowable outputs, and for output data having infinitely precise results; check the generated set of verification properties at the formal equivalence checking tool using the DUT and the reference specification; and generate a verification properties report at a conclusion of running the formal equivalence checking tool to detail the set of verification properties.

According to the chip verification system, the chip verification method and the related equipment, in the chip verification system, the verification environments of a plurality of first tested designs are integrated into the first verification environment, and compared with the mode that the corresponding verification environments are set for the plurality of first tested designs, the number of the verification environments can be reduced, and the verification efficiency is improved. Therefore, the integration difficulty between verification environments can be reduced, and the management and debugging difficulty can be reduced. Moreover, a first interconnection assembly located in the first verification environment or the second verification environment realizes the connection between the first tested design and the second test through the first application program interface, and a second interconnection assembly located in the first verification environment or the second verification environment realizes the connection between the first tested design and the second test through the second application program interface. The connection between the first reference model and the second reference model is realized through the second application program interface, so that the communication overhead between the first verification environment and the second verification environment is reduced, and the simulation verification efficiency is improved.