46 results about "Design under test" patented technology

A method for data center switching fabric path emulation in an electronics design automation (EDA) environment includes generating emulated data center traffic. The method further includes, at a path emulation element, modifying the emulated data center traffic to emulate passing of the emulated data center traffic through a data center switching fabric. The method further includes outputting, by the path emulation element, the modified emulated data center traffic to an EDA emulator emulating an electronics design under test. The method further includes receiving and storing a response of electronics design under test to the modified emulated data center traffic.

The invention discloses a software and hardware co-simulation field recovery method and device, equipment and a medium. Comprising the steps of defining a recording starting point and a storage time point of a simulation site; from the recording starting point to the storage time point, capturing transaction flow and causal metadata from the hardware simulation environment of the simulation site to the software test platform, and meanwhile, storing a state snapshot of the verified design in the hardware simulation environment; and when a recovery instruction is received, performing simulation field recovery based on the transaction flow, the causal metadata and the state snapshot. By defining the time range of data capture, a clear boundary is delimited for subsequent data storage, and pertinence and integrity of data records are ensured. A basis is provided for semantic reconstruction of a software test platform by capturing a transaction flow and causal metadata, a state snapshot ensures that the verified design hardware state can be accurately restored, and complete storage of recovery data on the two sides of software and hardware is achieved. And the system does not need to be restarted from the starting point during recovery, so that a redundancy initialization process is avoided, and the simulation debugging efficiency is improved.

The embodiment of the invention provides a chip verification method, system and device and a storage medium, a chip comprises a core particle group, the core particle group is formed by coupling a plurality of core particles, and the method comprises the following steps: based on a core particle verification environment, performing a verification test on a to-be-tested designed core particle; after the core particles pass the verification test, a core particle group verification environment is generated, the core particle group verification environment comprises a plurality of core particle verification sub-environments, and the core particle verification sub-environments are obtained based on instantiation of the core particle verification environment; and based on the core particle group verification environment, carrying out verification test on a to-be-tested designed core particle group. According to the chip verification method in the embodiment of the invention, complete verification of the core particle group can be realized.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

The invention provides a USB measurement and control system collaborative verification platform building method based on the combination of System Verilog and a C language, and relates to the technical field of FPGA testing, the method is based on a Cadence IES simulation environment to build a verification platform of a layered tree topology architecture, the verification platform is independent of a tested design project file, a three-level system structure is adopted, and the verification platform is provided with a three-level architecture; the rtl design layer is used for storing a source code file of a to-be-tested USB measurement and control system baseband processing FPGA (Field Programmable Gate Array) described by adopting a register transmission level; and the tb test platform layer adopts a modular design and comprises a dutif interface definition module, a dutrap design packaging module, a tb test control module and a tbtop top layer integration module. According to the USB measurement and control system collaborative verification platform building method based on the combination of the System Verilog and the C language, intelligent generation of a verification environment is achieved through an automatic script, and the configuration complexity is remarkably reduced; and a parameterized configuration mechanism is adopted, so that different types of USB measurement and control systems can be quickly adapted, and excellent adaptability is shown.

This application relates to the field of chip verification technology, and in particular to a method for constructing a verification platform for flexible GPU interconnection. It includes: obtaining a topology information description file; the topology information description file includes interconnection information of several topologies and topology information of each design under test (DUT) included in each topology; the DUT is a functional module in the GPU that is interconnected with external systems; instantiating the DUT according to the topology information description file; constructing a verification environment in the test platform that matches the topology in the topology information description file according to a dynamic configuration file; the dynamic configuration file is obtained by parsing the topology information description file; and implementing connections between DUTs and between the DUTs and the verification environment according to the dynamic configuration file. This invention can solve the problems of existing methods, such as fixed verification environment structure, insufficient reusability and scalability, and difficulty in supporting verification of multiple types of DUTs and various interconnection topologies and interconnection modes.

The invention relates to the technical field of nonvolatile memory chips, and discloses a verification method and device for a FLASH memory and a universal verification platform, and the simulation verification method comprises the steps: carrying out the modeling of a signal time sequence in the form of an executable task of a hardware description language based on the time sequence requirement of an operation manual of a target FLASH memory, defining a key time interval between the signals as a configurable parameter; performing parameter configuration on the executable task and the key time interval according to a parameter value input by a user for adapting to the target FLASH memory; according to the configured executable task and the key time interval, generating simulation data, and according to the simulation data, simulating the to-be-tested design of the target FLASH memory model; in the simulation process, a time sequence signal, a voltage signal and a decoding logic signal in a to-be-tested design are checked according to parameterized time sequence requirements. According to the invention, the accuracy and efficiency during simulation verification can be improved.

The present application relates to the technical field of chip verification, and more particularly to a verification system based on a shared register address, comprising: a design under test including a plurality of register groups; a register model for generating register access request information and sending it to an adapter; the adapter for decoding a target logical address, obtaining target PFVF information and a target register address, and generating target transaction information and sending it to a bus agent module; the bus agent module for driving the design under test based on the target transaction information; the design under test is also used to determine a target register group based on the target register address, determine a target register in the target register group based on the target PFVF information, and then execute target access information based on the target register. The present application can be applied to verification of a shared register address, simplifies the verification environment, and improves the efficiency and accuracy of verification.

This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastable states cannot be simulated in EMU simulation verification environments before chip design. This application adds a metastable state simulation circuit after the trigger synchronization circuit constructed based on a multi-level trigger cascade mode. The metastable state simulation circuit simulates cross-clock domain metastable data output scenarios. The technical solution provided in this application complements the CDC simulation method in the DV design verification environment, effectively identifying potential problems in the design under test under CDC scenarios in the early stages of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the chip development process.

This invention proposes a cloud native method and system for FPGA-based hardware logic emulation, including: building a hardware logic emulation platform based on a loosely coupled FPGA cluster, and partitioning each FPGA node into a static logic region and a plurality of dynamic logic regions. Specifically, with a custom design tool, such an FPGA-based emulation platform obtains multiple cloud tenants'hardware logic Design Under Tests (DUTs) wraps an emulation control circuit to each DUT. Then FPGA configuration bitstream files that are deployable in each dynamic logic region are generated with the toolset. An emulation software is also employed on a tightly coupled general-purpose microprocessor in each FPGA node to control emulation operation of the DUT and to receive circuit status of DUTs in each dynamic logic region as emulation results for each tenant.

According to the chip verification system, the chip verification method and the related equipment, in the chip verification system, the verification environments of a plurality of first tested designs are integrated into the first verification environment, and compared with the mode that the corresponding verification environments are set for the plurality of first tested designs, the number of the verification environments can be reduced, and the verification efficiency is improved. Therefore, the integration difficulty between verification environments can be reduced, and the management and debugging difficulty can be reduced. Moreover, a first interconnection assembly located in the first verification environment or the second verification environment realizes the connection between the first tested design and the second test through the first application program interface, and a second interconnection assembly located in the first verification environment or the second verification environment realizes the connection between the first tested design and the second test through the second application program interface. The connection between the first reference model and the second reference model is realized through the second application program interface, so that the communication overhead between the first verification environment and the second verification environment is reduced, and the simulation verification efficiency is improved.

The present disclosure provides a verification system, a verification method, an electronic device and a storage medium. The verification system includes a simulation verification device, a first portion and a second portion. The first portion includes a first master module and a second slave module. The second slave module includes a memory unit connected to a memory access interface at a periphery of a design under test. The second portion includes a first direct programming interface, a second direct programming interface, a function library module, and a test case module. The first direct programming interface communicates with the first master module and is configured to call a first function to implement front door access to a register of the design under test. The second direct programming interface communicates with the memory unit and is configured to call a second function to implement back door access to the memory unit.

This invention relates to the field of chip technology, and more particularly to a method, electronic device, and medium for automatically generating chip event statistics modules. The method includes: step S1, setting target event statistics module generation information according to a preset data structure; step S2, generating a target event statistics module architecture based on the design under test (DUT) identifier and the number of counters corresponding to the target event statistics module; step S3, generating a control module and a functional module based on the signal parameter list corresponding to the target event statistics module, generating control signals between the control module and the target event statistics architecture, generating functional signals between the functional modules and the target event statistics architecture, and generating event signals between the target event statistics architecture and the DUT, thereby generating a complete target event statistics module. This invention reduces the cost of generating chip event statistics modules and improves the efficiency and accuracy of generating chip event statistics modules.

The invention discloses a chip verification method and device, and relates to the technical field of integrated circuit design verification. The method comprises the following steps: determining an environment data class and an environment configuration class in a current verification environment; determining a reference algorithm class corresponding to the environment configuration class from algorithm classes of a pre-constructed transaction-level algorithm library according to the environment configuration class, and instantiating the reference algorithm class to obtain a reference model; constructing a reference model system comprising a reference model based on a common interface of a reference algorithm class and an object handle declared by the common interface; obtaining an environment data class and an environment configuration class through a model input agent of the reference model system, determining input of a reference model and a to-be-tested design, and obtaining final reference output of the reference model system and final test output of the to-be-tested design; and comparing the final reference output with the final test output to verify the chip. According to the embodiment, cross-level verification multiplexing can be realized, and the reusability and transportability of the reference model are improved.

This disclosure provides a method and system for large-scale model-assisted logic function simulation and verification for hardware design, relating to the fields of artificial intelligence and hardware design technology. The method includes: performing logical perception analysis on hardware design specifications to generate a structured design analysis report; based on the design analysis report and design specifications, using a generator agent to initially generate a testbench, obtaining an initial test platform and a reference design under test set; simulating the initial test platform and the reference design under test set, and verifying the initial test platform using a consensus verification mechanism based on confidence levels; iteratively refining the test platform using a corrector agent based on a structured reflection report to obtain the final optimal test platform; and automatically generating a retrieval knowledge base precisely aligned with hardware semantics using a reflexive domain knowledge mining method, achieving fully automated construction of the hardware domain knowledge base. This disclosure achieves fully automated system-level hardware design testbench generation and verification.

The application discloses a method for modifying RTL source code files and an electronic device, the method comprising: obtaining all RTL source code files of a design under test and a file name of a top RTL source code of the design under test, associating instantiation names of each module in each RTL source code file with the file name, and saving the association result as a tree type data structure; obtaining all signal names corresponding to each module in each RTL source code file one by one, and position information of each RTL source code file corresponding to the data structure, adding a prefix before the signal name to obtain a complete signal name according to the position information; selecting at least one signal to be observed from all complete signals, detecting each signal to be observed in a list of signals to be observed one by one to obtain a detection result, and modifying the RTL source code file corresponding to the signal to be observed based on the detection result. The application solves the technical problem of low efficiency of adaptive modification of a design under test in the prior art.

The application relates to the technical field of chip verification, in particular to a cross-domain verification bridging system for system-level chip verification, which comprises a configuration file acquisition module, a server, a transaction-level protocol transmitter and a client. The configuration file acquisition module is used for acquiring a configuration file. The server is used for connecting a corresponding target client based on the configuration file, adapting a corresponding target transaction-level protocol transmitter for the target client, receiving a request of the target client, distributing the request to the corresponding target transaction-level protocol transmitter, returning a response of the target transaction-level protocol transmitter to the target client, accessing a design under test based on the corresponding request, and receiving a response of the design under test. The client is used for generating and running an application program, a driver program or a test case, and sending a request to the server by calling a corresponding preset application programming interface. The application reduces the complexity of cross-domain verification of system-level chip verification and improves the cross-domain verification efficiency of system-level chip verification.

The application relates to the technical field of integrated circuits and provides a management method of a verification platform, an electronic device, a medium, a verification method and a platform. The method comprises determining a test requirement associated with a design under test, setting configurable parameters of a plurality of function modules of the verification platform based on the requirement, and setting verification rules included in a layered verifier of the verification platform, so that adaptation for the design under test is realized. Not only can customized service support be provided for specific interface test requirements, but also the complexity and workload of maintenance of the verification stage of the full life cycle of chip development from the early stage to the middle and late stages are effectively reduced. In addition, the verification efficiency is improved and the verification time is shortened, and quick response and cost reduction are supported, for complex and changeable chip IP verification requirements in different development stages, different communication protocols and interface standards, different interface test requirements and different customized requirements.

The invention provides a soft reset verification method, a logic device and data processing equipment, when a message ending signal of a tested design is monitored, an ideal model is triggered to start a processing flow, and when it is monitored that soft reset is completed, a global variable is set. And under the condition that the ideal model is triggered, obtaining the message data from the specified address and caching the message data. And if the global variable is not in the set state, the cached message data is used as expected message data to be sent to a comparator, and the comparator compares actual message data obtained from the detected and identified data with the expected message data to obtain a comparison result. And if the global variable is in the set state, the ideal model stops sending the message data to the comparator, and clears the cached message data and descriptors. According to the scheme, data comparison failure is avoided by establishing time sequence synchronization between the ideal model and the tested equipment, and a cache clearing mechanism is executed after soft reset is finished, so that a single test case can support multiple soft reset operations.

The application provides an AXI interconnection module verification platform and electronic equipment, and relates to the chip verification technical field. The AXI interconnection module verification platform comprises a test module, an interface module, a test case configuration module and a transmission transaction router. The test module comprises an agent cluster, a score board unit, a parameter configuration unit and a virtual sequence transmitter. The interface in the interface module is used for connecting a design under test and each agent in the agent cluster. The test case configuration module is used for generating corresponding test cases. The transmission transaction router is used for distributing a request transaction or a response transaction sent or received by the agent to a score board in the score board unit. Thus, the AXI interconnection module verification platform in the application realizes flexible adaptation to a complex topology structure, and effectively solves the verification challenge caused by the complexity of the AXI interconnection module.

The invention provides a conflict verification method, device and equipment based on transaction life cycle phase perception, and relates to the technical field of computers, and the method comprises the steps: obtaining transaction time sequence phase tracking data of a target transaction request in a to-be-tested design; wherein the transaction time sequence phase tracking data carries a timestamp and a phase label corresponding to a transaction life cycle phase; determining a target conflict strategy from a preset conflict strategy set based on the phase label and the timestamp; wherein the target conflict strategy corresponds to a conflict sensitive point subsequent to the current transaction life cycle phase; and generating a conflict transaction request sequence according to the target conflict strategy, and sending the conflict transaction request sequence to the to-be-tested design for verification. By adopting the method, the conflict scene verification coverage can be improved, the problems of test space explosion and effective sequence constraint loss are solved, and the verification efficiency and the convergence speed are improved.

The invention relates to the technical field of chip verification, in particular to a verification system based on a common register address, comprising: a to-be-tested design comprising a plurality of register groups; the register model is used for generating register access request information and sending the register access request information to the adapter; the adapter is used for decoding the target logic address, obtaining target PFVF information and a target register address, generating target transaction information and sending the target transaction information to the bus agent module; the bus agent module is used for driving the to-be-tested design based on target transaction information; the to-be-tested design is further used for determining a target register group based on the target register address, determining a target register in the target register group based on the target PFVF information, and then executing the target access information based on the target register. The method and device can be suitable for verification of the shared register address, the verification environment is simplified, and the verification efficiency and accuracy are improved.

This invention relates to the field of chip technology, and more particularly to a method, electronic device, and medium for querying connection relationships based on a netlist hierarchy. The method includes: S1, obtaining instance objects A1 of a first target port in the Design Under Test (DUT) and instance objects A2 of a second target port in the DUT; S2, determining whether candidate connection paths for A1 and A2 exist in the DUT; if they exist, proceeding to S3; otherwise, proceeding to S6; S3, generating L... x The set of candidate port groups; Step S4, if L x Each corresponding group (P) i x Q i x In M i x If a connected path exists between the first target port and P1, then execute S5; otherwise, execute S6. Step S5: If the first target port and P1... x Connected and the second target port and Q g(x) x If the network is connected, a connected path is generated; otherwise, proceed to step S6. Step S6: Determine if no connected path exists. This invention improves the efficiency of querying connection relationships in a netlist.

The application relates to the technical field of integrated circuits and provides a verification platform, a verification method, electronic equipment and a medium. The verification platform comprises: an application layer bus function level model, which comprises a customized interface for a design under test for interaction with the design under test, wherein the design under test is a PCIe protocol interface and protocol compliance test suite, the PCIe protocol interface and protocol compliance test suite supports verification requirements of a physical layer intellectual property core and supports verification requirements of PCIe controller plus physical layer subsystem level protocol consistency; and the design under test interacts with the application layer bus function level model through the customized interface. In this way, the integration and through-flow debugging cost of subsystem protocol consistency verification is reduced, the verification period of PCIe subsystem protocol standardization interface testing is shortened, and the completeness of PCIe subsystem full-quantization protocol interface verification and the platform reuse efficiency are improved.

Provided in the embodiments of the present application are a synchronization control method and apparatus, and an electronic device and a readable storage medium. The method comprises: controlling a design under test to execute a test program, and determining the number of executed instructions of the said design; when said design satisfies a first trigger condition of an instruction submission event, on the basis of the number of executed instructions of said design, driving a reference model to execute the same number of instructions; when said design satisfies a second trigger condition of a synchronization event, interrupting the operation of said design, and acquiring first state information of said design; and on the basis of the first state information, updating second state information of the reference model, so as to perform state synchronization between said design and the reference model.

This invention discloses a method, apparatus, and device for verifying debugging functions on a hardware-accelerated simulation platform, relating to the field of simulation testing and verification. The method includes deploying the Design Under Test (DUT) and an Embedded Debug Execution Unit (MCU) on the EMU, loading and executing a debugging program on the MCU to generate a debugging command sequence; converting the debugging command sequence into timing drive signals corresponding to the DUT's test interface specification for debugging or tracing interaction with the DUT, obtaining response information, status information, and tracing information returned by the DUT; comparing the DUT's returned information with the target result, and continuing EMU debugging and verification based on the comparison result. This application enables automated debugging and verification without relying on an external physical debugger.

The present application relates to the technical field of chip verification, and particularly relates to a hardware acceleration simulation offline debugging method, an electronic device and a medium, which comprises the following steps: setting a unique corresponding synthesizable monitor for each synthesizable design under test in a hardware acceleration simulation system; a target design under test performs hardware acceleration simulation, a target monitor acquires each simulation data of the target design under test and a time stamp corresponding to each simulation data, and stores the simulation data in a target memory database in chronological order; generating a target file database corresponding to the target design under test based on the target memory database; isolating the target design under test corresponding to the target design under test in the chip verification simulation system and a target test platform, inputting the simulation data in the target file database into the target test platform in chronological order of the corresponding time stamps, and performing hardware acceleration simulation offline debugging based on the output result of the target test platform. The present application improves the debugging efficiency of hardware acceleration simulation.

The application is suitable for the field of electronic design automation, and provides a chip verification method, device and equipment based on UVM and a storage medium, wherein the method comprises the following steps: encapsulating hardware interface layer code related to low-level design under test in a test platform in a low-level verification environment into a packaging module; encapsulating entire UVM environment components used for verifying the low-level design under test into a UVM package, and setting environment starting code associated with the UVM package in the packaging module; in a high-level verification environment, binding the packaging module to a design under test instance corresponding to the low-level design under test in a high-level design under test; and instantiating the packaging module in a test platform under the high-level verification environment, accessing the UVM package by the environment starting code to construct a low-level UVM environment, and verifying the design under test instance. The scheme improves the reuse and ease of use of the verification environment, and reduces the additional coding and integration cost.

This application relates to a read / write cache verification method, an electronic device, a computer-readable storage medium, and a program product. The method includes: acquiring the request-response result corresponding to an input request generated by the design under test (DUT) module in each clock cycle according to a preset hardware description language; acquiring the response reference result corresponding to the input request output by a white-box model in each clock cycle according to the hardware description language; sequentially comparing the request-response result and the response reference result in each clock cycle to obtain a white-box verification result; acquiring the output reference result corresponding to the input request output by a black-box model based on a preset read / write cache logic; acquiring the request processing result corresponding to the input request output by the DUT module, comparing the request processing result with the output reference result to obtain a black-box verification result; and comparing the white-box verification result with the black-box verification result to obtain the read / write cache verification result of the DUT module. This method can improve the verification correctness.

This application provides a chip functional verification method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: decomposing the design under test (DUT) into multiple first sub-modules; and decomposing a reference model of the DUT into multiple second sub-modules corresponding to the functions of the first sub-modules; simultaneously using the output of the current first sub-module as the input of the next first sub-module downstream of the data stream and the input of the second sub-module corresponding to the next first sub-module; and determining the functional verification result of the DUT based on the comparison results of the outputs of each first sub-module and the corresponding second sub-modules. The method and apparatus provided in this application synchronously decompose the DUT and the reference model and establish a co-simulation mechanism that drives the reference model execution using hardware simulation results. This can quickly and accurately locate chip design defects, improving chip verification efficiency and debugging convenience.