Chip atomic property verification system, method, device and storage medium

Abstract

The application discloses a kind of chip atomic characteristic verification system, method, device and storage medium, it is related to chip design and chip test field, the system includes: atomic characteristic excitation device is used to send random excitation signal to atomic test model device and chip design under test;Atomic test model device is used to obtain the expected output data corresponding to random excitation signal;Output monitoring device is used to obtain the actual output data of chip design under test for random excitation signal;Function result comparison device is used to obtain the function verification result of chip design under test according to actual output data and expected output data;Behavior consistent monitoring device is used to concurrently obtain the behavior consistency verification result of chip design under test.The technical scheme of the embodiment of the application simultaneously obtains the function verification result and the behavior consistency verification result by parallel monitoring mode, not only improves test efficiency, and ensures the comprehensiveness of atomic characteristic verification result of chip.

Description

Technical Field

[0001] This invention relates to the fields of chip design and chip testing, and in particular to a chip atomic characteristic verification system, method, apparatus and storage medium. Background Technology

[0002] During chip development, the supported atomic semantics and data types change continuously with design requirements, and the atomic emitters of each generation of chips are also different. This leads to a significant increase in the scope and complexity of atomic characteristic verification.

[0003] Atomic characteristics refer to the behavioral attributes of the smallest indivisible and uninterruptible functional unit within a System-on-Chip (SOC), which is also the smallest unit in the verification process. Examples include atomic instructions at the processor instruction level (compare-and-swap, addition, and AND operations); bus protocol level (bus-locked transmission, exclusive access transaction sequences, and monitoring units); and atomic modification operations of register bit fields. Existing chip atomic characteristic verification schemes typically involve manually constructing test cases for multiple scenarios, verifying each atomic characteristic sequentially based on these test cases, and recording the verification results. After completing the tests for each test case, all atomic characteristic verification results are summarized as the final verification result for the current chip.

[0004] However, this method of verifying atomic characteristics is not only inefficient, but also results in a one-sided view, failing to fully verify the atomic characteristics of the chip. Furthermore, the test results have a large error compared to the test results under complex loads in actual applications, and cannot reflect the true atomic characteristics of the chip. Summary of the Invention

[0005] This invention provides a chip atomic characteristic verification system, method, apparatus, storage medium, and computer program product to solve the problems of low testing efficiency and one-sidedness in atomic characteristic verification results.

[0006] According to another aspect of the present invention, a chip atomic characteristic verification system is provided, comprising: an atomic characteristic excitation device, an atomic test model device, a functional result comparison device, a behavior consistency monitoring device, and an output monitoring device; The atomic characteristic excitation device is connected to the atomic test model device and the chip design under test, and is used to send at least one random excitation signal to the atomic test model device and the chip design under test according to at least one test case in the test case set; The atomic testing model device is used to acquire the expected output data corresponding to the at least one random excitation signal; The output monitoring device is connected to the chip design under test and is used to acquire the actual output data of the chip design under test in response to the at least one random excitation signal. The functional result comparison device is connected to the atomic test model device and the output monitoring device, and is used to obtain the functional verification results of the chip design under test based on the actual output data and the expected output data. The behavior consistency monitoring device is used to concurrently monitor whether the interactive behavior of the chip design under test meets preset constraints, so as to obtain the behavior consistency verification result of the chip design under test.

[0007] According to another aspect of the present invention, a chip atomic characteristic verification method is provided, applied to the chip atomic characteristic verification system described in any embodiment of the present invention, comprising: The atomic characteristic excitation device sends at least one random excitation signal to the atomic test model device and the chip design under test according to at least one test case in the test case set; The atomic testing model device acquires the expected output data corresponding to the at least one random excitation signal; The output monitoring device acquires the actual output data of the chip design under test in response to the at least one random excitation signal; The functional result comparison device obtains the functional verification results of the chip design under test based on the actual output data and the expected output data. The behavior consistency monitoring device concurrently monitors whether the interactive behavior of the chip design under test meets preset constraints in order to obtain the behavior consistency verification results of the chip design under test.

[0008] According to another aspect of the present invention, a chip atomic characteristic verification apparatus is provided, applied to the chip atomic characteristic verification system described in any embodiment of the present invention, comprising: The test case acquisition module, configured in the atomic characteristic excitation device, is used to send at least one random excitation signal to the atomic test model device and the chip design under test based on at least one test case in the test case set; The expected output acquisition module, configured in the atomic test model device, is used to acquire the expected output data corresponding to the at least one random excitation signal; An actual output acquisition module, configured in the output monitoring device, is used to acquire the actual output data of the chip design under test in response to the at least one random excitation signal; A functional verification execution module, configured in the functional result comparison device, is used to obtain the functional verification result of the chip design under test based on the actual output data and the expected output data. The behavior consistency verification execution module is configured in the behavior consistency monitoring device and is used to concurrently monitor whether the interactive behavior of the chip design under test meets the preset constraints in order to obtain the behavior consistency verification result of the chip design under test.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the chip atomic characteristic verification method according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the chip atomic characteristic verification method described in any embodiment of the present invention.

[0011] The technical solution of this invention provides a chip atomic characteristic verification system comprising an atomic characteristic excitation device, an atomic test model device, a functional result comparison device, a behavior consistency monitoring device, and an output monitoring device. The atomic characteristic excitation device sends at least one random excitation signal to the atomic test model device and the chip design under test (DUT) based on at least one test case from a test case set. The atomic test model device acquires the expected output data corresponding to the at least one random excitation signal. The output monitoring device acquires the actual output data of the DUT in response to the at least one random excitation signal. The functional result comparison device acquires the functional verification result of the DUT based on the actual output data and the expected output data. The behavior consistency monitoring device concurrently monitors whether the interactive behavior of the DUT conforms to preset constraints to acquire the behavior consistency verification result of the DUT. Thus, by using parallel monitoring, both the functional verification result and the behavior consistency verification result of the chip's atomic characteristics are acquired simultaneously, improving testing efficiency and providing a comprehensive verification of the chip's atomic characteristics, avoiding the bias of atomic characteristic verification results. Furthermore, when multiple random excitation signals are emitted simultaneously, the verification results reflect the true atomic characteristics under complex loads in actual applications, improving the accuracy of the verification results.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a chip atomic characteristic verification system provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of another chip atomic characteristic verification system provided in Embodiment 2 of the present invention; Figure 3 This is a flowchart of the chip atomic characteristic verification method performed by the chip atomic characteristic verification system provided in Embodiment 3 of the present invention; Figure 4 This is a flowchart of a chip atomic characteristic verification method provided in Embodiment 4 of the present invention; Figure 5 This is a schematic diagram of a chip atomic characteristic verification device provided in Embodiment 5 of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1 Figure 1This is a schematic diagram of a chip atomic characteristic verification system provided in Embodiment 1 of the present invention. The system includes: an atomic characteristic excitation device 110, an atomic test model device 120, a functional result comparison device 130, a behavior consistency monitoring device 140, and an output monitoring device 160. The atomic characteristic excitation device 110 is connected to the atomic test model device 120 and the chip design under test 150, and is used to send at least one random excitation signal to the atomic test model device 120 and the chip design under test 150 according to at least one test case in the test case set. The atomic test model device 120 is used to obtain the expected output data corresponding to the at least one random excitation signal. The output monitoring device 160 is connected to the chip design under test 150 and is used to obtain the actual output data of the chip design under test 150 in response to the at least one random excitation signal.

[0018] Specifically, the test case set is a collection of test cases under different atomic characteristic test scenarios. Different test cases verify different atomic characteristics of the chip. If it is necessary to verify the target atomic characteristic of the chip, the target test case matching the target atomic characteristic is selected from the test case set. When each test case is constructed, it is based on the operation type and data type adapted under the atomic characteristic, and the test stimulus signal (i.e., random stimulus signal) is generated in the form of random operation type and random data type. The random stimulus signal in the test case can be obtained directly, or it can be obtained by parsing through existing parsing tools.

[0019] The test cases record the identifier and address of the atomic emitter that emits random excitation signals; among them, the atomic emitter, as the core hardware module in the chip that implements a specific function, is matched one-to-one with the atomic characteristics, that is, each atomic emitter is used to verify the emission of a random excitation signal for a certain atomic characteristic; the atomic characteristic excitation device 110, according to the identifier and address of the atomic emitter recorded in the test cases, sends the random excitation signal to the atomic test model device 120 and the chip design under test 150 through the target atomic emitter.

[0020] The Design Under Test (DUT) 150 refers to a chip system that has been designed but not yet verified during chip development, i.e., the actual hardware design to be verified. After receiving a random stimulus signal, it will output the actual data after actual operation (i.e., the actual output data). For the DUT 150, it is necessary to verify whether its functions, performance, timing, etc., meet the expected specifications through a configured test plan. After receiving a random stimulus signal, the actual output data of the DUT 150 will enter the output monitoring device 160, i.e., the output monitoring device 160 will complete the reception and acquisition of the actual output data. The atomic test model device 120 is a standard model pre-generated according to the chip design requirements and chip test requirements, used to generate the expected output data (i.e., the standard output result) of the random stimulus signal.

[0021] The functional result comparison device 130, connected to the atomic test model device 120 and the output monitoring device 160, is used to obtain the functional verification result of the chip design under test 150 based on the actual output data and the expected output data. If the actual output data is consistent with the expected output data, it indicates that the hardware function of the chip design under test 150 is correct under the current atomic characteristic test scenario, and also indicates that the current atomic characteristic of the chip design under test 150 has passed the functional verification; if the actual output data is inconsistent with the expected output data, it indicates that the hardware function of the chip design under test 150 is incorrect under the current atomic characteristic test scenario, and also indicates that the current atomic characteristic of the chip design under test 150 has failed the functional verification.

[0022] The behavior consistency monitoring device 140 is used to concurrently monitor whether the interactive behavior of the chip design under test 150 meets preset constraints, so as to obtain the behavior consistency verification result of the chip design under test 150. The behavior consistency monitoring device 140 monitors all interactive behaviors during the verification and testing process of the chip design under test 150, and performs them concurrently with the above-mentioned functional verification without affecting the execution of the functional verification; it specifically checks whether the interactive behavior of the chip design under test 150 meets preset constraints, such as whether it meets bus protocol specifications, timing requirements, and resource access rules; if any interactive behavior does not meet the preset constraints, even if the functional verification is passed, it may still cause system crashes in extreme scenarios. Therefore, the verification of the atomic characteristics of a chip actually includes two parts: functional verification and process compliance verification (i.e., behavioral consistency verification). In this way, while realizing the functional verification of the computing unit and the operation unit, the hidden problems of correct results but abnormal process are discovered in a timely manner through process compliance verification, avoiding the occurrence of extreme scenarios that could lead to system crashes. At the same time, behavioral monitoring and functional verification are carried out concurrently without adding extra testing time, which greatly improves the atomic characteristic verification efficiency of the chip design under test 150.

[0023] Specifically, the atomic characteristic excitation device 110 can simultaneously send different random excitation signals to the atomic test model device 120 and the chip design under test 150 through different atomic emitters, based on multiple test cases in the test case set. This allows the chip design under test 150 to generate actual output data for different random excitation signals, while the atomic test model device 120 also acquires the expected output data corresponding to each random excitation signal. The functional result comparison device 130 obtains the functional verification results of the chip design under test 150 for different atomic characteristics based on the actual output data and the expected output data. At the same time, the behavior consistency monitoring device 140 concurrently monitors the interactive behavior of the chip design under test 150 for different atomic characteristics to see if they meet their respective preset constraints. This multi-engine concurrent testing scenario more closely resembles the complex workload in actual applications, improving the accuracy of the atomic characteristic verification results.

[0024] The technical solution of this invention provides a chip atomic characteristic verification system comprising an atomic characteristic excitation device, an atomic test model device, a functional result comparison device, a behavior consistency monitoring device, and an output monitoring device. The atomic characteristic excitation device sends at least one random excitation signal to the atomic test model device and the chip design under test (DUT) based on at least one test case from a test case set. The atomic test model device acquires the expected output data corresponding to the at least one random excitation signal. The output monitoring device acquires the actual output data of the DUT in response to the at least one random excitation signal. The functional result comparison device acquires the functional verification result of the DUT based on the actual output data and the expected output data. The behavior consistency monitoring device concurrently monitors whether the interactive behavior of the DUT conforms to preset constraints to acquire the behavior consistency verification result of the DUT. Thus, by using parallel monitoring, both the functional verification result and the behavior consistency verification result of the chip's atomic characteristics are acquired simultaneously, improving testing efficiency and providing a comprehensive verification of the chip's atomic characteristics, avoiding the bias of atomic characteristic verification results. Furthermore, when multiple random excitation signals are emitted simultaneously, the verification results reflect the true atomic characteristics under complex loads in actual applications, improving the accuracy of the verification results.

[0025] Example 2 Figure 2This is a schematic diagram of a chip atomic characteristic verification system provided in Embodiment 2 of the present invention. The chip atomic characteristic verification system also includes a parameter extraction device 200. The parameter extraction device 200 is used to obtain an atomic transmitter list, an atomic data type library, an atomic operation type library, an operation type and data type mapping library, a parameter library, a test scenario configuration list, and a transmitter mapping library based on the verification test requirement document, the atomic characteristic requirement document, the transmitter interface mapping document, and the parameter flow management document.

[0026] Specifically, the verification test requirement document, as a test task list compiled by chip verification personnel based on the chip design requirement document, can be presented in a structured data format (e.g., JSON format). It indicates which functions of the chip need to be verified and what standards the functions to be verified must meet; that is, it defines the goals of chip verification. The atomic characteristic requirement document, as the chip designer lists the most basic atomic characteristics of the chip, such as what mathematical operations (e.g., addition and multiplication) computation unit A supports, and what types of data operation unit B can process, can be presented in tabular or text form, defining the functional basis for chip verification.

[0027] The transmitter interface mapping document defines the mapping relationship between atomic transmitters and verification interfaces. The atomic transmitter is the core hardware module of the function to be verified in the chip. It is used to realize the function to be verified through signals (e.g., stimulus signals). Therefore, verifying a specific function in the chip is actually the process of the atomic transmitter sending stimulus signals through the matched verification interface. The transmitter interface mapping document defines which verification interface each atomic transmitter is matched with. That is, to verify a certain function, which atomic transmitter needs to send a stimulus signal to which verification interface.

[0028] The parameter flow management document defines static configuration parameters and flow control parameters. Static configuration parameters are the basic configuration information for the verification environment, and may include the instance number of the computing unit, the interface number, macro control parameters in the test environment (e.g., macro definitions to distinguish between single-die and dual-die tests), indications of the valid location of atomic response data (to tell the tool which part of the returned data is valid), and the mount file path of the verification interface (to specify the location of the test configuration file), etc. Flow control parameters are the rule switches for the verification process, and may include start / stop control of the behavior consistency monitoring function (e.g., whether to enable real-time monitoring), configuration of constraints related to behavior consistency judgment (e.g., the range of data error considered acceptable), and control switches to adjust the efficiency of verification testing (e.g., whether to skip certain non-critical tests to speed up verification), etc.

[0029] The parameter extraction device 200 first extracts key elements from different documents, including: reading the verification test requirement document and parsing out all atomic characteristics that need to be verified (e.g., 32-bit floating-point addition operation, SPI (Serial Peripheral Interface) data transmission and reception); reading the atomic characteristic requirement document and extracting the specific parameters of each atomic characteristic (e.g., data type, operation type, input and output range, etc.); reading the transmitter interface mapping document and establishing the correspondence between atomic characteristics and verification interfaces; and reading the parameter flow management document and extracting the basic configuration and process control rules of the verification environment.

[0030] Secondly, the extracted key elements are categorized, including: classifying atomic characteristics according to their operation types to generate an atomic operation type library (e.g., arithmetic operation type, logical operation type, interface communication type, etc.). The atomic operation type library defines all the operation behaviors supported by the chip, such as data reading and writing, arithmetic operations, logical operations, protocol transmission and reception, etc. Each operation type includes information such as name, description, input and output parameters, which provides an action list for test behaviors to ensure that the test behaviors conform to the chip's functional definition.

[0031] Based on the data type of atomic characteristics, atomic characteristics are categorized to generate an atomic data type library. This library defines all data formats supported by the chip, such as 8-bit unsigned integers, 32-bit floating-point numbers, Boolean values, and custom structures, serving as the format specification for test data. Each data type includes information such as name, bit width, and value range, providing a format specification for test data and ensuring that the test data meets the chip's requirements.

[0032] A mapping relationship is established between atomic operation types and data types, generating an operation type-data type mapping library. This library defines the data types supported by each operation type; for example, "addition" supports "integers" and "floating-point numbers," and "logical operations" support "Boolean values," to avoid illegal operation combinations and ensure the legality and validity of test cases. A parameter library is generated based on the specific parameters of each atomic characteristic. This parameter library records all static configuration parameters and flow control parameters, such as operation precision requirements, data range, interface timing parameters, and timeout thresholds. It provides configuration details for the test model, ensuring the accuracy and reliability of the tests.

[0033] Obtain all atomic characteristics that need to be verified and generate an atomic emitter list. This list records the set of all atomic characteristics to be tested, with each characteristic corresponding to a unique identifier that specifies all functionalities to be tested and serves as a test checklist for subsequent tests. Based on the mapping relationship between atomic emitters and verification interfaces, generate an emitter mapping library. This library defines the verification interface information for each atomic characteristic, serving as an interface guide for test execution and ensuring that test signals are correctly sent to the chip under test.

[0034] Based on the verification test requirements document and process control parameters, a test scenario configuration list is generated. This list records the specific configurations for each test scenario, such as the test environment, test steps, and verification rules, providing scenario templates for test execution and ensuring test repeatability and scalability. The parameter extraction device 200 then transforms each requirement document into multiple types of structured data, classifies and stores this data, improving the ease of reading the requirement data and enhancing the data processing efficiency of the atomic characteristic excitation device 110, atomic test model device 120, and behavior consistency monitoring device 140.

[0035] Optionally, in this embodiment of the invention, the chip atomic characteristic verification system further includes an operator unit library 300 and an atomic test model generation device 400; the operator unit library 300, connected to the atomic test model generation device 400, is used to store a set of operation units; the atomic test model generation device 400 is used to obtain a target object according to an atomic data type library, an atomic operation type library, and an operation type and data type mapping library; obtain a target operation unit from the operator unit library 300 according to the target object; generate the atomic test model device 120 according to the target object and the target operation unit; and configure the parameters of the atomic test model device 120 through a parameter library; wherein, the target object includes a target operation type and a target data type.

[0036] Specifically, the operator unit library 300 stores the most basic set of arithmetic units at the chip's bottom layer. An arithmetic unit is the smallest unit that performs operations, such as adders, multipliers, logic gates, and data selectors. The atomic test model generation device 400 first obtains the target atomic characteristic to be verified from the test scenario configuration list (e.g., verifying 32-bit floating-point addition). It then obtains the target operation type (e.g., addition) that matches the target atomic characteristic through the atomic operation type library. Next, it determines the target data type that matches the target operation type through the operation type and data type mapping library, and obtains the target data type through the atomic data type library. Finally, it calls the target arithmetic unit that matches the target operation type and target data type from the operator unit library 300.

[0037] After combining the selected target computational units, target data types, and target operation types to generate an atomic test model device, the static parameters of the atomic test model device are configured according to the static configuration parameters in the parameter library. For example, the precision requirement for addition operations is set to "±0.001", and the data range is "-1000 to 1000". Thus, through multiple categorized and stored requirement databases, the atomic test model device 120 is automatically generated, allowing for reuse and expansion of the atomic test model device 120 by simply modifying the construction conditions.

[0038] Optionally, in this embodiment of the invention, the atomic characteristic excitation device 110 further includes multiple random excitation generation devices 111, emission address management devices 112, driver mapping devices 113, and tag library management devices 114; the random excitation generation device 111 is used to generate random operation types through a first random unit and to generate random data types matching the random operation types through a second random unit; wherein, the random excitation generation device 111 is matched one-to-one with the atomic emitters; the random operation types and the random data types are used to generate test cases; the emission address management device 112 is used to obtain the addresses of the atomic emitters; the driver mapping device 113 is used to obtain the identifiers of the atomic emitters; and the tag library management device 114 is used to manage test parameter tags and regression tags.

[0039] Specifically, the atomic characteristic excitation device 110 generates a corresponding number of random excitation generation devices 111 based on each atomic emitter in the atomic emitter list, and the random excitation generation devices 111 are matched one-to-one with the atomic emitters; each random excitation generation device 111 consists of a first random unit and a second random unit; the first random unit generates a random operation type based on the current test scenario, and the second random unit generates a randomly matched data type (i.e., a random data type) based on the data type supported by the random operation type. The random operation type and the random data type are used for the generation of subsequent test cases.

[0040] The transmission address management device 112 generates a continuous address sequence based on the start and end addresses of the current test scenario in the test scenario configuration list. This address sequence is the address of the atomic transmitter. The driver mapping device 113 obtains the corresponding atomic transmitter identifier in the verification environment for sending test excitation signals. The tag library management device 114 manages test-related tags (test parameter tags and regression tags, etc.) and parameters in a unified manner, including recording the specific parameter configuration of each test case and classifying the test cases to facilitate subsequent regression testing.

[0041] Thus, the random operation types and random data types generated by the random stimulus generation device 111 provide a test basis for the automatic generation of test cases, greatly improving test efficiency. At the same time, the multi-module design of the atomic characteristic stimulus device 110 allows each functional module to be adjusted independently, which can meet general test requirements and adapt to specific scenarios. In addition, the tag library management device 114 provides a complete tag management system for the analysis and regression of test results.

[0042] Optionally, in this embodiment of the invention, the chip atomic characteristic verification system further includes a verification interface mounting device 500; the behavior consistency monitoring device 140 specifically includes a monitoring configuration unit 141, an observation information processing unit 142, and a compliance determination unit 143; the verification interface mounting device 500 connects the verification intellectual property core and the chip design under test 150, and is used to guide the verification intellectual property core to verify the interface and protocol of the chip design under test 150; the monitoring configuration unit 141 is used to determine the monitoring object according to the atomic emitter identifier and the verification interface mounting device 500, and establish an observation connection of the monitoring object to obtain observation data through the observation connection; wherein, the monitoring object includes interactive behaviors related to atomic characteristics; the observation information processing unit 142 is used to perform data processing on the observation data to form the input features required for compliance determination; wherein, the data processing includes at least one of sorting, extraction, and transformation; the compliance determination unit 143 is used to compare the input features with the preset constraint conditions to output the behavior consistency determination result.

[0043] Specifically, the Verification IP (VIP) is a pre-designed and rigorously validated reusable hardware module with built-in expertise in various interfaces and protocols, specifically designed to verify the correctness of complex interfaces and protocols in chips (especially system-on-a-chip). The Verification Interface Mounting Device 500 provides a verification channel for the Verification IP and the chip design under test 150, thereby guiding the Verification IP to verify the interfaces and protocols of the chip design under test 150. The Monitoring Configuration Unit 141 first obtains the atomic emitter identifier, for example, from the driver mapping device 113 in the aforementioned atomic characteristic excitation device 110, to obtain the atomic emitter identifier corresponding to this test; then, it combines the connection information in the Verification Interface Mounting Device 500, such as which interface or module to monitor (i.e., the monitoring object), whether the monitoring scope is transmission speed, data accuracy, or response time (i.e., the monitoring range), and from which monitoring points to collect data (i.e., the monitoring point access relationship), thereby establishing an observable connection with the monitoring object.

[0044] The observation information processing unit 142 organizes, extracts, or transforms the observation data obtained by the monitoring configuration unit 141 to form the input features required for compliance determination. Organizing involves removing invalid data, such as sorting by time and removing expired data; extraction involves extracting key indicators, such as transmission rate and error rate; and transformation involves converting the signal data into a more easily judged data format, such as converting binary to decimal. The compliance determination unit 143 compares the input features with preset constraints to output a behavior consistency determination result. If the preset constraints are met, the behavior consistency determination is passed, meaning the behavior consistency verification result is "passed"; if the preset constraints are not met, the behavior consistency determination is failed, meaning the behavior consistency verification result is "failed," and specific discrepancies are output when failure occurs. Thus, standardized behavior consistency monitoring replaces manual judgment, improving verification efficiency and ensuring the accuracy of the verification process.

[0045] Optionally, in this embodiment of the invention, the chip atomic characteristic verification system further includes a basic testing device 600, a heterogeneous configuration device 700, and a test case generation device 800; the basic testing device 600 is used to perform a pre-verification step; wherein the pre-verification step includes at least one of application programming interface initialization, storage controller initialization, benchmark reference configuration, and global clock reset generation; the heterogeneous configuration device 700 is used to provide configuration parameters and test stimuli for other heterogeneous intellectual property cores in the test path; the test case generation device 800 is used to select a matching target random stimulus generation device 111 from the atomic characteristic stimulus device 110 and a matching target heterogeneous intellectual property core from the heterogeneous configuration device 700 based on the test scenario configuration list, so as to generate test cases according to the pre-verification step, the target random stimulus generation device 111, and the target heterogeneous intellectual property core, and add the test cases to the test case set.

[0046] Specifically, the basic test device 600 performs initialization work before verifying the atomic characteristics of the chip. For example, it completes API (Application Programming Interface) initialization to enable the test program to establish communication with the chip hardware; it completes memory controller initialization to ensure that the data read and write path is normal; it sets the chip's baseline reference configuration to put the chip in a standard working state; and it generates a global clock reset signal to start testing the chip from the initial state. All subsequent tests are carried out on this basic configuration to avoid repeating the same preparatory work.

[0047] A system-on-a-chip (SoC) is not a single chip, but rather an integration of multiple small chips with different functions. These small chips with different functions are called heterogeneous intellectual property (IP) cores. Each small chip with different functions has its own independent function and working mode. When the different functions of the chip design under test (DUT) are tested together, it provides parameter configuration and excitation signals to other heterogeneous IP cores to ensure that each link in the entire test path can cooperate with the verification of the current function under test.

[0048] Thus, the basic testing device 600 provides a preliminary verification step for the generation of test cases, the target random stimulus generation device 111 provides the random operation type and random data type required for the generation of test cases, and the heterogeneous configuration device 700 provides a heterogeneous intellectual property core for the test cases to cooperate with the current function under test for complete testing. This ensures the completeness of the test cases generated by the test case generation device 800 and avoids the one-sidedness of the test results.

[0049] The technical solution of this invention realizes the automatic generation of multiple functional devices based on requirements documents, including the automatic generation of atomic characteristic excitation devices, atomic test model devices, and behavior consistency monitoring devices. The atomic characteristic verification method based on atomic characteristic excitation devices, atomic test model devices, and behavior consistency monitoring devices not only improves testing efficiency but also comprehensively verifies the atomic characteristics of the chip, avoiding the one-sidedness of atomic characteristic verification results. Furthermore, it improves the reusability and scalability of the above-mentioned functional devices, further enhancing the functional integrity of the chip atomic characteristic verification system.

[0050] Example 3 Figure 3 This is a flowchart of a chip atomic characteristic verification method performed by a chip atomic characteristic verification system according to Embodiment 3 of the present invention, as shown below. Figure 3 As shown: S301, The parameter extraction device extracts verification requirement information based on various requirement documents.

[0051] The parameter extraction device specifically obtains the atomic emitter list, atomic data type library, atomic operation type library, operation type and data type mapping library, parameter library, test scenario configuration list and emitter mapping library based on the verification test requirement document, atomic characteristic requirement document, emitter interface mapping document and parameter flow management document.

[0052] S302, The atomic test model generation device generates an atomic test model based on the operator unit library and verification requirement information.

[0053] The atomic test model generation device obtains the target operation type and target data type based on the atomic data type library, the atomic operation type library, and the operation type to data type mapping library; obtains the target operation unit from the operator unit library based on the target operation type and target data type; generates the atomic test model device based on the target operation type, target data type, and target operation unit; and configures the parameters of the atomic test model device through the parameter library.

[0054] S303, the atomic characteristic excitation device obtains the random operation type, random data type, transmission address, transmitter identifier and multiple tag information according to the verification requirement information.

[0055] The atomic characteristic excitation device generates random operation types through the first random unit of the random excitation generation device, and generates random data types that match the random operation types through the second random unit of the random excitation generation device; the emission address management device is used to obtain the address of the atomic emitter; the driver mapping device is used to obtain the identifier of the atomic emitter; and the tag library management device is used to manage tag information such as test parameter tags and regression tags.

[0056] S304. The behavior consistency monitoring device determines the monitoring object based on the verification requirement information and the transmitter identifier.

[0057] The monitoring configuration unit in the behavior consistency monitoring device determines the monitoring object based on the atomic emitter identifier and the verification interface mounting device, and establishes an observation connection for the monitoring object in order to obtain observation data through the observation connection.

[0058] S305. The test case generation device generates a set of test cases based on the verification requirement information, basic test device, heterogeneous configuration device, random operation type, and random data type.

[0059] The test case generation device selects a matching target random stimulus generation device from the atomic characteristic stimulus device and a matching target heterogeneous intellectual property core from the heterogeneous configuration device based on the test scenario configuration list. It then generates test cases based on the pre-verification steps of the basic test device, the target random stimulus generation device, and the target heterogeneous intellectual property core, and adds the test cases to the test case set.

[0060] S306. The atomic characteristic excitation device sends random excitation signals to the atomic test model device and the chip design under test according to the test cases in the test case set.

[0061] S307, Output monitoring device acquires the actual output data of the chip under test for random excitation signal.

[0062] S308, the atomic testing model device acquires the expected output data corresponding to the random excitation signal.

[0063] S309. The functional result comparison device obtains the functional verification results of the chip design under test based on the actual output data and the expected output data.

[0064] S310, The behavior consistency monitoring device concurrently monitors whether the interactive behavior of the chip under test meets the preset constraints, so as to obtain the behavior consistency verification results of the chip under test.

[0065] The observation information processing unit in the behavior consistency monitoring device processes the observation data to form the input features required for compliance determination; the compliance determination unit in the behavior consistency monitoring device compares the input features with preset constraints to output the behavior consistency determination result.

[0066] The technical solution of this invention realizes the automatic generation of multiple functional devices based on requirements documents, including the automatic generation of atomic characteristic excitation devices, atomic test model devices, and behavior consistency monitoring devices. The atomic characteristic verification method based on atomic characteristic excitation devices, atomic test model devices, and behavior consistency monitoring devices not only improves testing efficiency but also comprehensively verifies the atomic characteristics of the chip, avoiding the one-sidedness of atomic characteristic verification results. Furthermore, it improves the reusability and scalability of the above-mentioned functional devices, further enhancing the functional integrity of the chip atomic characteristic verification system.

[0067] Example 4 Figure 4 This is a flowchart of a chip atomic characteristic verification method provided in Embodiment 4 of the present invention. This method can be executed by a chip atomic characteristic verification device, which can be implemented in hardware and / or software. This chip atomic characteristic verification device can be configured in any embodiment of the chip atomic characteristic verification system of the present invention. Figure 4 As shown, the method includes: S401, the atomic characteristic excitation device sends at least one random excitation signal to the atomic test model device and the chip design under test according to at least one test case in the test case set.

[0068] S402, The atomic testing model device acquires the expected output data corresponding to the at least one random excitation signal.

[0069] S403, The output monitoring device acquires the actual output data of the chip design under test in response to the at least one random excitation signal.

[0070] S404. The functional result comparison device obtains the functional verification results of the chip design under test based on the actual output data and the expected output data.

[0071] S405. The behavior consistency monitoring device concurrently monitors whether the interactive behavior of the chip design under test meets the preset constraints, so as to obtain the behavior consistency verification result of the chip design under test.

[0072] The technical solution of this invention includes an atomic characteristic excitation device that sends at least one random excitation signal to an atomic test model device and a chip design under test (DUT) based on at least one test case from a test case set; an atomic test model device that acquires expected output data corresponding to at least one random excitation signal; an output monitoring device that acquires actual output data of the chip DUT in response to at least one random excitation signal; a functional result comparison device that acquires the functional verification result of the chip DUT based on the actual output data and expected output data; and a behavior consistency monitoring device that concurrently monitors whether the interactive behavior of the chip DUT meets preset constraints to acquire the behavior consistency verification result of the chip DUT. Thus, by using parallel monitoring, both the functional verification result and the behavior consistency verification result of the chip's atomic characteristics are acquired simultaneously, improving testing efficiency and providing a comprehensive verification of the chip's atomic characteristics, avoiding the one-sidedness of atomic characteristic verification results. Furthermore, when multiple random excitation signals are emitted simultaneously, the verification results reflect the true atomic characteristics under complex loads in actual applications, improving the accuracy of the verification results.

[0073] Example 5 Figure 5 This is a structural block diagram of a chip atomic characteristic verification device provided in Embodiment 5 of the present invention. The device specifically includes: The test case acquisition module 501 is configured in the atomic characteristic excitation device and is used to send at least one random excitation signal to the atomic test model device and the chip design under test according to at least one test case in the test case set. The expected output acquisition module 502 is configured in the atomic test model device and is used to acquire the expected output data corresponding to the at least one random excitation signal; The actual output acquisition module 503 is configured in the output monitoring device and is used to acquire the actual output data of the chip design under test in response to the at least one random excitation signal; The functional verification execution module 504 is configured in the functional result comparison device and is used to obtain the functional verification result of the chip design under test based on the actual output data and the expected output data. The behavior consistency verification execution module 505 is configured in the behavior consistency monitoring device and is used to concurrently monitor whether the interactive behavior of the chip design under test meets the preset constraints in order to obtain the behavior consistency verification result of the chip design under test.

[0074] The technical solution of this invention includes an atomic characteristic excitation device that sends at least one random excitation signal to an atomic test model device and a chip design under test (DUT) based on at least one test case from a test case set; an atomic test model device that acquires expected output data corresponding to at least one random excitation signal; an output monitoring device that acquires actual output data of the chip DUT in response to at least one random excitation signal; a functional result comparison device that acquires the functional verification result of the chip DUT based on the actual output data and expected output data; and a behavior consistency monitoring device that concurrently monitors whether the interactive behavior of the chip DUT meets preset constraints to acquire the behavior consistency verification result of the chip DUT. Thus, by using parallel monitoring, both the functional verification result and the behavior consistency verification result of the chip's atomic characteristics are acquired simultaneously, improving testing efficiency and providing a comprehensive verification of the chip's atomic characteristics, avoiding the one-sidedness of atomic characteristic verification results. Furthermore, when multiple random excitation signals are emitted simultaneously, the verification results reflect the true atomic characteristics under complex loads in actual applications, improving the accuracy of the verification results.

[0075] The above-described apparatus can execute the chip atomic characteristic verification method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the chip atomic characteristic verification method provided in any embodiment of the present invention.

[0076] Example 6 In some embodiments, the chip atomic characteristic verification method can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed on a heterogeneous hardware accelerator via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the chip atomic characteristic verification method described above can be performed. Alternatively, in other embodiments, the processor can be configured to perform the chip atomic characteristic verification method by any other suitable means (e.g., by means of firmware).

[0077] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0078] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0079] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0080] To provide user interaction, the systems and techniques described herein can be implemented on a heterogeneous hardware accelerator, which includes: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the heterogeneous hardware accelerator. Other types of devices can also be used to provide user interaction; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or haptic feedback); and input from the user can be received in any form (including sound input, voice input, or haptic input).

[0081] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0082] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0083] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0084] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip atomic characteristic verification system, characterized in that, include: Atomic characteristic excitation device, atomic test model device, functional result comparison device, behavior consistency monitoring device, and output monitoring device; The atomic characteristic excitation device is connected to the atomic test model device and the chip design under test, and is used to send at least one random excitation signal to the atomic test model device and the chip design under test according to at least one test case in the test case set; The atomic testing model device is used to acquire the expected output data corresponding to the at least one random excitation signal; The output monitoring device is connected to the chip design under test and is used to acquire the actual output data of the chip design under test in response to the at least one random excitation signal. The functional result comparison device is connected to the atomic test model device and the output monitoring device, and is used to obtain the functional verification results of the chip design under test based on the actual output data and the expected output data. The behavior consistency monitoring device is used to concurrently monitor whether the interactive behavior of the chip design under test meets preset constraints, so as to obtain the behavior consistency verification result of the chip design under test.

2. The chip atomic characteristic verification system according to claim 1, characterized in that, The chip atomic characteristic verification system also includes a parameter extraction device; The parameter extraction device is used to obtain, based on the verification test requirement document, atomic characteristic requirement document, transmitter interface mapping document, and parameter flow management document, an atomic transmitter list, an atomic data type library, an atomic operation type library, an operation type and data type mapping library, a parameter library, a test scenario configuration list, and a transmitter mapping library.

3. The chip atomic characteristic verification system according to claim 1 or 2, characterized in that, The chip atomic characteristic verification system also includes an operator unit library and an atomic test model generation device; The operator unit library is connected to the atomic test model generation device and is used to store the set of operation units; The atomic test model generation device is used to obtain a target object based on an atomic data type library, an atomic operation type library, and an operation type to data type mapping library; obtain a target operation unit from the operator unit library based on the target object; generate the atomic test model device based on the target object and the target operation unit; and configure the parameters of the atomic test model device through a parameter library; wherein the target object includes a target operation type and a target data type.

4. The chip atomic characteristic verification system according to claim 1 or 2, characterized in that, The atomic characteristic excitation device also includes multiple random excitation generation devices, emission address management devices, driver mapping devices, and tag library management devices; The random stimulus generation device is used to generate random operation types through a first random unit and to generate random data types that match the random operation types through a second random unit; wherein, the random stimulus generation device is matched one-to-one with the atomic emitters; the random operation types and the random data types are used to generate test cases; The emission address management device is used to obtain the address of the atomic emitter; The driver mapping device is used to acquire the identifier of the atomic emitter; The label library management device is used to manage test parameter labels and regression labels.

5. The chip atomic characteristic verification system according to claim 1 or 2, characterized in that, The chip atomic characteristic verification system also includes a verification interface mounting device; the behavior consistency monitoring device specifically includes a monitoring configuration unit, an observation information processing unit, and a compliance determination unit. The verification interface mounting device connects the verification intellectual property core and the chip design under test, and is used to guide the verification intellectual property core to verify the interface and protocol of the chip design under test; The monitoring configuration unit is used to determine the monitoring object based on the atomic emitter identifier and the verification interface mounting device, and to establish an observation connection for the monitoring object in order to obtain observation data through the observation connection; wherein, the monitoring object includes interactive behaviors related to atomic properties; The observation information processing unit is used to process the observation data to form the input features required for compliance determination; wherein, the data processing includes at least one of sorting, extraction and transformation; The conformity determination unit is used to compare the input features with the preset constraints to output a behavior consistency determination result.

6. The chip atomic characteristic verification system according to claim 4, characterized in that, The chip atomic characteristic verification system also includes a basic testing device, a heterogeneous configuration device, and a test case generation device; The basic test apparatus is used to perform pre-verification steps; wherein, the pre-verification steps include at least one of application programming interface initialization, storage controller initialization, benchmark reference configuration, and global clock reset generation; The heterogeneous configuration device is used to provide configuration parameters and test stimuli for other heterogeneous intellectual property cores in the test path; The test case generation device is used to select a matching target random stimulus generation device from the atomic characteristic stimulus device and a matching target heterogeneous intellectual property core from the heterogeneous configuration device based on the test scenario configuration list, so as to generate test cases according to the pre-verification step, the target random stimulus generation device and the target heterogeneous intellectual property core, and add the test cases to the test case set.

7. A method for verifying the atomic characteristics of a chip, characterized in that, The chip atomic characteristic verification system according to any one of claims 1-6 includes: The atomic characteristic excitation device sends at least one random excitation signal to the atomic test model device and the chip design under test according to at least one test case in the test case set; The atomic testing model device acquires the expected output data corresponding to the at least one random excitation signal; The output monitoring device acquires the actual output data of the chip design under test in response to the at least one random excitation signal; The functional result comparison device obtains the functional verification results of the chip design under test based on the actual output data and the expected output data. The behavior consistency monitoring device concurrently monitors whether the interactive behavior of the chip design under test meets preset constraints in order to obtain the behavior consistency verification results of the chip design under test.

8. A chip atomic characteristic verification device, characterized in that, The chip atomic characteristic verification system configured in any one of claims 1-6 includes: The test case acquisition module, configured in the atomic characteristic excitation device, is used to send at least one random excitation signal to the atomic test model device and the chip design under test based on at least one test case in the test case set; The expected output acquisition module, configured in the atomic test model device, is used to acquire the expected output data corresponding to the at least one random excitation signal; An actual output acquisition module, configured in the output monitoring device, is used to acquire the actual output data of the chip design under test in response to the at least one random excitation signal; A functional verification execution module, configured in the functional result comparison device, is used to obtain the functional verification result of the chip design under test based on the actual output data and the expected output data. The behavior consistency verification execution module is configured in the behavior consistency monitoring device and is used to concurrently monitor whether the interactive behavior of the chip design under test meets the preset constraints in order to obtain the behavior consistency verification result of the chip design under test.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the chip atomic characteristic verification method of claim 7.

10. A computer program product comprising a computer program that, when executed by a processor, implements the chip atomic characteristic verification method of claim 7.

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