698 results about "Logisim" patented technology

The present application relates to the technical field of hanging debugging, and discloses a debugging method, device and equipment for a hanging management engine and a storage medium, which are applied to a baseboard management controller, wherein the baseboard management controller, a complex programmable logic device and a platform path controller are communicatively connected in pairs; the method comprises the following steps: when an abnormal state of the management engine is detected, obtaining state information of the platform path controller; the abnormal state information of the abnormal state is obtained by communication between the complex programmable logic device and the platform path controller and is sent to the baseboard management controller; based on the state information, the management engine is debugged to determine the abnormal source of the management engine. In this way, when the management engine is in an abnormal state, the state information of the platform path controller is obtained to debug the management engine and determine the abnormal source of the management engine, thereby improving the timeliness and completeness of the relevant debugging information obtained when the management engine is hanging, and thus the debugging efficiency of the hanging management engine is improved.

The application discloses an excitation automatic generation method and system and a computer readable medium, and relates to the technical field of electronic design. The method comprises the following steps: based on a pre-acquired test case file, a target test case is acquired from a plurality of pre-stored test cases; case key information of the target test case is acquired, and the case key information is used for representing basic signals to be simulated by the target test case; and based on the case key information, an excitation signal is generated. Therefore, in the face of different target test cases, a control excitation signal with a unified style is automatically generated based on the case key information of the target test case, thereby reducing the dependence of cases on manual checking of logic functions and manual writing of excitations for the functions, and improving the design and development efficiency of integrated circuits.

The application relates to the technical field of cross-domain computing, in particular to a decoupled packaging structure based on dynamic late binding and an in-situ execution method thereof; the three-layer decoupled packaging structure comprises a knowledge arrangement layer, an abstract logic layer and a symbolic interface layer; the technical effect of realizing logic non-movement configuration movement is achieved; a rule package does not need to be changed by one byte, and only by modifying an external configuration table, the rule package can be switched from processing historical data to processing real-time data instantaneously; a standardized packaging structure and an execution mechanism are provided, and three-party complete decoupling of knowledge definition, resource configuration and an execution environment is realized.

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The application discloses a soft and hard bidirectional semantic addressing jump method, belongs to the technical field of artificial intelligence data addressing and end-side storage, and is applied to the scene of artificial intelligence end-side equipment and edge computing equipment. According to the application, the semantic unit division is completed according to the minimum semantic granularity for the data to be processed, the unique mapping binding relationship between the software end logical address and the hardware end physical address is established based on the semantic unit, the one-way or bidirectional corresponding switching of the two types of addresses is realized through jump or table lookup operation, and the address one-to-one mapping alignment is kept through the semantic unit in the whole switching process and after the switching is completed. The application can cover the bidirectional addressing scene, solves the problems of asynchronous addressing, data disorder, power-off loss of mapping and high power consumption in the prior art, and improves the addressing stability of equipment.

The application is applied to the field of architecture anti-corrosion technology, and discloses a method, device and equipment for preventing and controlling system architecture corruption, and a storage medium. The method comprises the following steps: acquiring a visual architecture topology graph; the visual architecture topology graph is drawn through a preset graphical editor; the visual architecture topology graph is a logical topology graph corresponding to a distributed application system; acquiring architecture model data based on the visual architecture topology graph; generating rule data corresponding to the distributed application system based on the architecture model data; and performing rule monitoring on business code by using the rule data to determine whether the business code meets the rule data. In this way, the automatic and comprehensive review of the business code is realized by the rule data generated by the architecture model data corresponding to the visual architecture topology graph without depending on the ability of an architect, thereby improving the anti-corrosion effect of the system architecture.

This invention discloses a method, apparatus, device, storage medium, and program product for extracting interface changes. The method includes: acquiring merged request (PR) data corresponding to the target interface within a first specified time period; extracting features from the PR data to obtain a first PR feature; performing a structured conversion of the first PR feature according to a pre-set Markdown format specification to obtain a Markdown document, wherein the Markdown document includes original and target values ​​of basic interface information, original and target values ​​of request parameters, original and target values ​​of response parameters, and original and target values ​​of interface logic; validating the Markdown document, and if the validation passes, sending the Markdown document to a terminal device for display. Therefore, this embodiment can automatically extract interface change information, improving extraction efficiency.

This invention provides a heterogeneous architecture-based system and method for accelerating large language model inference, aiming to address the limitations of existing acceleration solutions in terms of cost, power consumption, storage capacity, and collaborative efficiency in meeting the deployment requirements of ultra-large-scale MoE models. The system primarily comprises a CPU, an FPGA accelerator card, and a high-speed communication interface. This method, targeting large language models with a hybrid expert architecture, analyzes the computational characteristics and storage requirements of different modules. It deploys computationally intensive attention calculations and shared expert calculations with relatively fixed parameter sizes on the FPGA accelerator card; while storing routing expert weights with large parameter sizes, sparse access, and strong data dependencies in the CPU memory, which then performs routing decisions and routing expert calculations. This invention effectively overcomes the storage capacity limitations of programmable logic accelerator cards, supports the deployment of ultra-large-scale sparse parameter models, and significantly reduces system cost and power consumption, improving the overall energy efficiency and practicality of heterogeneous collaborative inference.

This invention discloses a security chip based on a configurable lookup table. The security chip includes: at least one configurable logic block, each containing at least one configurable lookup table unit; a dynamic mask generator connected to the configurable lookup table unit, dynamically generating a mask sequence according to the current processing clock cycle; a reconfiguration controller connected to the dynamic mask generator, changing the configuration values ​​of the configurable lookup table units in real time according to a security policy; and a security execution engine, whose input is connected to the output of the configurable lookup table unit, performing secure operations based on the masked lookup results; wherein the configurable lookup table unit presents different truth table mappings for the same logic input in at least two different clock cycles. This invention enables the lookup table unit to present different truth table mappings in different clock cycles, breaking the deterministic correlation between power consumption characteristics and data, and effectively resisting side-channel attacks such as differential power analysis.

This application discloses a software testing method and related equipment based on dual-model collaboration, relating to the field of software testing technology. The method includes: processing a natural language requirements document using a pre-defined large language model to obtain a test script for testing the software under test; if the software test result is a test failure, verifying and classifying the test result using a pre-defined algorithm model to obtain abnormal scripts and system bugs; correcting the abnormal scripts and system bugs; and iteratively testing the software under test based on the corrected test script and the corrected software under test until the software test is completed. This application, through a collaborative architecture of "large model understanding + small model judgment" and a semantic consistency detection mechanism, effectively corrects logical deviations in the generated content (test script), ensuring a high degree of matching between test cases and system functional behavior, significantly improving the reliability and executability of test cases, and thus achieving high-quality and high-efficiency software testing.

The application provides a device and working method for AI chip system architecture verification, including a control center for logic control, timing coordination and data interaction of each module. A pulse writing module generates a writing signal with a special pulse form to realize state programming and conduct adjustment of storage or computing devices. A programming selection module accepts the signal of the pulse writing module, supports the structure requirements of various different memory devices of the measured unit, and performs different selective writing according to different array structures. A decoding module accepts the signal of the programming selection module and the feedback signal of the measured unit to be read, and is used for address space mapping, excitation line management and signal on-off control. The measured unit accepts the writing signal of the decoding module and feeds back the reading signal to the decoding module, and is used for storing neural network weights, logic states or continuous conduct grades. The application provides key test support and decision basis for AI chip system architecture research.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

This invention discloses a method, device, and medium for error prediction and self-repair in low-code applications, belonging to the field of low-code platform technology. It addresses the technical problems of existing low-code platforms, which rely heavily on manual testing, are prone to lag, have blind spots, and are difficult for non-professional developers to diagnose deep-seated logical errors. The method includes: classifying and configuring business scenarios in the low-code platform, collecting and obtaining scenario constraint data; performing error prediction detection on the low-code data at both dynamic and static levels to obtain dynamic and static error results; performing error prediction detection on the low-code data at the machine learning prediction layer to obtain machine learning layer error prediction results; classifying and repairing both dynamic / static error results and machine learning layer error prediction results to obtain repair result information; and blocking high-risk error results to obtain blocking result information; thereby completing error prediction and self-repair in the low-code application.

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

In some embodiments, a secure chatbot includes a generative language module (GLM) and a prompt manager configured to dynamically update GLM input prompts according to outputs of the GLM. The input prompts instruct the GLM to perform a task (e.g., determine whether a target message received by a user indicates online fraud) and, in response, output a particular token. In response to detecting the token within the output of the GLM, the prompt manager can selectively execute a code snippet identified according to the respective token. Executing the code snippet effectively updates the prompt, which is then fed back to the GLM for a next inference step. In contrast to conventional LLM prompts, the updates to the prompts herein include modifications (e.g., insertion of other tokens, etc.) rather than merely appending inferred tokens to previous prompts. Moreover, the prompt modifications are executed inline, i.e., without submitting a wholly new prompt to the GLM.

This invention relates to the fields of computer data processing and network communication technology, specifically to a method and system for real-time synchronization of paperless interactive information across multiple terminals. The method includes: a logic construction step: acquiring the original interactive command stream, constructing a semantic causal logic tree based on a vector clock, and dividing strong barriers and weak streaming events; a backpressure monitoring step: establishing a rendering backpressure model to calculate the rendering backpressure value of the target terminal; a dynamic shaping step: responding to a backpressure value exceeding a threshold, reducing the dimensionality of the command stream and reorganizing its timing, attaching weak streaming events to strong barrier events and merging them into an atomic state snapshot for transmission; and a consistency verification step: comparing the screen content-aware hash value, and if a mismatch occurs, performing full state synchronization. This invention solves the problem of visual semantic confusion caused by differences in rendering capabilities between heterogeneous terminals.

A compute device comprising includes volatile memory (VM) dies stacked with a non-volatile memory (NVM) die and a logic die having control logic. A first plurality of through-silicon vias (TSVs) are formed through the one or more VM dies and the NVM die. In embodiments, the first plurality of TSVs are intercoupled through a plurality of microbumps. The control logic writes data to and reading data from the one or more VM dies through a first subset of the first plurality of TSVs. The control logic folds the data from the one or more VM dies to the NVM die through a second subset of the first plurality of TSVs that are fewer than the first subset and are dedicated to the folding of the data.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

This invention discloses a firmware burning mode triggering method, an intelligent fusion terminal, and a system for embedded devices. The firmware burning mode triggering method for embedded devices is applied to an embedded device including a main control unit and at least one function key. The method includes: after the main control unit is powered on, running a bootloader; during the execution of the bootloader, monitoring the level state of a specific function key designated as a mode trigger key; when the duration of continuous pressing of the mode trigger key reaches a first preset threshold T1, determining that the user intends to enter the firmware burning mode; and responding to the determination, controlling the embedded device to enter a state of waiting to receive firmware burning data. This invention can achieve an effective firmware burning mode triggering mechanism to prevent accidental operation by reusing existing function keys and optimizing the logic of the bootloader without adding dedicated hardware.

The application discloses a remote online upgrading method and device of a programmable logic device and a medium, wherein a basic firmware area and a use firmware area which do not overlap each other are divided in a FLASH storage space; a host computer cuts a program to be upgraded into fixed frames, and then continuously sends the frames to an FPGA through a high-speed serial interface; the FPGA decodes the frames through an internal GTX high-speed transceiver according to a preset protocol, obtains continuous effective program data, and buffers the data in an on-chip ROM buffer area; a first-erasing-then-writing operation is performed on the FLASH, and the first-erasing-then-writing operation is checked; through double-mirror management of two programs, a timeout trigger is monitored to trigger a rollback to ensure that a basic function of the program can be run; data is transmitted by using the GTX to accelerate the upgrading speed, and the transmission is ensured to be complete through a CRC check and a retransmission mechanism; a pipeline type data transmission is realized through a ping-pong buffer structure; and the upgrading reliability is increased by comparing FLASH writing data.

This invention belongs to the interdisciplinary field of digital twins and artificial intelligence, specifically disclosing an automatic generation method for manufacturing equipment control logic based on neural-symbolic collaboration and intermediate representation verification. This method utilizes a neural-symbolic collaboration strategy, employing four-element semantic model constraints and thought chain reasoning to transform unstructured natural language process instructions into structured hierarchical state machine (HSM) intermediate representations. Through linear temporal logic (LTL) formal verification and graph theory connectivity analysis, static security verification of the control logic is performed, effectively improving the system's temporal determinism and deadlock resistance. Based on this, the system performs dynamic physical simulation in a digital twin environment, extracting spatial coordinate deviations when mechanical interference occurs, and inversely mapping these deviations into structured error correction prompts, which are then fed back to the large language model for logic reconstruction. This invention constructs a cross-modal "generation-verification-correction" closed-loop mechanism, achieving deep integration of model cognitive intent and underlying physical space constraints, ultimately deterministically compiling the verified intermediate representation into highly reliable industrial standard control code.

This invention discloses a live-cell analysis method and system based on a large model and formal verification. The method includes context injection and intent reasoning, receiving natural language and analyzing it using a large language model to infer the required algorithm modules and output candidate configuration files. Formal logical verification involves reading the candidate configuration files and converting them into standardized logical constraint code, which is then verified by a solver. Conflict self-healing and iteration are implemented: if the solver verification fails, the conflict core is identified, and the connection method of the candidate configuration file or algorithm module is modified according to an arbitration strategy, while updating the logical constraint code until the solver verification passes. An analysis pipeline is instantiated and constructed: if the solver verification passes, an executable analysis pipeline is built based on the final determined candidate configuration files for live-cell analysis. Analysis code is generated using a large language model and logically verified using formal methods to analyze live-cell microscopic images.

The application discloses a double-gate reconfigurable field effect transistor process design kit construction method, and belongs to the field of integrated circuit process design kit expansion, reconfigurable device modeling and physical verification. In view of the fact that existing open source PDK mainly faces traditional CMOS devices and is difficult to support circuit design, layout drawing and post-layout verification of double-gate RFET, the application provides a process design kit construction method for double-gate RFET. The method comprises the following steps: constructing a four-terminal RFET compact model and packaging the four-terminal RFET compact model into a SPICE subcircuit; establishing a schematic symbol, a layout unit and parameter configuration; extending LVS device identification rules to identify four-port RFET devices containing a source, a drain, a control gate and a polarity gate; constructing a parasitic parameter extraction file and integrating the parasitic parameter extraction file into a layout verification process; and finally, performing post-layout simulation verification on an RFET inverter and reconfigurable NAND and NOR logic. The application realizes a complete design closed loop of double-gate RFET from a model, a schematic, a layout, DRC / LVS, PEX and reverse label simulation.

Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). A method includes configuring a programmable logic device (PLD) having a fabric of programmable logic blocks arranged in a plurality of regions; routing data carry chains in a first direction across the fabric to each of the plurality of regions; placing global clock circuitry at a first edge of the PLD; and routing the global clock to a corresponding first edge of each region via a global clock trunk and a plurality of clock branches, the global clock trunk propagating the global clock signal across the fabric and in each region, in the same direction as the data carry chains.