61 results about "Logic synthesis" patented technology

The invention provides a logic synthesis cutting delay prediction method based on a graph neural network, which comprises the following steps of: firstly, constructing a cutting (Cut) delay prediction data set of a logic synthesis circuit, then extracting structural and functional features of nodes in a cutting sub-graph, constructing a heterogeneous cutting level graph taking a cutting super node as a center, and finally, carrying out segmentation on the heterogeneous cutting level graph. And packaging into a graph neural network input format. Then, a delay prediction model is constructed, the delay prediction model comprises a graph neural network module and a multi-layer perceptron module, the graph neural network module extracts circuit structure features and pointer attention mechanism dynamic association standard cell library features through SAGE convolution, and enhanced cutting representation is formed; and finally, carrying out delay prediction on cutting in a new circuit by utilizing the trained model. According to the method, the cutting structure modeling capability and the delay prediction precision are effectively improved, the method can be used for optimizing a cutting selection strategy in a synthesizer, and the logic comprehensive quality is improved.

The invention relates to the technical field of digital logic design, and discloses a hierarchical incremental logic synthesis method and device for multi-module design, and the method comprises the steps: building a node mapping relation between an original HDL hierarchical structure and an original network surface layer substructure; comparing the modified HDL hierarchical structure with the original HDL hierarchical structure, and identifying a target module which is changed; determining a module range, and constructing an HDL sub-design for the module range; performing logic synthesis on each HDL sub-design to generate a local department-level netlist; and integrating the local department-level netlist into the original comprehensive netlist to generate a comprehensive netlist after incremental updating. According to the method, the node mapping relation between the original HDL hierarchical structure and the original net surface layer substructure is established and utilized, so that the cross-boundary optimization behavior of the synthesizer is accurately tracked and compatible, the problem that the original structure is inconsistent with the net list structure is fundamentally solved, and the function correctness of incremental synthesis is ensured.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

The invention discloses a critical path optimization method and device and an optimization strategy determination method and device in logic synthesis. The optimization method comprises the following steps: identifying an initial key path from a comprehensive result corresponding to an RTL code, deleting a buffer tree on the path, and recording the path as a target key path; identifying abnormal path segments from all the target key paths, grouping all loads corresponding to the target signal lines on each abnormal path segment according to the obtained actual fan-out number on each abnormal path segment, copying the drivers of the target signal lines according to a copying strategy, and connecting the copied drivers with the load groups based on a preset connection strategy; and circularly executing optimization operation on all the abnormal path segments, and obtaining an optimized gate-level netlist after the path optimization operation on all the target key paths is completed. According to the method, the key path can be accurately identified, the comprehensive result is directly optimized, repeated modification and debugging on the RTL level are effectively avoided, and the efficiency of the whole design process is improved.

The application discloses a circuit input sensitivity analysis method based on Undef SAT, which comprises five steps of netlist analysis and input division, two groups of CNF clause construction, S set assignment and initial solving, first group of solution increment SAT processing and termination and result output. The method uses the incremental SAT processing mode to gradually determine the final assignment of the input variables of the L set, effectively avoids full space search, significantly reduces the search space, and improves the analysis and determination efficiency. The method constructs two groups of CNF clauses supporting irrelevant item propagation, directly processes the irrelevant input variables of the S set by using the Undef SAT solver, reduces the number of logic propagation, and thus reduces the operation time. The integrated process of the circuit input sensitivity analysis formed by the method is suitable for mainstream EDA tool chains, has good engineering applicability, and is suitable for different scenes such as logic synthesis stage, formal verification, functional equivalence checking and loop oscillation detection.

This invention discloses a functional testing device and method for trackside precision equipment in the rail transit industry. The functional testing device includes: an industrial control computer; a network switch connected to the industrial control computer; and at least one chassis containing multiple test boards, which are either A-series or B-series test boards for trackside precision equipment. The A-series and B-series boards have identical structures. The multiple test boards are communicatively connected to the industrial control computer via the network switch. The industrial control computer sends control commands to perform individual function tests and interlocking logic comprehensive tests on each test board. Its advantages are: this functional testing device can perform individual function tests and interlocking logic comprehensive tests on the test boards of trackside precision equipment; it can test the main functional modules of the test boards, ensuring complete and stable board functions and performance; simultaneously, it can perform interlocking logic comprehensive tests to test multiple test boards, improving board testing efficiency and the timeliness of reproducing board problems.

The invention discloses a structured sparse matrix multiplier realized based on FPGA primitives, and belongs to the technical field of FPGA hardware acceleration and deep learning computing architecture. The multiplier is composed of a register area and a multiplication and addition area, and the core design thought is that a circuit is built in a customized mode by directly calling bottom layer physical resources based on FPGA primitives; the register area stores a dense matrix B and supports parallel reading of elements by utilizing the characteristic that LUT in an SLICEM can be configured to be double SRL16E; the multiplication and addition area refers to a partial product generation unit based on the 4-Booth algorithm and an improved GPC (4: 2) compressor structure, and efficient generation and rapid accumulation of partial products are achieved. According to the method, redundant loss caused by high-level HDL logic synthesis is avoided through precise physical resource binding of primitives, fine wiring constraint and structured sparse data characteristic adaptation.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

A simultaneous placement and routing based method and apparatus for incremental design optimization, and a computer device. The method includes according to a net-list file and a core constraint file acquired after logic synthesis, sequentially placing modules, each including units, on an initial coarse grid and simultaneously performing routing of each module and a placed module; performing iterative verification on placement and routing of the modules, and adjusting an illegal module and simultaneously adjusting routing of the illegal module according to a verification result, until requirements of the core constraint file are met; refining the grid, dividing each module into a plurality of sub-modules, and performing simultaneous placement and routing on the sub-modules in a refined grid; performing iterative verification and simultaneously adjusting placement and routing of illegal sub-modules; and repeating the above steps, until the iterative verification meets the requirements of the core constraint file and timing convergence.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The invention discloses a process control method and device for rear-end design of a digital chip and EDA tool software, and the method comprises the steps: firstly, carrying out RC automatic calibration on a pre-wiring database according to a design database, a reference database, a reference parasitic parameter information file and / or a preset time sequence calibration target, and then obtaining a parameter configuration file, the parameter configuration file comprises calibration configuration parameters for parasitic parameter extraction and / or time sequence values; and then loading the parameter configuration file in a logic synthesis stage, a layout stage, a clock tree synthesis stage, a wiring stage and / or an ECO stage of physical perception in a digital chip back-end design for RC extraction. According to the calibration configuration parameters, RC extraction or a time sequence value of a certain stage is used as a reference value to guide an RC engine of another stage, and then an optimized RC estimation model is used for iterative design again, so that a calibrated RC estimation or extraction model can be applied in different stages, the RC estimation and extraction precision is improved, and the design process efficiency is further improved.

Software tools, tools flows and software infrastructure to extract content and execute extracted content in hardware (termed content-computing) from a high-level language description of an application software program is disclosed. A software program for content-computing comprises: a high-level logic synthesis software to convert an identified content in an application program to a synthesized hardware image; and a language compiler software to instantiate the content customized instruction to execute in a configurable hardware unit programmed to the synthesized hardware image. A software tools flow to generate executable instructions in an application software program comprises a combined high level logic synthesis software and language compiler software to: identify an application software program content that is targeted for hardware implementation as a hardware function in a configurable hardware unit that comprises configuration memory; generate a synthesized gate-level netlist of the targeted hardware function; generate a bit-stream of configuration memory to program the targeted hardware function in the configurable hardware unit; and generate a compiled hardware instruction for a processor unit to execute the instruction in the configured hardware function.

Embodiments of the present application provide a circuit logic synthesis parameter optimization method, device, equipment and medium, the method comprises: obtaining initial clock uncertainty parameter and initial clock conversion time parameter; according to initial clock uncertainty parameter, initial clock conversion time parameter and preset optimization model, determine optimization clock uncertainty parameter and optimization clock conversion time parameter;According to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine timing score and area score;In the case where timing score and area score meet the preset score condition, according to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine target clock uncertainty parameter and target clock conversion time parameter;In this way, the optimized clock uncertainty parameter and clock conversion time parameter can be accurately calculated.The problem of parameter setting depending on experience and lacking scientificity is solved, and the accuracy and reliability of clock tree design are improved.

The application provides a mixed polarity RM logic area-power consumption trade-off analysis system and method, which is applied to the field of integrated circuit design and comprises a logic library database, a mixed polarity synthesizer, a logic synthesizer, a power consumption calculator, a constraint converter and a layout analyzer. The mixed polarity synthesizer is a core innovative module, which comprises a circuit topology mapping engine, a multi-level homomorphism decision engine, a spectrum feature cooperative optimization engine and an optimization strategy adjustment unit. The application innovatively maps the circuit structure into a weighted directed graph and converts the polarity distribution problem into an optimization problem on the graph. The multi-level topology homomorphism model is adopted to realize the macroscopic, mesoscopic and microscopic representation of the circuit, thereby effectively reducing the optimization complexity. The spectrum graph theory is introduced to analyze the circuit structure, and the optimal trade-off between area and power consumption is realized through spectrum segmentation and cooperative optimization. Compared with the prior art, the search space is reduced by more than 80%, and the optimization speed is increased by 3-5 times.

The invention discloses a chip design method based on digital chip IP integration. The method comprises the following steps: setting specifications; architecture design: designing a chip structure according to the specification; the writing module is used for performing RTL writing based on a chip structure, the RTL writing comprises digital IP integration, and specifically, an IP integration event table is configured; reading port description of an original IP file through a matching rule based on configuration in the IP integration event table, and extracting input and output signals and bit width information; generating a standardized packaging file according to a matching result of the matching rule; storing the standardized packaging file and the associated IP integration event table into an IP pool for multiplexing; function simulation: verifying a chip function; and logic synthesis: physically synthesizing the verified chip. According to the chip design method based on digital chip IP integration, manual operation is replaced with the IP integration event table and the automatic tool, the efficiency of design and product opening is improved, and the technical problems that in the prior art, efficiency is low, the error rate is high and reuse is difficult are solved.

The present disclosure relates to the technical field of FPGA, and discloses a LUT Pack method and device based on backend feedback-oriented optimization, which comprises: in the logic synthesis stage, generating an initial configuration file; performing a first implementation process, performing layout and wiring on the target circuit design, and collecting physical information after layout and wiring; based on the collected physical information, optimizing and updating the constraint parameters in the initial configuration file to generate an updated configuration file; taking the updated configuration file as input, performing the next iteration process until the preset convergence condition is met, and finally outputting the optimized hardware design data. By introducing a closed-loop feedback and iterative optimization mechanism based on real physical information of backend layout and wiring, the present disclosure realizes dynamic self-adaptive adjustment of the LUT packing strategy, thereby overcoming the contradiction between resource utilization rate and timing performance, and achieving a global optimization balance between area efficiency and circuit performance.

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

This invention discloses a logic synthesis mapping method based on FPGA dual-output lookup tables. First, the target circuit netlist is preprocessed and structurally normalized, mapping logic nodes to single-output lookup tables of a unified format. Then, through primitive normalization, each lookup table unit is converted into native lookup table primitives consistent with the target FPGA technology library, forming a standardized lookup table netlist. An inverted index is constructed, and candidate lookup table pairs with shared inputs are generated using index relationships. Structural and functional constraints are sequentially performed on the candidate pairs to filter out mergeable lookup table pairs. After sorting them using a resource cost function, a merge mapping is performed sequentially, concatenating them into a six-input dual-output lookup table and generating corresponding initialization parameters. This method can reduce the number of lookup tables and input pin pressure while maintaining logical functional correctness, and can be integrated as an independent optimization step into various FPGA synthesis and place-and-route tools.

This utility model discloses a conventional relay logic device for "N-to-M" signal selection. Taking "5-to-3" signal selection as an example, it mainly consists of a signal input module, a logic synthesis and judgment output module, and a signal source early warning and device fault alarm output module. The signal input module mainly consists of 5 branches; the logic synthesis and judgment output module mainly consists of 2 branches; and the signal source early warning and device fault alarm output module mainly consists of 12 branches. This utility model is used to ensure the reliability of the signal source and avoid large-scale emergency equipment operation caused by malfunctions, which could lead to losses in engineering projects. It performs "N-to-M" logic judgment on the signal source circuit. It has standardized design specifications, a wide range of applications, and can be directly installed and used. It is suitable for various hydropower and power engineering projects, as well as various industries that use "N-to-M" logic to improve signal accuracy.

An integrated circuit includes a filter circuit and a computation circuit that applies emphasis to a data stream in a frequency domain to reduce distortion to the data stream caused by the filter circuit. The emphasis is determined based on the distortion caused by the filter circuit. A circuit design system includes logic synthesis and optimization tools that relax parameters for a first filter circuit to generate relaxed parameters, use the relaxed parameters to generate a second filter circuit that filters data, generate an emphasis vector based on distortion in the data caused by the second filter circuit, and generate a computation circuit that applies the emphasis vector to the data to reduce the distortion in the data caused by the second filter circuit.

The invention relates to the technical field of integrated circuit design automation (EDA), in particular to a logic circuit comprehensive optimization method based on a graph neural network, which can be applied to a logic comprehensive stage in digital circuit design. Comprising the following steps: representing a logic circuit as a directed symbol graph G = (V, E, X, S), and generating a graph data container C1; constructing a heterogeneous graph neural network model containing alternately stacked side symbol perception GraphSAGE layers and graph isomorphic network GIN layers, and packaging the model into a model container C2; multi-layer convolution is executed, multi-scale features are fused through Dense connection, and a node embedding container C3 is generated; two tasks of node-level probability prediction and graph-level classification prediction are executed in parallel, a prediction result container C4 is output, and graph-level classification outputs selection probabilities of two optimization strategies AIG and MIG; and automatically selecting an optimization strategy according to the classification probability, executing a corresponding circuit optimization algorithm, and outputting an optimized circuit C'and an optimization report.

This invention discloses a remote verification method and system based on a multi-FPGA verification public cloud platform. The method includes: a user selecting a corresponding resource configuration module from multiple candidate resource configuration templates provided by the cloud platform; receiving the design source file uploaded by the user through an encrypted channel; performing logic synthesis, probe insertion, partitioning, mapping, and top module generation operations to complete the simulation configuration; acquiring and calling computing resources from the computing cluster; generating a bitstream file according to the simulation configuration; allocating corresponding resources from the resource pool according to the simulation configuration; configuring the switching architecture routing table; connecting the resources corresponding to the simulation configuration to build a hardware simulation execution environment; loading the generated bitstream file onto the FPGA chip allocated to the user; configuring the peripheral interface board; connecting the debugger to the peripheral and making it ready; and the user remotely logging into the debugger via a virtual network computing protocol to perform simulation and debugging operations to obtain waveform data, thus completing the remote verification.

A control signal generation circuit 5 according to one embodiment comprises: an insulated gate driver that is configured to output a control pulse signal corresponding to a common input pulse signal to first and second switching elements; a delay signal generation unit that is configured to generate at least one delay pulse signal using the control pulse signal; and a logic synthesis unit that is configured to generate first and second control pulse signals by performing different logic synthesis on two signal sets among a plurality of signal sets that are defined by the at least one delay pulse signal and the control pulse signal, wherein the first control pulse signal is different from the control pulse signal, and the second control pulse signal is different from the control pulse signal and the first control pulse signal.

The application provides a chip research and development method, system, device and storage medium, the method comprises the following steps: generating a SPEC file according to a chip architecture, and generating a register conversion circuit code according to the SPEC file; the register conversion circuit code is put into a storage server, and a register conversion circuit index is written into a resource directory; the register conversion circuit code is read based on the register conversion circuit index, and syntax checking is performed on the register conversion circuit code; and it is judged whether there is a syntax error in the register conversion circuit code; in response to the fact that there is no syntax error in the register conversion circuit code, logic synthesis is performed according to the register conversion circuit code to generate a net list, the net list is put into the storage server, and a net list index is written into the resource directory; and the net list is read based on the net list index, and formal verification and timing analysis are performed on the net list. The application can maximize resource utilization and improve research and development efficiency.

The invention discloses a control circuit of a flying capacitor multi-level step-down DC-DC converter, which belongs to the technical field of integrated circuits and comprises a phase shift circuit, a ramp signal generation circuit and a signal generation circuit. Phase shift clock signals with sequentially offset phases are output through logic operation of the logic synthesis circuit, and the duty ratio is set at the same time; the ramp signal generation circuit generates linearly-changed corresponding ramp signals according to the phase shift clock signals, and the ramp signals are connected to the signal generation circuit; the in-phase end of an error amplifier of the signal generation circuit is connected with reference voltage, the inverted end is connected with converter topology output feedback voltage, and the output is connected with the inverted end of a comparator. The in-phase end of the comparator is connected with a corresponding ramp signal, a pulse signal is output to the S end of the RS trigger after voltage comparison, the R end of the RS trigger is connected with a corresponding phase shift clock signal, and an output control signal is connected to a converter topology, so that the defects of large output voltage ripple, large switching stress and loss, EMI challenge and the like are remarkably improved.

The present application relates to a kind of logic synthesis sequence optimization space exploration method and system based on reward correction reinforcement learning, belong to the technical field of electronic design automation, logic synthesis process is embedded into the reinforcement learning algorithm based on reward correction, logic synthesis process is modeled as the environment of reinforcement learning, realize automatic exploration logic synthesis sequence optimization space.The reinforcement learning algorithm is improved for logic synthesis scene, carries out feature extraction and action coding, improves the precision of circuit state representation, expands search space.The present application increases the exploration ability in early training by adding reward correction, obtains adaptive reward function by agent training, reduces the performance decline caused by the limitation of prior knowledge on circuit optimization direction, obtains more optimal logic synthesis area result under the condition of meeting delay constraint.

A method is performed by a trained recipe recommendation model. The method comprises loading a plurality of circuits into a circuit data loader; separately loading a plurality of recipes into a recipe data loader; and generating a recommended recipe for each circuit based on at least one quality of result determined during logic synthesis optimization.

This will reduce the effort required to generate synthetic netlists. [Solution] The logic synthesis apparatus includes: an extraction means for extracting from a netlist portions that are logically equivalent to asset circuit formulas registered in a database as an extracted netlist; a circuit structure determination means for determining the structure of the circuit to be used in the extracted netlist from the database based on the frequency of the extracted netlist and the frequency of the logically equivalent asset circuit formulas registered in the database; a timing margin calculation means for calculating the timing margin based on the determined circuit structure; a cell characteristic determination means for determining the characteristics of the cells to be used in the extracted netlist from the database based on the timing margin calculated by the timing margin calculation means; and a logic synthesis means for converting the netlist into a synthesized netlist having physical characteristics using the circuit structure determined by the circuit structure determination means and the cell characteristics determined by the cell characteristic determination means.

The invention discloses a logic synthesis method and system in a memristor memory driven by a multi-type state logic gate, and the method comprises the steps: taking preset simple logic functions as a synthesis unit library for the input complex logic functions, and carrying out the synthesis, so as to obtain a synthesized netlist composed of the simple logic functions, performing merging processing to combine the simple logic function combination into a simple logic function or a composite logic function so as to obtain an optimized netlist; based on the given array scale of the memristor crossbar switch array, mapping is executed on the optimized netlist by adopting a mapping method based on a topological sorting method so as to obtain an execution sequence of state logic gates in a single row in the memristor storage array; and in the mapping process, the array scale of the memristor crossbar switch array is continuously reduced until correct mapping cannot be carried out so as to obtain a state logic gate execution sequence under the minimum array scale. According to the method, more state logic gate functions, types and mergeable conditions are introduced to optimize and improve the calculation timeliness of the comprehensive mapping result.

The invention discloses an FPGA logic comprehensive netlist optimization method based on Bayesian optimization and an attention mechanism, and the method comprises the steps: converting an original netlist of a to-be-optimized circuit into a graph structure, and carrying out the optimization; performing SAT check on the optimized AIG structure, and if the output function of the main output end is consistent with the function of the initial netlist, returning to the AIG structure after execution of the optimization command; mapping the optimized AIG structure to the LUT of the FPGA for evaluation, and judging whether the requirements are met or not; calculating and predicting a sequence-result space formed by different command combination sequences by using an improved Gaussian process regression model; calculating and selecting a next command sequence with the most potential according to an adaptive sampling function; and training until performance requirements are met. The method is low in cost loss and high in search efficiency.