86 results about "Logic synthesis" patented technology

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention provides a logic synthesis cutting delay prediction method based on a graph neural network, which comprises the following steps of: firstly, constructing a cutting (Cut) delay prediction data set of a logic synthesis circuit, then extracting structural and functional features of nodes in a cutting sub-graph, constructing a heterogeneous cutting level graph taking a cutting super node as a center, and finally, carrying out segmentation on the heterogeneous cutting level graph. And packaging into a graph neural network input format. Then, a delay prediction model is constructed, the delay prediction model comprises a graph neural network module and a multi-layer perceptron module, the graph neural network module extracts circuit structure features and pointer attention mechanism dynamic association standard cell library features through SAGE convolution, and enhanced cutting representation is formed; and finally, carrying out delay prediction on cutting in a new circuit by utilizing the trained model. According to the method, the cutting structure modeling capability and the delay prediction precision are effectively improved, the method can be used for optimizing a cutting selection strategy in a synthesizer, and the logic comprehensive quality is improved.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention belongs to the field of electronic design automation (EDA), and particularly provides a logic comprehensive optimization operator acceleration method, which introduces a screening strategy of a sub-circuit diagram, and improves the optimization efficiency of an operator on the premise of ensuring the optimization quality of the operator. According to the method, the sub-circuit diagrams are classified by using the graph neural network, and the sub-diagrams suitable for operator execution are screened out, so that all the sub-diagrams are prevented from being traversed, and the operator execution speed is increased; in the sub-graph screening, a screening range is set according to the execution sequence of operators, a relatively large screening range is set for the operators executed firstly so as to obtain a better optimization effect, and a relatively small screening range is set for the operators executed later so as to obtain a higher execution speed; in conclusion, the characteristic that the logic comprehensive optimization operator is continuously executed in a sequence mode is utilized, and the operator optimization efficiency is improved on the premise that the operator optimization quality is guaranteed.

The invention relates to the technical field of digital logic design, and discloses a hierarchical incremental logic synthesis method and device for multi-module design, and the method comprises the steps: building a node mapping relation between an original HDL hierarchical structure and an original network surface layer substructure; comparing the modified HDL hierarchical structure with the original HDL hierarchical structure, and identifying a target module which is changed; determining a module range, and constructing an HDL sub-design for the module range; performing logic synthesis on each HDL sub-design to generate a local department-level netlist; and integrating the local department-level netlist into the original comprehensive netlist to generate a comprehensive netlist after incremental updating. According to the method, the node mapping relation between the original HDL hierarchical structure and the original net surface layer substructure is established and utilized, so that the cross-boundary optimization behavior of the synthesizer is accurately tracked and compatible, the problem that the original structure is inconsistent with the net list structure is fundamentally solved, and the function correctness of incremental synthesis is ensured.

The invention belongs to the field of digital integrated chips, particularly relates to a clock tree generation and optimization method for quickly realizing time sequence convergence, and aims to solve the problems that an existing clock tree does not completely optimize a time sequence violation path and is difficult to realize quick time sequence convergence. The method comprises the following steps: carrying out logic synthesis on RTL codes to obtain a time sequence convergence netlist after logic synthesis; performing chip layout planning and hardware unit placement based on the time sequence convergence netlist; performing clock tree generation and clock tree comprehensive optimization on the chip with the hardware unit to obtain to-be-wired chip data with time sequence convergence; and based on the to-be-wired chip data, wiring of the to-be-wired chip is carried out according to preset parameters, and static time sequence analysis is carried out. According to the method, the frequency index of the chip is effectively optimized by combining an EDA tool, manually adjusting the clock tree structure and guiding the file, the number of iterations in the clock tree generation process and the time sequence optimization process after the clock tree generation process can be reduced, and the method is effective, reliable, convenient and practical.

The invention provides a logic synthesis method and device of an FPGA (Field Programmable Gate Array) device. The method comprises the following steps: identifying a plurality of memory structures corresponding to a target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least: capacity information; and according to the capacity information and the quantity of various types of storage resources supported by the target FPGA device, carrying out storage resource inference on the plurality of memory structures to obtain a target storage resource type of each memory structure. When storage resource inference is carried out on a plurality of memory structures, the plurality of memory structures are not directly inferred as one type of storage resources, and then how to process the memory structures exceeding the quantity of the type of storage resources supported by the target FPGA device is considered, but in the inference process, the number of the types of storage resources supported by the target FPGA device is not considered. Therefore, the capacity information and the quantity of various types of storage resources supported by the target FPGA device are considered, and the logic synthesis time is shortened.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

The invention discloses a critical path optimization method and device and an optimization strategy determination method and device in logic synthesis. The optimization method comprises the following steps: identifying an initial key path from a comprehensive result corresponding to an RTL code, deleting a buffer tree on the path, and recording the path as a target key path; identifying abnormal path segments from all the target key paths, grouping all loads corresponding to the target signal lines on each abnormal path segment according to the obtained actual fan-out number on each abnormal path segment, copying the drivers of the target signal lines according to a copying strategy, and connecting the copied drivers with the load groups based on a preset connection strategy; and circularly executing optimization operation on all the abnormal path segments, and obtaining an optimized gate-level netlist after the path optimization operation on all the target key paths is completed. According to the method, the key path can be accurately identified, the comprehensive result is directly optimized, repeated modification and debugging on the RTL level are effectively avoided, and the efficiency of the whole design process is improved.

The application discloses a circuit input sensitivity analysis method based on Undef SAT, which comprises five steps of netlist analysis and input division, two groups of CNF clause construction, S set assignment and initial solving, first group of solution increment SAT processing and termination and result output. The method uses the incremental SAT processing mode to gradually determine the final assignment of the input variables of the L set, effectively avoids full space search, significantly reduces the search space, and improves the analysis and determination efficiency. The method constructs two groups of CNF clauses supporting irrelevant item propagation, directly processes the irrelevant input variables of the S set by using the Undef SAT solver, reduces the number of logic propagation, and thus reduces the operation time. The integrated process of the circuit input sensitivity analysis formed by the method is suitable for mainstream EDA tool chains, has good engineering applicability, and is suitable for different scenes such as logic synthesis stage, formal verification, functional equivalence checking and loop oscillation detection.

This invention discloses a functional testing device and method for trackside precision equipment in the rail transit industry. The functional testing device includes: an industrial control computer; a network switch connected to the industrial control computer; and at least one chassis containing multiple test boards, which are either A-series or B-series test boards for trackside precision equipment. The A-series and B-series boards have identical structures. The multiple test boards are communicatively connected to the industrial control computer via the network switch. The industrial control computer sends control commands to perform individual function tests and interlocking logic comprehensive tests on each test board. Its advantages are: this functional testing device can perform individual function tests and interlocking logic comprehensive tests on the test boards of trackside precision equipment; it can test the main functional modules of the test boards, ensuring complete and stable board functions and performance; simultaneously, it can perform interlocking logic comprehensive tests to test multiple test boards, improving board testing efficiency and the timeliness of reproducing board problems.

The invention discloses a structured sparse matrix multiplier realized based on FPGA primitives, and belongs to the technical field of FPGA hardware acceleration and deep learning computing architecture. The multiplier is composed of a register area and a multiplication and addition area, and the core design thought is that a circuit is built in a customized mode by directly calling bottom layer physical resources based on FPGA primitives; the register area stores a dense matrix B and supports parallel reading of elements by utilizing the characteristic that LUT in an SLICEM can be configured to be double SRL16E; the multiplication and addition area refers to a partial product generation unit based on the 4-Booth algorithm and an improved GPC (4: 2) compressor structure, and efficient generation and rapid accumulation of partial products are achieved. According to the method, redundant loss caused by high-level HDL logic synthesis is avoided through precise physical resource binding of primitives, fine wiring constraint and structured sparse data characteristic adaptation.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

An embodiment may involve obtaining a specification of connectivity between a plurality of electronic components, a property library of logical validations, and a set of restrictions for an execution environment of the electronic components, wherein each of the electronic components is associated with at least one of the logical validations; determining that, according to properties in the property library applied to their associated electronic components, a subset of the electronic components exhibit invariance within the execution environment; based on the subset of the electronic components that exhibit invariance within the execution environment, rewiring the connectivity between the plurality of electronic components; and performing logic synthesis on the connectivity between the plurality of electronic components as rewired to simplify at least some of the subset of the electronic components that exhibit invariance within the execution environment.

A simultaneous placement and routing based method and apparatus for incremental design optimization, and a computer device. The method includes according to a net-list file and a core constraint file acquired after logic synthesis, sequentially placing modules, each including units, on an initial coarse grid and simultaneously performing routing of each module and a placed module; performing iterative verification on placement and routing of the modules, and adjusting an illegal module and simultaneously adjusting routing of the illegal module according to a verification result, until requirements of the core constraint file are met; refining the grid, dividing each module into a plurality of sub-modules, and performing simultaneous placement and routing on the sub-modules in a refined grid; performing iterative verification and simultaneously adjusting placement and routing of illegal sub-modules; and repeating the above steps, until the iterative verification meets the requirements of the core constraint file and timing convergence.

The present application discloses a comprehensive method, apparatus, device, and storage medium for optimizing chip area, belonging to the field of chip design technology. The method includes: obtaining original timing constraints and a hardware description file, the hardware description file being used to describe the function and structure of the chip circuit; amplifying the clock cycle in the original timing constraints to obtain an amplified timing constraint; based on the amplified timing constraint, executing a logic synthesis process on the hardware description file to obtain a logic netlist, the logic netlist being used to indicate the logical structure of the chip circuit; executing a physical synthesis process based on the logic netlist and the original timing constraints to obtain a physical netlist, the physical netlist being used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit. By relaxing the timing constraints in the logic synthesis stage and using the original timing constraints in the physical synthesis stage, the problem of increased chip area caused by the logic synthesis stage is solved while ensuring timing.

The embodiment of the invention discloses an information interaction method and device. According to the embodiment of the invention, after a congestion hotspot analysis instruction is received, congestion hotspot analysis is carried out on a to-be-tested gate-level netlist to determine at least one combinational logic congestion hotspot, and a to-be-modified code statement is determined in a register transfer-level code according to the combinational logic congestion hotspot; and modifying each to-be-modified code statement into a target code statement, and regenerating a target gate-level netlist according to the modified register transfer-level code. Wherein the to-be-modified code statement only supports to be converted into a combinational logic structure in the logic synthesis process, and the target code statement supports to be converted into a multiplexer structure in the logic synthesis process. Therefore, the embodiment of the invention can support a user to analyze and solve the wiring congestion problem in the logic synthesis process, so that the chip design efficiency is improved, and the negative effects of the wiring congestion problem solving process on the power consumption, the performance and the area of the formed chip are reduced.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The invention discloses a process control method and device for rear-end design of a digital chip and EDA tool software, and the method comprises the steps: firstly, carrying out RC automatic calibration on a pre-wiring database according to a design database, a reference database, a reference parasitic parameter information file and / or a preset time sequence calibration target, and then obtaining a parameter configuration file, the parameter configuration file comprises calibration configuration parameters for parasitic parameter extraction and / or time sequence values; and then loading the parameter configuration file in a logic synthesis stage, a layout stage, a clock tree synthesis stage, a wiring stage and / or an ECO stage of physical perception in a digital chip back-end design for RC extraction. According to the calibration configuration parameters, RC extraction or a time sequence value of a certain stage is used as a reference value to guide an RC engine of another stage, and then an optimized RC estimation model is used for iterative design again, so that a calibrated RC estimation or extraction model can be applied in different stages, the RC estimation and extraction precision is improved, and the design process efficiency is further improved.

Software tools, tools flows and software infrastructure to extract content and execute extracted content in hardware (termed content-computing) from a high-level language description of an application software program is disclosed. A software program for content-computing comprises: a high-level logic synthesis software to convert an identified content in an application program to a synthesized hardware image; and a language compiler software to instantiate the content customized instruction to execute in a configurable hardware unit programmed to the synthesized hardware image. A software tools flow to generate executable instructions in an application software program comprises a combined high level logic synthesis software and language compiler software to: identify an application software program content that is targeted for hardware implementation as a hardware function in a configurable hardware unit that comprises configuration memory; generate a synthesized gate-level netlist of the targeted hardware function; generate a bit-stream of configuration memory to program the targeted hardware function in the configurable hardware unit; and generate a compiled hardware instruction for a processor unit to execute the instruction in the configured hardware function.

Embodiments of the present application provide a circuit logic synthesis parameter optimization method, device, equipment and medium, the method comprises: obtaining initial clock uncertainty parameter and initial clock conversion time parameter; according to initial clock uncertainty parameter, initial clock conversion time parameter and preset optimization model, determine optimization clock uncertainty parameter and optimization clock conversion time parameter;According to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine timing score and area score;In the case where timing score and area score meet the preset score condition, according to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine target clock uncertainty parameter and target clock conversion time parameter;In this way, the optimized clock uncertainty parameter and clock conversion time parameter can be accurately calculated.The problem of parameter setting depending on experience and lacking scientificity is solved, and the accuracy and reliability of clock tree design are improved.

The application provides a mixed polarity RM logic area-power consumption trade-off analysis system and method, which is applied to the field of integrated circuit design and comprises a logic library database, a mixed polarity synthesizer, a logic synthesizer, a power consumption calculator, a constraint converter and a layout analyzer. The mixed polarity synthesizer is a core innovative module, which comprises a circuit topology mapping engine, a multi-level homomorphism decision engine, a spectrum feature cooperative optimization engine and an optimization strategy adjustment unit. The application innovatively maps the circuit structure into a weighted directed graph and converts the polarity distribution problem into an optimization problem on the graph. The multi-level topology homomorphism model is adopted to realize the macroscopic, mesoscopic and microscopic representation of the circuit, thereby effectively reducing the optimization complexity. The spectrum graph theory is introduced to analyze the circuit structure, and the optimal trade-off between area and power consumption is realized through spectrum segmentation and cooperative optimization. Compared with the prior art, the search space is reduced by more than 80%, and the optimization speed is increased by 3-5 times.

The present invention discloses a post-layout physical feature prediction method and system based on a graph neural network. The method converts the circuit netlist of the logic synthesis stage into a topological graph consisting of nodes and edges, constructs an adjacency matrix based on the connection relationship between the nodes, extracts the initial feature vector of each node to obtain a feature matrix, and inputs a graph neural network module consisting of an embedding layer, a multi-layer GNN layer, a merging layer, and a fully connected layer. The feature information of neighboring nodes is aggregated and the semi-perimeter of the post-layout network is predicted. The present invention introduces a physical feature prediction model based on a graph neural network to estimate the post-layout network line length. The predicted result can be used as one of the features of the subsequent early timing prediction framework, significantly improving the prediction accuracy of the post-layout path delay, thereby guiding designers or tools to optimize, reducing design iterations, and lowering the time cost of chip design.

The invention discloses a chip design method based on digital chip IP integration. The method comprises the following steps: setting specifications; architecture design: designing a chip structure according to the specification; the writing module is used for performing RTL writing based on a chip structure, the RTL writing comprises digital IP integration, and specifically, an IP integration event table is configured; reading port description of an original IP file through a matching rule based on configuration in the IP integration event table, and extracting input and output signals and bit width information; generating a standardized packaging file according to a matching result of the matching rule; storing the standardized packaging file and the associated IP integration event table into an IP pool for multiplexing; function simulation: verifying a chip function; and logic synthesis: physically synthesizing the verified chip. According to the chip design method based on digital chip IP integration, manual operation is replaced with the IP integration event table and the automatic tool, the efficiency of design and product opening is improved, and the technical problems that in the prior art, efficiency is low, the error rate is high and reuse is difficult are solved.

Disclosed is a digital integrated circuit design method that extracts the timing characteristics of the rising and falling edges of a double-edge dynamic trigger, obtains a first library with relatively large timing characteristic parameters, unifies the first library into a rising-edge trigger type, and obtains a first process library file. The method then executes the design input, logic synthesis, formal verification, layout and routing, timing checking, and physical verification of a traditional design process, as well as the corresponding simulation process, based on the double-edge dynamic trigger functional model and the first process library file. The digital integrated circuit design method of the present invention creates a first process library file based on the relatively large timing characteristic parameters in the timing characteristics of the rising and falling edges, executes the traditional design process based on the first process library file, and simplifies the integration of double-edge dynamic triggers in digital integrated circuit design while ensuring the reliability of the designed circuit, thereby facilitating the application of double-edge dynamic triggers in digital integrated circuits.

The present disclosure relates to the technical field of FPGA, and discloses a LUT Pack method and device based on backend feedback-oriented optimization, which comprises: in the logic synthesis stage, generating an initial configuration file; performing a first implementation process, performing layout and wiring on the target circuit design, and collecting physical information after layout and wiring; based on the collected physical information, optimizing and updating the constraint parameters in the initial configuration file to generate an updated configuration file; taking the updated configuration file as input, performing the next iteration process until the preset convergence condition is met, and finally outputting the optimized hardware design data. By introducing a closed-loop feedback and iterative optimization mechanism based on real physical information of backend layout and wiring, the present disclosure realizes dynamic self-adaptive adjustment of the LUT packing strategy, thereby overcoming the contradiction between resource utilization rate and timing performance, and achieving a global optimization balance between area efficiency and circuit performance.

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

This invention discloses a logic synthesis mapping method based on FPGA dual-output lookup tables. First, the target circuit netlist is preprocessed and structurally normalized, mapping logic nodes to single-output lookup tables of a unified format. Then, through primitive normalization, each lookup table unit is converted into native lookup table primitives consistent with the target FPGA technology library, forming a standardized lookup table netlist. An inverted index is constructed, and candidate lookup table pairs with shared inputs are generated using index relationships. Structural and functional constraints are sequentially performed on the candidate pairs to filter out mergeable lookup table pairs. After sorting them using a resource cost function, a merge mapping is performed sequentially, concatenating them into a six-input dual-output lookup table and generating corresponding initialization parameters. This method can reduce the number of lookup tables and input pin pressure while maintaining logical functional correctness, and can be integrated as an independent optimization step into various FPGA synthesis and place-and-route tools.

This utility model discloses a conventional relay logic device for "N-to-M" signal selection. Taking "5-to-3" signal selection as an example, it mainly consists of a signal input module, a logic synthesis and judgment output module, and a signal source early warning and device fault alarm output module. The signal input module mainly consists of 5 branches; the logic synthesis and judgment output module mainly consists of 2 branches; and the signal source early warning and device fault alarm output module mainly consists of 12 branches. This utility model is used to ensure the reliability of the signal source and avoid large-scale emergency equipment operation caused by malfunctions, which could lead to losses in engineering projects. It performs "N-to-M" logic judgment on the signal source circuit. It has standardized design specifications, a wide range of applications, and can be directly installed and used. It is suitable for various hydropower and power engineering projects, as well as various industries that use "N-to-M" logic to improve signal accuracy.

An integrated circuit includes a filter circuit and a computation circuit that applies emphasis to a data stream in a frequency domain to reduce distortion to the data stream caused by the filter circuit. The emphasis is determined based on the distortion caused by the filter circuit. A circuit design system includes logic synthesis and optimization tools that relax parameters for a first filter circuit to generate relaxed parameters, use the relaxed parameters to generate a second filter circuit that filters data, generate an emphasis vector based on distortion in the data caused by the second filter circuit, and generate a computation circuit that applies the emphasis vector to the data to reduce the distortion in the data caused by the second filter circuit.