35 results about "Logic synthesis" patented technology

The invention relates to the technical field of digital logic design, and discloses a hierarchical incremental logic synthesis method and device for multi-module design, and the method comprises the steps: building a node mapping relation between an original HDL hierarchical structure and an original network surface layer substructure; comparing the modified HDL hierarchical structure with the original HDL hierarchical structure, and identifying a target module which is changed; determining a module range, and constructing an HDL sub-design for the module range; performing logic synthesis on each HDL sub-design to generate a local department-level netlist; and integrating the local department-level netlist into the original comprehensive netlist to generate a comprehensive netlist after incremental updating. According to the method, the node mapping relation between the original HDL hierarchical structure and the original net surface layer substructure is established and utilized, so that the cross-boundary optimization behavior of the synthesizer is accurately tracked and compatible, the problem that the original structure is inconsistent with the net list structure is fundamentally solved, and the function correctness of incremental synthesis is ensured.

The application discloses a circuit input sensitivity analysis method based on Undef SAT, which comprises five steps of netlist analysis and input division, two groups of CNF clause construction, S set assignment and initial solving, first group of solution increment SAT processing and termination and result output. The method uses the incremental SAT processing mode to gradually determine the final assignment of the input variables of the L set, effectively avoids full space search, significantly reduces the search space, and improves the analysis and determination efficiency. The method constructs two groups of CNF clauses supporting irrelevant item propagation, directly processes the irrelevant input variables of the S set by using the Undef SAT solver, reduces the number of logic propagation, and thus reduces the operation time. The integrated process of the circuit input sensitivity analysis formed by the method is suitable for mainstream EDA tool chains, has good engineering applicability, and is suitable for different scenes such as logic synthesis stage, formal verification, functional equivalence checking and loop oscillation detection.

The invention discloses a structured sparse matrix multiplier realized based on FPGA primitives, and belongs to the technical field of FPGA hardware acceleration and deep learning computing architecture. The multiplier is composed of a register area and a multiplication and addition area, and the core design thought is that a circuit is built in a customized mode by directly calling bottom layer physical resources based on FPGA primitives; the register area stores a dense matrix B and supports parallel reading of elements by utilizing the characteristic that LUT in an SLICEM can be configured to be double SRL16E; the multiplication and addition area refers to a partial product generation unit based on the 4-Booth algorithm and an improved GPC (4: 2) compressor structure, and efficient generation and rapid accumulation of partial products are achieved. According to the method, redundant loss caused by high-level HDL logic synthesis is avoided through precise physical resource binding of primitives, fine wiring constraint and structured sparse data characteristic adaptation.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

A simultaneous placement and routing based method and apparatus for incremental design optimization, and a computer device. The method includes according to a net-list file and a core constraint file acquired after logic synthesis, sequentially placing modules, each including units, on an initial coarse grid and simultaneously performing routing of each module and a placed module; performing iterative verification on placement and routing of the modules, and adjusting an illegal module and simultaneously adjusting routing of the illegal module according to a verification result, until requirements of the core constraint file are met; refining the grid, dividing each module into a plurality of sub-modules, and performing simultaneous placement and routing on the sub-modules in a refined grid; performing iterative verification and simultaneously adjusting placement and routing of illegal sub-modules; and repeating the above steps, until the iterative verification meets the requirements of the core constraint file and timing convergence.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The application provides a mixed polarity RM logic area-power consumption trade-off analysis system and method, which is applied to the field of integrated circuit design and comprises a logic library database, a mixed polarity synthesizer, a logic synthesizer, a power consumption calculator, a constraint converter and a layout analyzer. The mixed polarity synthesizer is a core innovative module, which comprises a circuit topology mapping engine, a multi-level homomorphism decision engine, a spectrum feature cooperative optimization engine and an optimization strategy adjustment unit. The application innovatively maps the circuit structure into a weighted directed graph and converts the polarity distribution problem into an optimization problem on the graph. The multi-level topology homomorphism model is adopted to realize the macroscopic, mesoscopic and microscopic representation of the circuit, thereby effectively reducing the optimization complexity. The spectrum graph theory is introduced to analyze the circuit structure, and the optimal trade-off between area and power consumption is realized through spectrum segmentation and cooperative optimization. Compared with the prior art, the search space is reduced by more than 80%, and the optimization speed is increased by 3-5 times.

The present disclosure relates to the technical field of FPGA, and discloses a LUT Pack method and device based on backend feedback-oriented optimization, which comprises: in the logic synthesis stage, generating an initial configuration file; performing a first implementation process, performing layout and wiring on the target circuit design, and collecting physical information after layout and wiring; based on the collected physical information, optimizing and updating the constraint parameters in the initial configuration file to generate an updated configuration file; taking the updated configuration file as input, performing the next iteration process until the preset convergence condition is met, and finally outputting the optimized hardware design data. By introducing a closed-loop feedback and iterative optimization mechanism based on real physical information of backend layout and wiring, the present disclosure realizes dynamic self-adaptive adjustment of the LUT packing strategy, thereby overcoming the contradiction between resource utilization rate and timing performance, and achieving a global optimization balance between area efficiency and circuit performance.

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

This invention discloses a logic synthesis mapping method based on FPGA dual-output lookup tables. First, the target circuit netlist is preprocessed and structurally normalized, mapping logic nodes to single-output lookup tables of a unified format. Then, through primitive normalization, each lookup table unit is converted into native lookup table primitives consistent with the target FPGA technology library, forming a standardized lookup table netlist. An inverted index is constructed, and candidate lookup table pairs with shared inputs are generated using index relationships. Structural and functional constraints are sequentially performed on the candidate pairs to filter out mergeable lookup table pairs. After sorting them using a resource cost function, a merge mapping is performed sequentially, concatenating them into a six-input dual-output lookup table and generating corresponding initialization parameters. This method can reduce the number of lookup tables and input pin pressure while maintaining logical functional correctness, and can be integrated as an independent optimization step into various FPGA synthesis and place-and-route tools.

This utility model discloses a conventional relay logic device for "N-to-M" signal selection. Taking "5-to-3" signal selection as an example, it mainly consists of a signal input module, a logic synthesis and judgment output module, and a signal source early warning and device fault alarm output module. The signal input module mainly consists of 5 branches; the logic synthesis and judgment output module mainly consists of 2 branches; and the signal source early warning and device fault alarm output module mainly consists of 12 branches. This utility model is used to ensure the reliability of the signal source and avoid large-scale emergency equipment operation caused by malfunctions, which could lead to losses in engineering projects. It performs "N-to-M" logic judgment on the signal source circuit. It has standardized design specifications, a wide range of applications, and can be directly installed and used. It is suitable for various hydropower and power engineering projects, as well as various industries that use "N-to-M" logic to improve signal accuracy.

An integrated circuit includes a filter circuit and a computation circuit that applies emphasis to a data stream in a frequency domain to reduce distortion to the data stream caused by the filter circuit. The emphasis is determined based on the distortion caused by the filter circuit. A circuit design system includes logic synthesis and optimization tools that relax parameters for a first filter circuit to generate relaxed parameters, use the relaxed parameters to generate a second filter circuit that filters data, generate an emphasis vector based on distortion in the data caused by the second filter circuit, and generate a computation circuit that applies the emphasis vector to the data to reduce the distortion in the data caused by the second filter circuit.

The invention relates to the technical field of integrated circuit design automation (EDA), in particular to a logic circuit comprehensive optimization method based on a graph neural network, which can be applied to a logic comprehensive stage in digital circuit design. Comprising the following steps: representing a logic circuit as a directed symbol graph G = (V, E, X, S), and generating a graph data container C1; constructing a heterogeneous graph neural network model containing alternately stacked side symbol perception GraphSAGE layers and graph isomorphic network GIN layers, and packaging the model into a model container C2; multi-layer convolution is executed, multi-scale features are fused through Dense connection, and a node embedding container C3 is generated; two tasks of node-level probability prediction and graph-level classification prediction are executed in parallel, a prediction result container C4 is output, and graph-level classification outputs selection probabilities of two optimization strategies AIG and MIG; and automatically selecting an optimization strategy according to the classification probability, executing a corresponding circuit optimization algorithm, and outputting an optimized circuit C'and an optimization report.

This invention discloses a remote verification method and system based on a multi-FPGA verification public cloud platform. The method includes: a user selecting a corresponding resource configuration module from multiple candidate resource configuration templates provided by the cloud platform; receiving the design source file uploaded by the user through an encrypted channel; performing logic synthesis, probe insertion, partitioning, mapping, and top module generation operations to complete the simulation configuration; acquiring and calling computing resources from the computing cluster; generating a bitstream file according to the simulation configuration; allocating corresponding resources from the resource pool according to the simulation configuration; configuring the switching architecture routing table; connecting the resources corresponding to the simulation configuration to build a hardware simulation execution environment; loading the generated bitstream file onto the FPGA chip allocated to the user; configuring the peripheral interface board; connecting the debugger to the peripheral and making it ready; and the user remotely logging into the debugger via a virtual network computing protocol to perform simulation and debugging operations to obtain waveform data, thus completing the remote verification.

A control signal generation circuit 5 according to one embodiment comprises: an insulated gate driver that is configured to output a control pulse signal corresponding to a common input pulse signal to first and second switching elements; a delay signal generation unit that is configured to generate at least one delay pulse signal using the control pulse signal; and a logic synthesis unit that is configured to generate first and second control pulse signals by performing different logic synthesis on two signal sets among a plurality of signal sets that are defined by the at least one delay pulse signal and the control pulse signal, wherein the first control pulse signal is different from the control pulse signal, and the second control pulse signal is different from the control pulse signal and the first control pulse signal.

The application provides a chip research and development method, system, device and storage medium, the method comprises the following steps: generating a SPEC file according to a chip architecture, and generating a register conversion circuit code according to the SPEC file; the register conversion circuit code is put into a storage server, and a register conversion circuit index is written into a resource directory; the register conversion circuit code is read based on the register conversion circuit index, and syntax checking is performed on the register conversion circuit code; and it is judged whether there is a syntax error in the register conversion circuit code; in response to the fact that there is no syntax error in the register conversion circuit code, logic synthesis is performed according to the register conversion circuit code to generate a net list, the net list is put into the storage server, and a net list index is written into the resource directory; and the net list is read based on the net list index, and formal verification and timing analysis are performed on the net list. The application can maximize resource utilization and improve research and development efficiency.

The invention discloses a control circuit of a flying capacitor multi-level step-down DC-DC converter, which belongs to the technical field of integrated circuits and comprises a phase shift circuit, a ramp signal generation circuit and a signal generation circuit. Phase shift clock signals with sequentially offset phases are output through logic operation of the logic synthesis circuit, and the duty ratio is set at the same time; the ramp signal generation circuit generates linearly-changed corresponding ramp signals according to the phase shift clock signals, and the ramp signals are connected to the signal generation circuit; the in-phase end of an error amplifier of the signal generation circuit is connected with reference voltage, the inverted end is connected with converter topology output feedback voltage, and the output is connected with the inverted end of a comparator. The in-phase end of the comparator is connected with a corresponding ramp signal, a pulse signal is output to the S end of the RS trigger after voltage comparison, the R end of the RS trigger is connected with a corresponding phase shift clock signal, and an output control signal is connected to a converter topology, so that the defects of large output voltage ripple, large switching stress and loss, EMI challenge and the like are remarkably improved.

The invention discloses an FPGA logic comprehensive netlist optimization method based on Bayesian optimization and an attention mechanism, and the method comprises the steps: converting an original netlist of a to-be-optimized circuit into a graph structure, and carrying out the optimization; performing SAT check on the optimized AIG structure, and if the output function of the main output end is consistent with the function of the initial netlist, returning to the AIG structure after execution of the optimization command; mapping the optimized AIG structure to the LUT of the FPGA for evaluation, and judging whether the requirements are met or not; calculating and predicting a sequence-result space formed by different command combination sequences by using an improved Gaussian process regression model; calculating and selecting a next command sequence with the most potential according to an adaptive sampling function; and training until performance requirements are met. The method is low in cost loss and high in search efficiency.

Machine-leaming-aided logic synthesis using do-not-care-based backpropagation, including constructing a neural network (NN) model based on a functional specification of a circuit design, training the NN model to perform a function of the circuit design, where nodes of the neural network perform a first Boolean function (e.g., AND), and where the training comprises do-not-care-based backpropagating, which may include explicitly computing target functions at fanins of the nodes. The NN may be converted to a two-input graph having nodes that represent a second Boolean function (e.g., AND). The function of the circuit design may include a multiplier function, and the graph may include an AND-inverter graph (AIG). A Boolean patch may be constructed to correct an error in the graph.

The invention is suitable for the technical field of integrated circuit design automation, and provides a logic synthesis tool mapping stage-oriented fault detection method, which comprises the following steps of: generating and preprocessing a hardware description language test program, and constructing a test program library; performing guided exploration on the mapping parameter space of the logic synthesis tool based on a Monte Carlo tree search algorithm, and outputting high-risk candidate mapping parameter configuration; submitting the candidate configuration to a logic synthesis tool to execute a synthesis process, and identifying a crash fault, a performance fault and a function fault through a multi-dimensional fault judgment mechanism combining differential simulation, log analysis and form verification; performing test program minimization processing on the confirmed fault, and feeding back fault information to the search step to optimize the subsequent search direction; and step 5, sorting and outputting a standardized fault report. According to the method, potential faults of the logic synthesis tool in the mapping stage can be efficiently and comprehensively found, and the reliability of the chip design process is remarkably improved.

The application relates to the field of integrated circuit design, and discloses a physical design method suitable for a high-performance atomic-level computing chip. The application firstly analyzes RTL code, carries out module division, and generates required memories; then carries out logic synthesis, sets up different path groups for the memory-to-register path, and gives different weights; in the layout and wiring stage, according to the algorithm function and data flow direction of each module, top layout planning, module layout planning, power supply and ground planning, layout, clock tree synthesis, wiring and design rule checking are realized; then physical verification, timing analysis, power consumption and voltage drop analysis are carried out, and through sufficient iteration optimization, it is ensured that the final design meets the timing, power consumption and voltage drop requirements. The application focuses on the physical design of the high-performance atomic-level computing chip, effectively deals with the challenges of high computing intensity, high design complexity, large chip scale and high power consumption, and improves the reliability of the chip on the basis of ensuring high performance.

The application discloses a kind of multi-agent-based Internet of Things service logic automatic generation system and method.The application constructs three agents: function implementation agent, which decomposes and implements user function intent into function demand branch;Quality implementation agent is constructed, and quality intent is instantiated based on environment evaluation to generate quality demand branch;Service logic synthesis agent is constructed, which synthesizes and detects conflicts for the two branches, and extracts and switches the conflict-free service logic scheme in real time.Through the three-layer demand model of "user intent-implementation planning-service logic", the three agents collaborate.If the service logic synthesis agent finds a conflict, the conflict information is explicitly passed to the function implementation agent for collaborative refinement until there is no conflict.The application realizes white-box and high explainability of the generation process through the three-layer model, and the multi-agent collaboration resolves hardware resource preemption conflicts at the source, significantly improving the quality of service scheduling logic.

The present disclosure relates to the technical field of digital logic design, and discloses a hierarchical incremental logic synthesis method and device for multi-module design, which comprises the following steps: establishing a node mapping relationship between an original HDL hierarchy and an original netlist hierarchy; comparing a modified HDL hierarchy with the original HDL hierarchy to identify a target module that has been changed; determining a module range and constructing an HDL sub-design for the module range; performing logic synthesis on each HDL sub-design to generate a local partial netlist; and integrating the local partial netlist into the original synthesis netlist to generate an incremental updated synthesis netlist. By establishing and utilizing the node mapping relationship between the original HDL hierarchy and the original netlist hierarchy, the present disclosure realizes accurate tracking and compatibility of the synthesizer cross-border optimization behavior, thereby fundamentally solving the inconsistency problem between the original structure and the netlist structure and ensuring the functional correctness of the incremental synthesis.

This invention discloses a collaborative method for logic structure partitioning and netlist optimization in multi-core FPGAs, belonging to the fields of electronic design automation and integrated circuits. This invention introduces physical partitioning constraints during the logic synthesis stage, establishing an interconnect-aware synthesis cost function that integrates area, timing, and cross-core interconnect costs. The method includes: pre-partitioning the netlist and anchoring its locations using a hypergraph partitioning algorithm; real-time selection and optimization operators based on dynamically adjusted interconnect penalty coefficients during logic transformation; implementation of suppression mechanisms for high interconnect cost operations; and active logic cloning and topology reconstruction for long-distance cross-core paths. This invention breaks the traditional boundaries between logic synthesis and physical partitioning, effectively reducing the number of cross-core interconnects at the source through closed-loop iteration of micro-optimization and macro-constraints, significantly reducing the risk of wiring congestion, and improving the operating frequency and performance of multi-core FPGA systems.

The invention discloses a scale-adaptive logic comprehensive optimization circuit representation learning method, and belongs to the technical field of integrated circuit design automation. Comprising the following steps: constructing circuit diagram data, and extracting node features, edge connection relationships and node depth information; a scale adaptive graph encoder is constructed, a double-layer GCN and a multi-scale feature fusion module are adopted, and scale adaptive node representation is generated through multi-hop neighborhood aggregation, circuit perception gating and attention fusion; performing hierarchical pooling based on the node depth to construct a hierarchical graph sequence; carrying out embedded coding on the optimized sequence and injecting position information to obtain sequence representation; establishing bidirectional association between a circuit structure and optimization steps through a dynamic graph-sequence adaptive interaction module, and generating a context sensing target sequence; and a Transform decoder is used for carrying out sequence modeling and predicting a quality result track. According to the method, through scale self-adaption and a dynamic interaction mechanism, the problems of representation learning and optimization dynamic modeling of a heterogeneous scale circuit are solved.

The invention discloses a logic synthesis method, device and equipment for a large-scale logic circuit, and a storage medium. The method comprises the following steps: analyzing all clock paths and gating logic in a target logic circuit to obtain a complete gating clock analysis result; splitting the target logic circuit into a plurality of sub-logic circuits, analyzing all clock paths and gating logic in each sub-logic circuit to obtain a partial gating clock analysis result, and comparing the partial gating clock analysis result with the complete gating clock analysis result; determining a missing clock path and gating logic of each sub-logic circuit, and copying the missing clock path and gating logic into each sub-logic circuit; and performing parallel synthesis on each sub-logic circuit, and integrating the comprehensive netlist results corresponding to all the sub-logic circuits to obtain a target comprehensive netlist result. According to the technical scheme of the embodiment of the invention, the problem of logic circuit gating clock conversion failure can be solved, and the accuracy of a super-large-scale logic circuit comprehensive result is improved.

The invention relates to the field of FPGA technology, and discloses an LUT Pack method and device based on back-end feedback guide optimization, and the method comprises the steps: generating an initial configuration file in a logic synthesis stage; executing a first-time implementation process, carrying out layout and wiring on the target circuit design, and collecting physical information after layout and wiring; based on the collected physical information, optimizing and updating constraint parameters in the initial configuration file to generate an updated configuration file; and taking the updated configuration file as input, executing the next iteration process until a preset convergence condition is met, and finally outputting the optimized hardware design data. According to the method, a closed-loop feedback and iterative optimization mechanism based on real physical information of back-end layout wiring is introduced to realize dynamic adaptive adjustment of the LUT packaging strategy, so that the contradiction that the resource utilization rate and the time sequence performance are difficult to consider at the same time is overcome, and global optimization balance is obtained between the area efficiency and the circuit performance.

This invention provides a reliable chip compilation environment detection method based on differential testing, comprising the following steps: S1, obtaining a seed Simulink model; S2, using an EMI mutation strategy component to mutate the seed Simulink model to obtain a mutated model; S3, using the LinUCB algorithm to train the mutated model, treating each EMI mutation strategy as one arm of a multi-armed slot machine, and outputting the trained mutated model; S4, inputting the code of the trained mutated model into the FPGA logic synthesis tool to be tested for equivalence checking, and finally outputting the defect detection result. This invention utilizes contextual information to provide an efficient way to model the dynamic adaptive selection process and improve overall testing efficiency.

This application discloses a method, electronic device, medium, and product for determining the optimal sequence of optimization operators, relating to the field of integrated circuit design technology. The method includes: in the current iteration, acquiring an initial dataset, which includes subsets of datasets from multiple stages of the logic synthesis process. At any stage, a fitting operation can be performed using the subset of datasets for that stage to obtain the distribution function for that stage. Additionally, candidate operator sequence sets for each stage can be acquired in the current iteration. Then, based on the subsets of datasets from multiple stages, the distribution function, and the candidate operator sequence sets, a new set of operator sequences can be selected from the candidate operator sequence sets to update the initial dataset, resulting in the latest dataset. When the current iteration count reaches a preset number of iterations, the optimal sequence of optimization operators is selected from the latest dataset. This approach offers high accuracy, high efficiency, and low cost.

The invention discloses a chip logic synthesis method based on meta reinforcement learning and multi-modal circuit representation, which comprises the following steps: constructing a circuit basic data set, an operator sequence data set, a pre-training data set and a reinforcement learning-logic synthesis interaction environment, the method comprises the following steps: constructing a double-layer mechanism adaptive to external loop general parameter learning and an internal loop new circuit by adopting model-independent element learning, training general parameters, and constructing a collaborative multi-stage reinforcement learning framework and a multi-near-end strategy optimization agent; the method comprises the steps of extracting structural function modal original features of a circuit, optimizing historical modal original features and scalar feature modal original features, generating a unified circuit feature representation vector through cross-modal fusion, and guiding a multi-near-end strategy optimization agent to execute whole-process optimization in combination with a delay reward function. Through multi-modal feature representation and multi-stage collaborative optimization, cross-circuit efficient migration is realized, global balance of circuit performance-power consumption-area is improved, and the problems of poor mobility and optimization splitting of a traditional method are solved.