105 results about "Logic synthesis" patented technology

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention provides a logic synthesis cutting delay prediction method based on a graph neural network, which comprises the following steps of: firstly, constructing a cutting (Cut) delay prediction data set of a logic synthesis circuit, then extracting structural and functional features of nodes in a cutting sub-graph, constructing a heterogeneous cutting level graph taking a cutting super node as a center, and finally, carrying out segmentation on the heterogeneous cutting level graph. And packaging into a graph neural network input format. Then, a delay prediction model is constructed, the delay prediction model comprises a graph neural network module and a multi-layer perceptron module, the graph neural network module extracts circuit structure features and pointer attention mechanism dynamic association standard cell library features through SAGE convolution, and enhanced cutting representation is formed; and finally, carrying out delay prediction on cutting in a new circuit by utilizing the trained model. According to the method, the cutting structure modeling capability and the delay prediction precision are effectively improved, the method can be used for optimizing a cutting selection strategy in a synthesizer, and the logic comprehensive quality is improved.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention relates to a logic comprehensive sequence optimization space exploration method and system for reinforcement learning based on reward correction, and belongs to the technical field of electronic design automation. A logic comprehensive process is embedded into a reinforcement learning algorithm based on reward correction, and the logic comprehensive process is modeled as a reinforcement learning environment; and the logic comprehensive sequence optimization space is automatically explored. A reinforcement learning algorithm is improved for a logic comprehensive scene, feature extraction and action coding are carried out, the circuit state expression precision is improved, and the search space is expanded. According to the method, by adding award correction, the exploration ability in the early stage of training is improved, a self-adaptive award function is obtained through intelligent agent training, performance reduction caused by limitation of priori knowledge on the circuit optimization direction is reduced, and a better logic comprehensive area result is obtained under the condition that delay constraints are met.

The invention provides a logic code quality inspection method and device, a server and a storage medium, and is applied to the technical field of computers. According to the method, after logic synthesis of an integrated circuit is completed, starting point registers and end point registers of all time sequence paths in the integrated circuit are extracted; counting the number of rear-stage fan-out registers and the number of front-stage fan-in registers of each register, obtaining a register number threshold value corresponding to the integrated circuit, and if the number of the front-stage fan-in registers or the number of the rear-stage fan-out registers corresponding to any register is larger than the register number threshold value, determining that the logic code of the integrated circuit is abnormal. Compared with the prior art in which the quality of the logic code is detected after layout and wiring are completed, the method provided by the invention can detect the quality of the code after logic synthesis is completed, can complete the quality detection of the logic code as early as possible, effectively avoids the situation that the logic code is found to be abnormal after all physical designs are completed, and improves the design efficiency.

The invention relates to a logic comprehensive stage delay prediction method and system based on machine learning, and belongs to the technical field of digital integrated circuit design automation. According to the method, a concept in the field of natural language processing is used for reference, a time sequence path is analogous to a sentence in a natural language processing task, and a basic element forming the sentence is called token. One time sequence path is formed by connecting a plurality of standard units and a wire net, and each token forming one time sequence path contains both the information of the standard units and the information of the wire net. The method comprises the following steps: firstly, predicting the physical size of a line network in a time sequence path by using a graph attention network, and then capturing the time sequence correlation and physical correlation of each part of the whole time sequence path by using an LSTM-Attention network. According to the method, the time sequence performance after wiring is accurately and efficiently fed forward to the logic synthesis process, so that time sequence optimization and time sequence convergence in the logic synthesis stage are guided, and the number of iterations of chip design is greatly reduced.

The invention belongs to the field of electronic design automation (EDA), and particularly provides a logic comprehensive optimization operator acceleration method, which introduces a screening strategy of a sub-circuit diagram, and improves the optimization efficiency of an operator on the premise of ensuring the optimization quality of the operator. According to the method, the sub-circuit diagrams are classified by using the graph neural network, and the sub-diagrams suitable for operator execution are screened out, so that all the sub-diagrams are prevented from being traversed, and the operator execution speed is increased; in the sub-graph screening, a screening range is set according to the execution sequence of operators, a relatively large screening range is set for the operators executed firstly so as to obtain a better optimization effect, and a relatively small screening range is set for the operators executed later so as to obtain a higher execution speed; in conclusion, the characteristic that the logic comprehensive optimization operator is continuously executed in a sequence mode is utilized, and the operator optimization efficiency is improved on the premise that the operator optimization quality is guaranteed.

The invention relates to the technical field of digital logic design, and discloses a hierarchical incremental logic synthesis method and device for multi-module design, and the method comprises the steps: building a node mapping relation between an original HDL hierarchical structure and an original network surface layer substructure; comparing the modified HDL hierarchical structure with the original HDL hierarchical structure, and identifying a target module which is changed; determining a module range, and constructing an HDL sub-design for the module range; performing logic synthesis on each HDL sub-design to generate a local department-level netlist; and integrating the local department-level netlist into the original comprehensive netlist to generate a comprehensive netlist after incremental updating. According to the method, the node mapping relation between the original HDL hierarchical structure and the original net surface layer substructure is established and utilized, so that the cross-boundary optimization behavior of the synthesizer is accurately tracked and compatible, the problem that the original structure is inconsistent with the net list structure is fundamentally solved, and the function correctness of incremental synthesis is ensured.

The invention belongs to the field of digital integrated chips, particularly relates to a clock tree generation and optimization method for quickly realizing time sequence convergence, and aims to solve the problems that an existing clock tree does not completely optimize a time sequence violation path and is difficult to realize quick time sequence convergence. The method comprises the following steps: carrying out logic synthesis on RTL codes to obtain a time sequence convergence netlist after logic synthesis; performing chip layout planning and hardware unit placement based on the time sequence convergence netlist; performing clock tree generation and clock tree comprehensive optimization on the chip with the hardware unit to obtain to-be-wired chip data with time sequence convergence; and based on the to-be-wired chip data, wiring of the to-be-wired chip is carried out according to preset parameters, and static time sequence analysis is carried out. According to the method, the frequency index of the chip is effectively optimized by combining an EDA tool, manually adjusting the clock tree structure and guiding the file, the number of iterations in the clock tree generation process and the time sequence optimization process after the clock tree generation process can be reduced, and the method is effective, reliable, convenient and practical.

The invention discloses a comprehensive method and device for optimizing a chip area, equipment and a storage medium, and belongs to the technical field of chip design. The method comprises the following steps: acquiring an original time sequence constraint and a hardware description file, wherein the hardware description file is used for describing the function and the structure of a chip circuit; amplifying a clock period in the original time sequence constraint to obtain an amplified time sequence constraint; based on the amplification time sequence constraint, executing a logic comprehensive process on the hardware description file to obtain a logic netlist, the logic netlist being used for indicating a logic structure of a chip circuit; and based on the logic netlist and the original time sequence constraint, executing a physical comprehensive process to obtain a physical netlist, the physical netlist being used for indicating the logic structure of the chip circuit and the physical position information of each circuit element in the chip circuit. By relaxing the time sequence constraint in the logic synthesis stage and using the original time sequence constraint in the physical synthesis stage, the problem of chip area increase caused by the logic synthesis stage is solved under the condition of ensuring the time sequence.

The invention provides a logic synthesis method and device of an FPGA (Field Programmable Gate Array) device. The method comprises the following steps: identifying a plurality of memory structures corresponding to a target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least: capacity information; and according to the capacity information and the quantity of various types of storage resources supported by the target FPGA device, carrying out storage resource inference on the plurality of memory structures to obtain a target storage resource type of each memory structure. When storage resource inference is carried out on a plurality of memory structures, the plurality of memory structures are not directly inferred as one type of storage resources, and then how to process the memory structures exceeding the quantity of the type of storage resources supported by the target FPGA device is considered, but in the inference process, the number of the types of storage resources supported by the target FPGA device is not considered. Therefore, the capacity information and the quantity of various types of storage resources supported by the target FPGA device are considered, and the logic synthesis time is shortened.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

The invention discloses a critical path optimization method and device and an optimization strategy determination method and device in logic synthesis. The optimization method comprises the following steps: identifying an initial key path from a comprehensive result corresponding to an RTL code, deleting a buffer tree on the path, and recording the path as a target key path; identifying abnormal path segments from all the target key paths, grouping all loads corresponding to the target signal lines on each abnormal path segment according to the obtained actual fan-out number on each abnormal path segment, copying the drivers of the target signal lines according to a copying strategy, and connecting the copied drivers with the load groups based on a preset connection strategy; and circularly executing optimization operation on all the abnormal path segments, and obtaining an optimized gate-level netlist after the path optimization operation on all the target key paths is completed. According to the method, the key path can be accurately identified, the comprehensive result is directly optimized, repeated modification and debugging on the RTL level are effectively avoided, and the efficiency of the whole design process is improved.

The invention discloses a logic synthesis method and system in a memristor memory driven by a multi-logic function set. The logic synthesis method comprises the following steps: converting an input original complex calculation function into a synthesized netlist formed by simple logic functions; introducing a composite logic function to combine the mergeable simple logic functions in the integrated netlist into the composite logic function; mapping the new netlist containing the composite logic function; and counting performance indexes in the comprehensive mapping process, comparing the performance indexes of netlist results obtained by using different state logic function sets through the same complex calculation function, and selecting the netlist result with the optimal corresponding performance index as a final output netlist result according to application scene requirements. According to the method, a plurality of simple logic function sets are integrated to obtain the netlists with different structures, the logic functions in the integrated netlists are combined to optimize and improve the in-memory calculation efficiency, and mapping results meeting different scene requirements are obtained through different selections of the results.

The invention provides a chip design method and system based on IO multiplexing performance optimization, a terminal and a medium, RTL codes are automatically generated by calling a script according to a constructed IO multiplexing information table and RTL codes of a high-speed IO output multiplexing module written in advance, and then the generated RTL codes are converted into corresponding circuits by utilizing a logic synthesis tool. The method comprises the following steps: firstly, carrying out IO (Input / Output) visualization on the basis of a chip size and a preliminary layout plan, and adjusting a position relationship between each functional module and an IO unit used by the functional module in the preliminary layout plan to obtain an optimized layout plan; and in the physically realized layout and post-layout stage, the positions of corresponding modules in the circuit are limited based on the optimized layout planning, and the input path and the output path of the functional signal are optimized to obtain a design layout. According to the method, a physical design tool can automatically realize time sequence performance optimization of function multiplexing IO, support is provided for large-scale general chips to realize a high-speed IO protocol, RTL codes can be automatically generated, manpower is reduced, and the condition of wire winding of IO signal wiring is avoided.

The application discloses a circuit input sensitivity analysis method based on Undef SAT, which comprises five steps of netlist analysis and input division, two groups of CNF clause construction, S set assignment and initial solving, first group of solution increment SAT processing and termination and result output. The method uses the incremental SAT processing mode to gradually determine the final assignment of the input variables of the L set, effectively avoids full space search, significantly reduces the search space, and improves the analysis and determination efficiency. The method constructs two groups of CNF clauses supporting irrelevant item propagation, directly processes the irrelevant input variables of the S set by using the Undef SAT solver, reduces the number of logic propagation, and thus reduces the operation time. The integrated process of the circuit input sensitivity analysis formed by the method is suitable for mainstream EDA tool chains, has good engineering applicability, and is suitable for different scenes such as logic synthesis stage, formal verification, functional equivalence checking and loop oscillation detection.

This invention discloses a functional testing device and method for trackside precision equipment in the rail transit industry. The functional testing device includes: an industrial control computer; a network switch connected to the industrial control computer; and at least one chassis containing multiple test boards, which are either A-series or B-series test boards for trackside precision equipment. The A-series and B-series boards have identical structures. The multiple test boards are communicatively connected to the industrial control computer via the network switch. The industrial control computer sends control commands to perform individual function tests and interlocking logic comprehensive tests on each test board. Its advantages are: this functional testing device can perform individual function tests and interlocking logic comprehensive tests on the test boards of trackside precision equipment; it can test the main functional modules of the test boards, ensuring complete and stable board functions and performance; simultaneously, it can perform interlocking logic comprehensive tests to test multiple test boards, improving board testing efficiency and the timeliness of reproducing board problems.

The invention discloses a structured sparse matrix multiplier realized based on FPGA primitives, and belongs to the technical field of FPGA hardware acceleration and deep learning computing architecture. The multiplier is composed of a register area and a multiplication and addition area, and the core design thought is that a circuit is built in a customized mode by directly calling bottom layer physical resources based on FPGA primitives; the register area stores a dense matrix B and supports parallel reading of elements by utilizing the characteristic that LUT in an SLICEM can be configured to be double SRL16E; the multiplication and addition area refers to a partial product generation unit based on the 4-Booth algorithm and an improved GPC (4: 2) compressor structure, and efficient generation and rapid accumulation of partial products are achieved. According to the method, redundant loss caused by high-level HDL logic synthesis is avoided through precise physical resource binding of primitives, fine wiring constraint and structured sparse data characteristic adaptation.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

The present invention discloses a method for improving the temperature immunity of digital circuits and an electronic device. The method includes: selecting standard cells for transient simulation; tracking the device current trajectory and voltage trajectory and selecting voltage sampling points; calculating the effective drive current and the temperature dependence of the device; determining the zero-temperature delay operating point; establishing a zero-temperature delay operating point database for the standard cell library and determining the zero-temperature delay operating point from the device level to the standard cell level; using the statistical average of the zero-temperature coefficient points of the standard cell library as the initial power supply voltage to complete the logic synthesis process; generating the gate-level netlist of the circuit according to the timing analysis result of the logic synthesis; performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero-temperature delay operating point for large-scale digital circuits. The present invention can alleviate the thermal effect in digital circuits and reduce the temperature dependence of electrical characteristics, and can be widely applied to the field of integrated circuit technology.

An embodiment may involve obtaining a specification of connectivity between a plurality of electronic components, a property library of logical validations, and a set of restrictions for an execution environment of the electronic components, wherein each of the electronic components is associated with at least one of the logical validations; determining that, according to properties in the property library applied to their associated electronic components, a subset of the electronic components exhibit invariance within the execution environment; based on the subset of the electronic components that exhibit invariance within the execution environment, rewiring the connectivity between the plurality of electronic components; and performing logic synthesis on the connectivity between the plurality of electronic components as rewired to simplify at least some of the subset of the electronic components that exhibit invariance within the execution environment.

The invention discloses a combination equivalence verification method based on intelligent engine selection, and the method comprises the steps: constructing Mitter circuit random simulation, extracting embedded vectors, splicing the embedded vectors into an image, inputting the image into a trained AlexNet network, carrying out the prediction to obtain an optimal scanning engine, and carrying out the equivalence verification of a candidate equivalent node pair, and after all candidate equivalent node pairs are verified and merged, performing final equivalence verification by using an SAT solver. According to the method, efficient and self-adaptive optimal scanning engine selection can be realized, when a high-XOR density circuit is processed, remarkable advantages are shown, the processing speed is greatly improved, and the verification efficiency and accuracy of equivalence verification of the two circuits can be remarkably improved. According to the method, a new research thought is provided for the design of the combination equivalence verification tool, the solving time can be remarkably shortened, the stability and adaptability of solving are improved, and the method has important practical significance in application of the logic synthesis field and development of the equivalence verification tool.

A simultaneous placement and routing based method and apparatus for incremental design optimization, and a computer device. The method includes according to a net-list file and a core constraint file acquired after logic synthesis, sequentially placing modules, each including units, on an initial coarse grid and simultaneously performing routing of each module and a placed module; performing iterative verification on placement and routing of the modules, and adjusting an illegal module and simultaneously adjusting routing of the illegal module according to a verification result, until requirements of the core constraint file are met; refining the grid, dividing each module into a plurality of sub-modules, and performing simultaneous placement and routing on the sub-modules in a refined grid; performing iterative verification and simultaneously adjusting placement and routing of illegal sub-modules; and repeating the above steps, until the iterative verification meets the requirements of the core constraint file and timing convergence.

The present application discloses a comprehensive method, apparatus, device, and storage medium for optimizing chip area, belonging to the field of chip design technology. The method includes: obtaining original timing constraints and a hardware description file, the hardware description file being used to describe the function and structure of the chip circuit; amplifying the clock cycle in the original timing constraints to obtain an amplified timing constraint; based on the amplified timing constraint, executing a logic synthesis process on the hardware description file to obtain a logic netlist, the logic netlist being used to indicate the logical structure of the chip circuit; executing a physical synthesis process based on the logic netlist and the original timing constraints to obtain a physical netlist, the physical netlist being used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit. By relaxing the timing constraints in the logic synthesis stage and using the original timing constraints in the physical synthesis stage, the problem of increased chip area caused by the logic synthesis stage is solved while ensuring timing.

A signal generation circuit according to one embodiment comprises: a delay signal generation unit configured so as to generate at least one delay pulse signal using an input pulse signal common to a first switching element and a second switching element; and a logic synthesis unit configured so as to generate a first control pulse signal and a second control pulse signal for the first switching element and the second switching element by performing different logic synthesis on two signal sets of a plurality of signal sets specified by the at least one delay pulse signal and the input pulse signal. The first control pulse signal is different from the input pulse signal, and the second control pulse signal is different from the input pulse signal and the first control pulse signal.

The embodiment of the invention discloses an information interaction method and device. According to the embodiment of the invention, after a congestion hotspot analysis instruction is received, congestion hotspot analysis is carried out on a to-be-tested gate-level netlist to determine at least one combinational logic congestion hotspot, and a to-be-modified code statement is determined in a register transfer-level code according to the combinational logic congestion hotspot; and modifying each to-be-modified code statement into a target code statement, and regenerating a target gate-level netlist according to the modified register transfer-level code. Wherein the to-be-modified code statement only supports to be converted into a combinational logic structure in the logic synthesis process, and the target code statement supports to be converted into a multiplexer structure in the logic synthesis process. Therefore, the embodiment of the invention can support a user to analyze and solve the wiring congestion problem in the logic synthesis process, so that the chip design efficiency is improved, and the negative effects of the wiring congestion problem solving process on the power consumption, the performance and the area of the formed chip are reduced.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The invention discloses a process control method and device for rear-end design of a digital chip and EDA tool software, and the method comprises the steps: firstly, carrying out RC automatic calibration on a pre-wiring database according to a design database, a reference database, a reference parasitic parameter information file and / or a preset time sequence calibration target, and then obtaining a parameter configuration file, the parameter configuration file comprises calibration configuration parameters for parasitic parameter extraction and / or time sequence values; and then loading the parameter configuration file in a logic synthesis stage, a layout stage, a clock tree synthesis stage, a wiring stage and / or an ECO stage of physical perception in a digital chip back-end design for RC extraction. According to the calibration configuration parameters, RC extraction or a time sequence value of a certain stage is used as a reference value to guide an RC engine of another stage, and then an optimized RC estimation model is used for iterative design again, so that a calibrated RC estimation or extraction model can be applied in different stages, the RC estimation and extraction precision is improved, and the design process efficiency is further improved.

The invention belongs to the field of model detection and symbol simulation, and relates to a symbol track value counting method and system based on a satisfiability model theory solver and limit model detection. The method comprises the following steps of: taking a hardware description language Chisel and a circuit specification described by extended track counting logic as input, reading the extended track counting logic through a preprocessing module, and performing logic synthesis and SMT (Surface Mount Technology) coding on a Chisel circuit; and the model detection rear-end module verifies the circuit specification based on SMT coding in combination with an STE algorithm and a BMC algorithm. According to the method, the respective advantages of the BMC and the STE are combined to enhance the solving capability of the symbol track value, the efficiency and the reliability of model detection are improved, meanwhile, the standard description capability of the STE is expanded on the Chisel level, and the verification process is greatly simplified.

Software tools, tools flows and software infrastructure to extract content and execute extracted content in hardware (termed content-computing) from a high-level language description of an application software program is disclosed. A software program for content-computing comprises: a high-level logic synthesis software to convert an identified content in an application program to a synthesized hardware image; and a language compiler software to instantiate the content customized instruction to execute in a configurable hardware unit programmed to the synthesized hardware image. A software tools flow to generate executable instructions in an application software program comprises a combined high level logic synthesis software and language compiler software to: identify an application software program content that is targeted for hardware implementation as a hardware function in a configurable hardware unit that comprises configuration memory; generate a synthesized gate-level netlist of the targeted hardware function; generate a bit-stream of configuration memory to program the targeted hardware function in the configurable hardware unit; and generate a compiled hardware instruction for a processor unit to execute the instruction in the configured hardware function.