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AT96 bus controller IP (internet protocol) core based on FPGA (field programmable gate array) and construction method thereof

A technology of a bus controller and a construction method, applied in the fields of instruments, electrical digital data processing, etc., can solve the problems of cumbersome configuration operations, low application efficiency, poor portability, etc., and achieve simple configuration operations, reduce application costs, and reduce CPU. the effect of the load

Inactive Publication Date: 2011-09-14
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the disadvantages are high cost, poor portability, cumbersome configuration operations, and low application efficiency

Method used

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  • AT96 bus controller IP (internet protocol) core based on FPGA (field programmable gate array) and construction method thereof
  • AT96 bus controller IP (internet protocol) core based on FPGA (field programmable gate array) and construction method thereof
  • AT96 bus controller IP (internet protocol) core based on FPGA (field programmable gate array) and construction method thereof

Examples

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Embodiment

[0048] figure 2 Shown is the functional block diagram of the IP core of the AT96 bus controller based on FPGA. Taking a bus read and write access through an AT96 bus controller as an example, an embodiment of the present invention will be described.

[0049] 1. The present invention is an FPGA-based AT96 bus controller IP core, such as figure 2 As shown, it is composed of AT96 bus interface module (001), AT96 bus controller state machine module (002), FIFO buffer module (003), local bus control module (004), local bus interface module (005) and functional configuration Module (006) composition, such as figure 2 As shown, the positional connection relationship and signal flow between them are as follows. a) One end of the AT96 bus interface module (001) is connected to the AT96 bus interface card, and the other end is connected to the AT96 bus controller state machine module (002), which receives data and control signals from the AT96 bus or sends data and control signals On the ...

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Abstract

The invention relates to an AT96 bus controller IP (internet protocol) core based on an FPGA (field programmable gate array), which comprises an AT96 bus interface module, an AT96 bus controller state machine module, a FIFO (first in, first out) cache module, a local bus control module, a local bus interface module and a function configuration module, wherein one end of the AT96 bus interface module is connected to an AT96 bus interface card while the other end is connected to the AT96 bus controller state machine module; the AT96 bus controller state machine module is connected to the FIFO cache module; the FIFO cache module is connected to the local bus control module; the local bus control module is connected to the local bus interface module; and the function configuration module is connected to later four modules. A construction method for the AT96 bus controller IP core based on FPGA comprises the following six steps: 1) design input; 2) function simulation; 3) logic composition; 4) pre-simulation; 5) a table file output; and 6) an IP core calling module output.

Description

1. Technical Field [0001] The invention relates to the application of interconnection of communication single boards through an AT96 bus interface, in particular to an FPGA-based AT96 bus controller IP core and a construction method thereof, and belongs to the technical field of communication equipment design and application. 2. Background technology [0002] In order to apply the AT96 bus PC to the harsh industrial environment, the German SIEMENS company initiated the development of the AT96 bus European card standard (IEEE996) in 1994, and it has been promoted and applied in Europe. AT96 bus = AT96 bus electrical specification + 96-pin pinhole connector + European card specification (IEC297 / IEEE 1011.1). The AT96 bus industrial computer eliminates the edge gold finger connection between the modules, and has the ability to resist strong vibration and shock; its 16-bit data bus, 24-bit addressing capability, high reliability and good maintainability are more suitable for harsh in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/20G06F13/24
Inventor 陈娟祁晓野马俊功王德义付永领
Owner BEIHANG UNIV
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