31 results about "Logic simulation" patented technology

The invention relates to the technical field of software simulation operation simulation, and discloses a software logic simulation operation control method and system in an audio processor. The control method is applied to logic simulation operation control equipment and specifically comprises the following steps that S101, an audio processor simulation operation request sent by a user side is received, a graphical user interface is generated according to the operation request, and the graphical user interface comprises a logic module list area, a design editing area, an attribute bar and an information display area; and the user side drags an icon of a logic circuit element from the logic module list area to the design editing area. Through a highly integrated graphical interface and intelligent interactive design, the design and simulation efficiency of an audio processor logic circuit is remarkably improved, and by adopting a'drag-and-generate 'module instantiation mechanism, an attribute bidirectional real-time synchronization technology and visual connection and signal type inspection, the reliability of the audio processor logic circuit is greatly improved. Therefore, the user can intuitively and quickly construct the complex circuit topology, and the professional threshold is greatly reduced.

The invention relates to the technical field of chip simulation, in particular to a voltage logic simulation design method and system for a passive internet-of-things tag chip. The method comprises the following steps: performing energy characteristic measurement on the tag chip, and calculating voltage fluctuation and logic gate triggering probability to obtain energy logic state mapping data; state transition probability distribution mapping is carried out according to the energy logic state mapping data, and a transition probability distribution tensor is constructed; collecting measurement environment parameters in the energy characteristic measurement process, and performing dynamic environment interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; carrying out simulation precision demand distribution based on the interference compensation distribution tensor, and constructing a layered simulation configuration file; and performing multi-precision parallel simulation execution based on the layered simulation configuration file, and generating a probabilistic verification report. Through precise and efficient logic simulation, the reliability of chip design is improved, and the fault probability is reduced.

The embodiment of the invention discloses a virtual-real linkage experiment system based on digital twinning. The virtual-real linkage experiment system comprises hardware experiment equipment and computer equipment for operating a virtual simulation platform. The hardware experiment equipment comprises a simulator and a plurality of pluggable function modules. And the simulator is in communication connection with the virtual simulation platform through a computer equipment communication interface and communicates with each functional module. And the virtual simulation platform runs the virtual simulation model, receives an operation instruction input by a user through the computer equipment input assembly, performs logic simulation, updates the simulation state of the virtual simulation model, generates simulation state information and sends the simulation state information to the simulator. The simulator converts the simulation state information into a driving signal, drives the corresponding function module to update the physical state, and collects the physical state of each function module to obtain physical state information. The physical state is generated by operation of a user on the corresponding functional module or by the functional module responding to the driving signal. And the virtual simulation platform updates the simulation state of the virtual simulation model according to the physical state information.

The invention provides a chip design verification method and system, electronic equipment and a storage medium. The chip design verification method comprises the following steps: acquiring a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from a plurality of collaborative verification modes; wherein the cooperative verification mode comprises a mode for verifying the design file through cooperation between logic simulation verification and form verification; the collaborative verification modes corresponding to different design stages are different, and the collaborative modes between logic simulation verification and form verification in the different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. According to the method, logic simulation verification and formal verification work cooperatively, and respective advantages are combined for complementation, so that the efficiency and effectiveness of chip design and verification are improved.

The application relates to a relay protection misoperation root cause analysis method, device, equipment, medium and program product. The method comprises the following steps: in response to detecting a relay protection misoperation event, acquiring a corresponding observation data set; extracting and locking an exogenous noise vector of the relay protection misoperation event by inverse operation of a mixed driving structure equation; calculating average causal effects of each environmental state variable on relay protection action behavior, and generating a root cause quantitative analysis result according to the average causal effects; receiving an intervention operation instruction input by a user for a target environmental state variable, keeping the locked exogenous noise vector unchanged, inputting the modified target environmental state variable into a structural causal model, performing forward prediction and waveform synthesis through a mixed deduction engine, generating a virtual fault waveform and corresponding relay protection logic simulation results; and comparing the time domain waveform and the action logic to generate a comparison result. The method can quickly reproduce an accident scene and quantitatively locate a misoperation root cause.

This invention relates to the field of logic simulation and decision support for nuclear power units, and particularly to a lightweight simulation analysis system and method for the consequences of power outages in nuclear power units. The system includes an electrical node module, a logic judgment module, and a simulation analysis module. The electrical node module constructs an electrical node model and defines the attributes and electrical logic relationships of the electrical nodes. The logic judgment module performs logical judgments to determine the state of the electrical nodes. When the simulation analysis module receives a power outage signal from an electrical node, it queries the downstream electrical nodes of the out-of-power node and transmits the power outage signal to the downstream electrical nodes. It then performs logical judgments on the out-of-power node and the downstream electrical nodes, and provides the power outage status of the downstream electrical nodes based on the judgment results. This invention uses the simulation analysis module to simulate and analyze power outage faults in nuclear power plants. Authorized users can perform simulation operations via the Internet, improving the flexibility and efficiency of the simulation system.

The application discloses an elevator software electronic simulation test system, the test object includes elevator logic control software and elevator drive software, wherein data exchange is carried out between the elevator logic control software and the elevator drive software, the elevator simulation test device includes an elevator logic simulation subsystem and a motor drive simulation subsystem, wherein the motor drive simulation subsystem includes a PWM sampling module, a frequency converter DC bus voltage estimation module, a motor power estimation module, an elevator load simulation module, a motor simulation module, an encoder simulation module and other output interface modules and the like. The simulation test system collects the data of the PWM output waveform of the elevator drive software, the data of I / O interfaces such as a brake resistor and a fan, simulates the running state of the elevator and the motor in a pure software mode, realizes the simulation of the motor rotating speed, position and current and the like, connects the simulation result into the elevator drive software, and thus realizes the test on the elevator drive software.

The application belongs to the technical field of electric power storage, and discloses a power warehouse operation simulation and bottleneck diagnosis system based on digital twinning. A multi-source perception architecture is constructed through an acquisition and adaptation module, covering full-factor data such as equipment operation and personnel operation. Combined with a five-dimension fusion model of a twinning modeling module and a laser scanning modeling technology, the physical space and operation logic of the power warehouse are accurately restored. A simulation and deduction module adopts a fusion simulation algorithm and a double-scene template library to realize linkage simulation of the whole process and control instructions of warehousing, storage, picking, and delivery, can simulate the operation state under different scenes, and avoid efficiency problems such as equipment waiting and path redundancy in advance. A bottleneck diagnosis module constructs a three-dimension evaluation system of operation state, control parameters, and equipment performance, integrates real-time working condition data and simulation analysis results, scientifically distributes index weights through an analytic hierarchy process, and realizes quantitative division of bottleneck grades.

This application relates to the interdisciplinary field of artificial intelligence and reliability systems engineering, and provides a method and apparatus for intelligent generation of equipment fault behavior logic models based on LLM (Limited Linear Modeling). This method combines a vector database to achieve enhanced retrieval, constructs an agent-based framework for generating equipment fault behavior logic models, and then generates structural elements in the agent for each business component involved in the equipment fault behavior logic. Based on the model structure, the results are integrated and merged, ultimately achieving a complete and runnable equipment fault behavior logic simulation model. This method integrates the interactive modeling capabilities of agents with the semantic understanding and logical reasoning capabilities of large language models, enabling intelligent generation of fault behavior models for complex equipment and effectively improving the generation efficiency of equipment fault behavior models.

The application provides a chip design verification method, system, electronic equipment and storage medium. The chip design verification method comprises: obtaining a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from multiple collaborative verification modes; wherein the collaborative verification mode comprises a mode of verifying the design file by cooperation between logic simulation verification and formal verification; the collaborative verification modes corresponding to different design stages are different, and the cooperation modes between logic simulation verification and formal verification in different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. The method makes logic simulation verification and formal verification work collaboratively, combines their respective advantages for complementation, so as to improve the efficiency and effectiveness of chip design and verification.

The invention discloses a method for calculating overvoltage of an offshore wind power power frequency and low frequency hybrid power transmission system, which comprises the following steps: establishing an electromagnetic transient simulation model of the offshore wind power power frequency and low frequency hybrid power transmission system, selecting typical working conditions of the offshore wind power power frequency and low frequency hybrid power transmission system, and calculating the overvoltage of the system according to a control protection strategy of the system; correct action logic is set for key equipment in the system, overvoltage waveforms of key positions of the system are obtained through simulation calculation, representative overvoltage and corresponding working conditions of the key positions of the system are obtained after all working conditions are summarized, and a guidance basis can be provided for insulation cooperation design of offshore wind power power frequency and low frequency hybrid power transmission projects.

A verification method for an integrated circuit according to an embodiment includes: acquiring circuit operation information of an integrated circuit to be verified by a logic simulation; and analyzing the circuit operation information and extracting a verification set. The verification method according to the embodiment further includes verifying a logical operation of a location where clock domains are crossed for the verification set for each inter-flip-flop.

The present application relates to avionics ground test, photoelectric load production debugging technical field, especially to a kind of photoelectric load ground detection and avionics simulation system and method based on FC point-to-point, with simulation control host computer as core, replace complex exchange avionics network by FC point-to-point direct connection, under the condition of no real avionics equipment, no switch, the behavior of avionics node required by photoelectric load, communication timing and instruction logic are completely simulated, to simplify the physical connection logic simulation complete complex avionics network to the whole communication behavior of photoelectric load, while through image acquisition module real-time recycling image or video data stream, realize control flow+image or video data stream double closed loop.The system supports test configuration, instruction sending, data monitoring, record playback, automatic criterion, fault location and test report generation, constitute complete photoelectric load ground detection system.

The invention discloses a universal asynchronous receiver / transmitter (UART) digital logic simulation architecture system based on VerilogHDL. The system comprises a demand module, a test case TESTCASE module, an instruction model CMDMOD module and an asynchronous serial port model UARTMOD module. The UART digital logic simulation architecture based on VerilogHDL is established, the problems that an existing UART simulation architecture is single in application scene and needs to be continuously modified to be suitable for various application scenes of various items are solved, the UART simulation architecture is suitable for various application scenes of various items through parameter transmission and analysis, and the simulation verification efficiency of various application scenes of UART of various items is improved.

The invention discloses a power distribution network co-jump risk identification and early warning method based on multi-source data fusion, and the method comprises the steps: collecting operation data in real time from a plurality of heterogeneous data source systems of a power distribution network; preprocessing the collected multi-source data to form a standardized data sequence with a unified time scale; extracting a multi-dimensional feature index based on the standardized data sequence; constructing a same-hop risk identification model based on machine learning, fusing the multi-dimensional feature indexes, calculating to obtain a comprehensive same-hop risk probability value, and delimiting a risk level according to a numerical value interval; when the risk level reaches or exceeds a preset intermediate risk threshold value, load flow calculation and protection logic simulation are carried out, and a potential cascading failure development path is predicted; and generating early warning information according to the risk level and the predicted fault path, and pushing the early warning information to a power distribution network dispatching system. Through deep combination of multi-source data fusion and a machine learning technology, leap-type improvement of the same jump risk identification and early warning capability of the power distribution network is realized.

A method for providing power analysis of a circuit comprises estimating output power during a time interval for a gate of the circuit based on an input event; and including the estimated output power of the gate in the power analysis of the circuit. In some implementations, estimating output power includes considering, for the gate, an “output timing reject region” of the input event in which a pulse width at the input is between two thresholds, the thresholds being selected such that the input event does not propagate to an output of the gate. Nevertheless, the input event contributes partially to the estimated output of the gate. In some implementations, estimating output power includes implementing a live gate model using gate datasheet information stored by the gate.

The application discloses a transaction-based data logic simulation system, which comprises an upper computer and a digital logic simulation device; wherein the upper computer is coupled with the digital logic simulation device and is used to send a design under test (DUT) and a simulation instruction to the digital logic simulation device; the digital logic simulation device receives and loads the design under test and receives the simulation instruction, generates simulation excitation data based on the simulation instruction, applies the simulation excitation data to the design under test to obtain a simulation result, compares the simulation result with a preset simulation result to obtain a comparison result, and sends the comparison result to the upper computer. The application solves the technical problem of low digital logic simulation efficiency in the prior art.

The present application relates to avionics ground test, photoelectric load production debugging technical field, especially to a kind of photoelectric load ground detection and avionics simulation system and method based on FC point-to-point, with simulation control host computer as core, replace complex exchange avionics network by FC point-to-point direct connection, under the condition of no real avionics equipment, no switch, the behavior of avionics node required by photoelectric load, communication timing and instruction logic are completely simulated, to simplify the physical connection logic simulation complete complex avionics network to the whole communication behavior of photoelectric load, while through image acquisition module real-time recycling image or video data stream, realize control flow+image or video data stream double closed loop.The system supports test configuration, instruction sending, data monitoring, record playback, automatic criterion, fault location and test report generation, constitute complete photoelectric load ground detection system.

The invention discloses a relay protection device logic simulation model standardization module modeling system and method, particularly relates to the technical field of relay protection simulation modeling, and is used for solving the problem of insufficient simulation model fidelity caused by complex implicit logic coupling between standardization function modules in an existing modularization modeling method. The method comprises the following steps: acquiring standardized function modules of a target device and an initial combination connection relationship thereof, identifying all cross-module interaction paths, evaluating fault characteristics of the cross-module interaction paths to generate an interaction strength map, identifying a high-coupling risk path, applying directional excitation to the high-coupling risk path, and simulating the high-coupling risk path; whether path interaction abnormity triggered by implicit logic dependence exists or not is analyzed and detected through causal inference, finally, according to an abnormity generation behavior constraint rule, the abnormity generation behavior constraint rule, a module and a connection relation are packaged together, a high-fidelity standardized combined simulation model is formed, unexpected interaction behaviors in a module combination are effectively found and constrained, and the simulation efficiency is improved. And the accuracy of the protection device model and the reliability of action logic reproduction are improved.

The invention relates to the technical field of artificial intelligence and reliability system engineering crossing, and provides an LLM-based equipment fault behavior logic model intelligent generation method and device. The method combines a vector database to realize enhanced retrieval, constructs an equipment fault behavior logic model generation framework based on an intelligent agent, then generates structural elements in the intelligent agent one by one for business components involved in equipment fault behavior logic, and completes integration and combination of results based on a model structure. And finally, a complete and operable equipment fault behavior logic simulation model is realized. According to the method, the interactive modeling ability of the intelligent agent and the semantic understanding and logical reasoning ability of the large language model are fused, intelligent generation of the fault behavior model of the complex equipment is realized, and the generation efficiency of the equipment fault behavior model is effectively improved.

The present invention provides a verification method, verification apparatus, program, and storage medium that can suppress the occurrence of false errors in integrated circuits including CDC locations. [Solution] The verification method for an integrated circuit according to the embodiment comprises the steps of acquiring circuit operation information of the integrated circuit to be verified by logic simulation, and analyzing the circuit operation information to extract verification combinations. The verification method according to the embodiment further comprises the step of verifying the logic operation of the verification combinations that span clock domains for each flip-flop.

The invention discloses a multi-path 2711 digital logic simulation architecture system based on Verilog HDL (High Definition Language). The multi-path 2711 digital logic simulation architecture system comprises a demand module, a test case TESTCASE module and a 2711 model 2711 MOD module, according to the invention, the multi-path 2711 digital logic simulation architecture based on Verilog HDL is established, the problems that the application scene of the existing 2711 simulation architecture is single and needs to be continuously modified to be suitable for various application scenes of each project are solved, the multi-path 2711 digital logic simulation architecture is suitable for various application scenes of each project through parameter transmission and analysis, and the simulation verification efficiency of each project about various application scenes of 2711 is improved. According to the multi-path 2711 digital logic simulation architecture based on VerilogHDL, adaptive modification of requirements can be completed on a TESTCASE layer of a test case according to the requirements, and a lower-layer 2711 model 2711MOD does not need to be modified, so that the applicability of the lower-layer 2711 model 2711MOD is higher, and the application is more flexible.

The application relates to the field of computer simulation and automatic control technology, and discloses a complex system launch control logic simulation and verification method.The method comprises the following steps: fusing multi-source flight states, environment perception and task information to construct a multi-dimensional state space representation; outputting candidate control rules through a logic generation model fused by a graph neural network and an attention mechanism; carrying out double verification by combining formal semantic checking and safety reachability analysis; after verification, smoothly deploying new logic in an isolated sandbox, and online fine-tuning the model based on execution feedback.The system comprises five modules, namely, multi-source data fusion, logic generation, formal verification, logic deployment and monitoring and updating.The application realizes dynamic evolution and safety closed-loop optimization of launch control logic, and significantly improves the task continuity and control reliability of a complex system under non-expected working conditions.

The invention discloses a fault injection test case screening method and device based on fault detectability analysis, and aims to solve the problems of blindness and low efficiency of existing screening. The method comprises the steps of firstly defining a fault injection range and generating a full-quantity fault set, extracting a dynamic behavior portrait of a test case through fault-free gate-level logic simulation, and identifying a static region register set; performing structure detectability analysis on the full-amount fault set under unconstrained and static region conversion structure constraints respectively; quantifying irreplaceability of the test case to fault detection through differential analysis, and fusing a multi-dimensional coverage rate index and time cost to obtain a sorting score; and finally, screening out an optimal test case subset through a greedy algorithm by using a combinatorial optimization model with budget constraint. According to the method, a large amount of fault injection simulation is not needed, the screening time is remarkably shortened, the fault coverage rate is improved, the computing resource overhead is reduced, and the method is suitable for functional security verification of a high-reliability chip.

The invention provides a wind power conversion controller hardware-in-the-loop joint simulation test platform. The wind power conversion controller hardware-in-the-loop joint simulation test platform comprises an RT-LAB real-time simulation subsystem, a wind power conversion controller and a PLC industrial simulation subsystem. The RT-LAB real-time simulation system simulates and realizes electromagnetic transient simulation of a converter main circuit, a motor and a power grid, and the PLC industrial simulation system simulates and realizes peripheral industrial communication and peripheral logic simulation of a converter controller, so that a controller closed-loop test environment under a dual-simulation system collaborative architecture is formed. The method has the beneficial effects that the wind power conversion controller works in a fan system environment close to the reality, and a complete signal system of the converter in actual operation is restored to the maximum extent by improving the simulation coverage rate of a hardware interface and the precision of a test model; united closed-loop verification of the wind power conversion controller under a high-precision electrical environment and a real industrial communication protocol is realized, and the consistency of hardware-in-loop simulation operation of a controller product and actual prototype operation is ensured.

The invention discloses a transaction object instantiation method and system based on a virtual pre-execution model and atomization anchor point implantation. The method comprises the following steps: constructing a source data container supporting a Web DOM and a graphic engine; executing memory sandbox rehearsal of an application layer, and constructing a virtual model in a server-side memory to carry out logic simulation independent of a database; and after the verification is passed, creating a transaction object, and reconstructing an original node into an atomization interaction anchor point. Meanwhile, dynamic permission fusing is achieved through environment fingerprints and a rendering pipeline interceptor, and on the premise that the integrity of memory data is kept, mask replacement is only conducted on sensitive data in the view drawing stage. According to the method, the problem of data fault is effectively solved, dirty data caused by tentative writing is eliminated, and safe decoupling of data transmission and visual rendering is realized.

The present disclosure relates to a vehicle function test system, a test method, a medium and a cloud device, and relates to the technical field of testing. The test system comprises a cloud service module configured to manage information required when testing a target function of a vehicle; and a simulation service module configured to simulate software logic of an entity resource and test the target function through information interaction with the cloud service module. The simulation service module is configured to execute a software execution process of the software logic simulation related to the entity resource, so as to replace the interaction between the entity resource and the cloud service module, improve the test efficiency of the target function of the vehicle, and reduce the entity resource cost when testing the target function without the participation of the entity resource.

This application relates to a method, apparatus, computer device, and storage medium for simulating gate-level logic. The method includes: preprocessing a logic cell library of the simulation circuit to obtain a logic extended state table; performing parallel analysis on the simulation circuit according to a preset processing algorithm to obtain a target parallel computing scheme; and performing simulation based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation result. This method enables flexible and universal parallel gate-level logic simulation, saves simulation computation costs, and accelerates the execution efficiency of parallel computing.

This invention discloses a method for calculating transistor aging stress based on an analytical model. It is an analytical formula automatic generation method applicable to transistors with aging mechanisms of bias temperature instability (BTI) and hot carrier degradation (HCD). The analytical model of this invention calculates the stress of the internal transistor based on statistical dynamic information such as duty factor (DF) and toggle rate (TR) obtained from gate-level simulation. The analytical formula used is automatically generated through transistor-level logic simulation and supports stress analysis for different aging mechanisms.

The invention discloses a spare power automatic switching logic simulation system and method, and relates to the technical field of spare power automatic switching. The system is composed of a spare power automatic switching device, a simulation system power supply module, a protection information background simulation module, a first bus and first switch simulation module, a second bus and second switch simulation module, an interconnection switch simulation module and other switching value simulation modules. The invention further provides a simulation method. The spare power automatic switching device is combined and connected with each simulation module, the running conditions of the spare power automatic switching device and the control switch thereof are simulated, the simulation control of the spare power automatic switching logic is realized, a test platform is provided for the verification of the spare power automatic switching logic, risks and economic losses caused by direct application of the spare power automatic switching logic to field tests are reduced, and the test efficiency is improved. And the method can be used for practical operation training of operation and maintenance personnel, thereby reducing manpower training cost.