System and method for verifying embedded memory controller based on assertion

Abstract

The invention discloses a system and a method for verifying an embedded memory controller based on assertion, and relates to the field of logic verification of integrated circuits. The verification system mainly comprises a DUV code analysis and extraction unit (1), a verification assertion and excitation generation unit (2) and a comprehensive verification unit (3). A verification assertion code and an excitation generation code can be efficiently generated in combination with a verification assertion bank and an excitation generation bank of the memory controller by automatically analyzing and extracting a DUV design code, verification codes can be simultaneously applied to a simulation verification method and a formal verification method, and automatic loadable verification of the UDV design can be realized in the comprehensive verification unit, so the verification efficiency is improved. Compared with a conventional method adopting independent logic simulation verification, the method disclosed by the invention has many advantages in verification efficiency, coverage rate and the like.

Description

technical field [0001] The invention relates to the field of integrated circuit logic verification, in particular to an assertion-based embedded memory controller verification system and method. Background technique [0002] With the continuous increase of integrated circuit design scale, the type and capacity of embedded memory are also increasing, and the verification of memory controller has become an important part of chip design. In particular, the functional verification of memory controllers with complex control protocols and large storage capacity has become the focus of some design verification work. To achieve high-coverage verification requires a lot of manpower and time. There are two problems in the functional verification of this type of logic relying solely on logic simulation: one is that the increase in the design scale leads to a huge amount of simulation test stimulus data, and the time and labor costs of logic simulation also increase exponentially; Ver...

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Problems solved by technology

In particular, the functional verification of storage controllers with complex control protocols and large storage capacity has become the focus of some design verification work. To achieve high coverage verification, a lot of manpower and time are required

There are two problems in the functional verification of this type of logic relying solely on logic simulation: one is that the increase in design scale leads to a huge amount of simulation test stimulus data, and the time and labor costs of logic simulation also increase exponentially; Verification completeness is difficult to get an accurate judgment

However, in the traditional embedded storage controller verification method, it is necessary to manually design the verification assertion code for each storage controller in the DUV design, and write the verification stimulus file. increase

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