30 results about "RapidIO" patented technology

The invention discloses a high-performance CPU-GPU (Central Processing Unit-Graphics Processing Unit) cooperative processing architecture of an audio frequency integrated signal processor, belonging to the technical field of audio frequency integrated signal processing, the architecture is based on a dynamic priority scheduling model and realizes efficient collaboration of a CPU and a GPU through hierarchical resource management and protocol level optimization, a hardware layer adopts a multi-GPU cluster and a distributed storage node, and the CPU-GPU cooperative processing architecture has the advantages that the multi-GPU cluster and the distributed storage node are integrated; high-concurrency task processing is supported; the transmission layer fuses RapidIO and an Ethernet protocol, and adapts to a short frame control signal and a long packet data stream respectively; and the application layer calculates task resource demands through dynamic priority weights, and ensures low time delay of key tasks in combination with a normalized allocation algorithm. According to the architecture, in an audio signal processing scene, the task scheduling efficiency is improved by 40%, the short frame transmission delay is as low as 0.5, the throughput of a long data stream reaches 100 Gbps, and the requirements for real-time performance and calculation precision in a complex acoustic environment can be met.

The invention provides an audio frequency integrated signal processing system based on a VPX architecture, and the system comprises a case which accords with the OpenVPX standard and is internally provided with a backboard, and the backboard is integrated with a high-speed serial RapidIO bus and an Ethernet interface; the plurality of heterogeneous computing board cards are connected into the case through VPX slots, the board cards are in point-to-point communication through high-speed serial RapidIO buses, and the heterogeneous computing board cards comprise different types of computing chips and execute different types of audio signal processing tasks; and the multi-machine stacking expansion module is connected with the case through a backboard Ethernet interface, and is connected with an external processor through the backboard Ethernet interface to carry out distributed calculation when it is detected that the calculation capability of any heterogeneous calculation board card cannot meet the audio signal processing requirement. By implementing the scheme, the overall signal processing efficiency of the system can be improved, and the error-tolerant rate and reliability of the system can be improved.

The present invention discloses a high-speed real-time transmission implementation system and method based on the RapidIO protocol, comprising a data exchange module that is simultaneously connected to a source device and a destination device, the data exchange module comprising an FPGA chip, the source device and the data exchange module exchanging data via a serial transceiver, the data exchange module and the destination device exchanging data via a RapidIO interface, and the serial transceiver and the RapidIO interface both being connected to the FPGA chip via a cache module. The system of the present invention is highly flexible, highly scalable, and easy to transplant. The present invention can increase or decrease the interface between the source device and the data exchange module FPGA, and the interface between the data exchange module FPGA and the destination device according to system requirements, and adjust the data transmission bandwidth by increasing or decreasing the interface. The present invention takes into account both high bandwidth and real-time performance, adopts multi-channel transmission, increases the transmission speed, and improves the transmission efficiency.

The utility model belongs to the field of avionics, and relates to a data acquisition management processor integrating multi-type data acquisition and storage. Comprising a power conversion module, a flight parameter acquisition module, a task processing module, a 1394B bus module, an FC network monitoring module, a video acquisition module, a maintenance data card and an information data card. The power failure indication output end of the power supply conversion module is connected with the IO port of the task processing module; the lighting signal input end of the power supply conversion module is connected with the other IO port of the task processing module; the flight parameter acquisition module is connected with one SRIO port of the task processing module through an SRIO bus; the 1394B bus monitoring module is respectively connected with three PCIe ports of the task processing module through three paths of independent PCIe buses; the FC network monitoring module is connected with the other PCIe port of the task processing module through a PCIe bus; the video acquisition module is connected with a RapidIO port of the task processing module through a RapidIO bus; and the maintenance data card and the information data card are respectively connected with the PCIe bus interface of the task processing module.

The invention provides a DMA (Direct Memory Access) controller, a control method and a bridging chip. The controller comprises a PCIe (Peripheral Component Interconnect Express) splitting and combining processing module, a WDMA processing module, a control and state register, a doorbell processing module and a RapidIO splitting and combining processing module, the PCIe splitting and combining processing module is connected with the WDMA processing module and the control and state register; and the RapidIO splitting and combining processing module is connected with the WDMA processing module and the doorbell processing module. The WDMA processing module is used for reading to-be-sent data on the PCIe side, assembling a RapidIO write request according to the descriptor information, and sending the RapidIO write request to an opposite side device connected with the RapidIO controller; the control and state register is used for controlling behaviors of the WDMA processing module and storing necessary information; and the doorbell processing module is used for generating and sending a doorbell data packet and processing doorbell response. According to the scheme, the doorbell is automatically triggered after hardware finishes data migration, so that a plurality of links of software processing are omitted, the speed is higher, and the burden of a CPU (Central Processing Unit) is relieved.

The application provides an audio integrated signal processing system based on a VPX architecture, which comprises: a case conforming to an OpenVPX standard, wherein a backboard is arranged in the case, the backboard is integrated with a high-speed serial RapidIO bus and an Ethernet interface; a plurality of heterogeneous computing board cards are connected to the case through VPX slots, the board cards are in point-to-point communication through the high-speed serial RapidIO bus, the heterogeneous computing board cards contain different types of computing chips and perform different types of audio signal processing tasks; and a multi-machine stacking expansion module is connected to the case through the Ethernet interface of the backboard, when it is detected that the computing capacity of any of the heterogeneous computing board cards cannot meet the audio signal processing demand, an external processing machine is connected through the Ethernet interface of the backboard to perform distributed computing. Through implementation of the scheme, the signal processing efficiency of the whole system can be improved, and the fault tolerance and reliability of the system are improved.

This application provides a fault detection and handling method for RapidIO switching networks, belonging to the field of embedded computer technology. Specifically, it includes several RapidIO service nodes, a dual-redundant RapidIO system management node, and a RapidIO switch. The RapidIO system management node connects to the RapidIO switch and the RapidIO service nodes through an independent RapidIO system management bus interface. The two RapidIO system management nodes employ a master / slave switching strategy to determine the master node. Master and slave determination is performed upon power-up, and master / slave checks are periodically performed during operation. After determining the RapidIO system management master node, it performs the detection and handling of RapidIO switching network faults. This application's solution effectively prevents the spread and deterioration of RapidIO switching network faults.

The application discloses a kind of high-performance CPU-GPU collaborative processing architecture of audio integrated signal processor, belong to audio integrated signal processing technical field, this architecture is based on dynamic priority scheduling model, through hierarchical resource management and protocol level optimization, the efficient cooperation of CPU and GPU is realized, hardware layer uses multi-GPU cluster and distributed storage node, support high concurrency task processing;Transport layer fuses RapidIO and Ethernet protocol, respectively adapts short frame control signal and long packet data stream;Application layer calculates task resource demand by dynamic priority weight, and combines normalization allocation algorithm to guarantee the low latency of key task.The architecture in the scene of audio signal processing, task scheduling efficiency is improved by 40%, short frame transmission delay is as low as 0.5, long data stream throughput reaches 100Gbps, can satisfy the real-time and calculation accuracy demand under complex acoustic environment.

The application discloses a RapidIO link configuration system, method and medium, and belongs to the field of spaceflight TT&C (Tracking, Telemetry and Command), and comprises the following steps: firstly, a central node configures the routing between any two nodes connected through a RapidIO switching network; and secondly, a FPGA receiving node configures the link of a communication node related to the FPGA receiving node and the link of the FPGA receiving node itself. The application provides a simple and reliable RapidIO link configuration scheme with high flexibility and capable of reducing the coupling relationship between the central node and the leaf node.

The invention belongs to the technical field of computer bus interfaces, and particularly relates to a PCIe-to-RapidIO protocol conversion method and device and application. Comprising the following steps: receiving a transaction request from a PCIe end; dynamically calculating an optimal fragmentation strategy according to the initial address, the transmission data length and the effective byte indication, and outputting a fragmentation descriptor; according to the fragmentation strategy, carrying out segmentation or recombination on transmission data, and generating a corresponding RapidIO protocol packet header for each RapidIO data packet; and the plurality of packaged RapidIO data packets are sent to a RapidIO end. According to the invention, the number of data packets required by protocol conversion is reduced, and the bus overhead and transmission delay are reduced, so that the overall throughput and efficiency of a cross-protocol interconnection system are improved.

The application discloses a data exchange device for network interface equipment and SRIO interface equipment, which comprises a main chip and a network exchange chip, the main chip adopts an FMQL45T900 chip, and a processor system PS and programmable logic PL are integrated in the chip, wherein the processor system PS is connected with the network exchange chip to realize data intercommunication between various external terminals with network interfaces; the programmable logic PL constitutes an SRIO exchange network to realize physical SRIO intercommunication between various main chips and data intercommunication between various external terminals with RapidIO high-speed serial ports; and the network exchange chip adopts an SF2507 chip to realize gigabit network exchange function of a network port. The application realizes data interaction between the network interface equipment and the SRIO interface equipment, and widens the application range of the data exchange device.

The invention provides an IO core grain NoC network node high-speed interface circuit based on RISC-V. The IO core grain NoC network node high-speed interface circuit comprises PCIe, RapidIO, a DDR and a configuration management unit. The configuration management unit comprises an RISC-V instruction core, a CROSSBAR bus, a configuration unit and an AXI 1to6 conversion bridge; the configuration unit comprises an AXI one-to-six conversion bridge and a plurality of configuration bridges; and an AXI interface output by the CRO SSBAR bus is subjected to one-to-six processing. Through the innovative design that the configuration bridge unit is additionally arranged between the RISC-V core and the interface IP, efficient initialization configuration of IO equipment is achieved.

The application discloses a complex electronic system RapidIO link quality guarantee method, device, medium and system, belongs to the field of spaceflight TT&C communication, and the method comprises the steps of setting at least two redundant connections between system exchange chips; reserving and configuring NVram for each exchange chip; according to the communication demand of a newly-inserted function and the existing routing configuration in the NVram, the management software recalculates the port routing of the newly-inserted function; the newly-calculated port routing is stored in the configuration NVram of the related exchange chip, and takes effect after power-on again. The application provides a simple system and software implementation scheme, and can reduce the high-speed communication interference influence between the existing function and the newly-inserted function.

The application discloses a data packet transmission method for a network on chip and a RapidIO device, and belongs to the field of integrated circuit communication. The data transmission format in the network on chip is defined, wherein the data transmission in the network on chip is carried out in units of data packets, and the data transmitted on one data link in the network on chip in one clock cycle is defined as a microchip, the data bit width of the microchip is 154 bits, and each data packet is composed of a plurality of microchips. The NWRITE packet data load format of an AXI request received / sent by a conversion interface is specified; wherein the received NWRITE packet is divided into an NWRITE initial configuration packet, an NWRITE request packet and an NWRITE write data packet, and the data load format of the sent NWRITE packet is divided into an NWRITE read response data packet and an NWRITE various notification information packet. The application supports efficient communication between the network on chip and the RapidIO device, and reduces the data packet transmission delay.

The present application relates to the field of RapidIO switching network, and provides a RapidIO line rate dynamic configuration method and a switching network system, the method comprising: a RIO management node performing link scanning on an FPGA node, and issuing a dynamic configuration RapidIO line rate instruction to the FPGA node when the link state is poor; after the FPGA node receives the dynamic configuration RapidIO line rate instruction, starting the dynamic configuration of the RapidIO line rate. The present application detects the link state in real time through the RIO management node, and when the link state is poor, starts the dynamic configuration of the RapidIO line rate of the FPGA node through the instruction issuing mode, solves the problem of poor link state of the FPGA node, can effectively ensure the normal communication of the RapidIO switching network, and is simple in software implementation.

This invention relates to the field of electronics and communication technology, and discloses a signal processing system and signal generation and transmission method based on a heterogeneous processing platform. The system includes a host computer, a main control processing module, a dedicated signal processing module, a digital-to-analog converter (DAC) module, an analog-to-digital converter (ADC) module, and a radio frequency (RF) front-end. The main control processing module integrates a programmable logic unit (PLU), a processing system unit, and an on-chip memory module. The host computer is connected to the PLU via a first high-speed external bus and to the processing system unit via a first control bus. The dedicated signal processing module is connected to the PLU via a second high-speed external bus and a second control bus, respectively. Both the PLU and ADC modules are controlled by the PLU, and the output and input terminals of the PLU are connected to the RF front-end. This invention is compatible with processor hardware environments that do not support RapidIO messages, offering high transmission rates and low pin usage.

The application provides a kind of spaceborne high-performance computing module system, including CPU processing unit, FPGA control unit, storage unit and communication unit, wherein: the CPU processing unit is connected with FPGA control unit, and FPGA control unit, storage unit and communication unit are controlled and resource allocation by LocalBus bus;The data sent by the CPU processing unit is sent to external equipment after being processed by the FPGA control unit;The storage unit stores the program of CPU processing unit and the program of FPGA control unit;The communication unit is used to realize internal RapidIO interface and serial port.The application runs a "3+1" working mode under the premise of meeting high performance, provides a two-out-of-three scheme for application data, and solves the reliability problem of high-performance processors on commercial satellites.The application provides a hardware structure for realizing the reliability of high-performance processors.

The application provides an implementation method of reading and writing any byte length of RapidIO memory, comprising the following steps: the communication node and the FPGA node are interconnected with the RapidIO exchange chip through the RapidIO bus; the FPGA node realizes the reading and writing of any byte length of RapidIO memory by unpacking and padding the length field of the memory write sending or the memory read sending input by the user logic. In the application, the FPGA node unpacks and pads the length field of the memory write sending or the memory read sending input by the user logic, on the one hand, for the memory write sending, the actual application data length is sent out after the data is completely sent, thereby solving the problem of the memory write of any byte length. On the other hand, for the memory read sending, the data received by the memory read response is discarded according to the length of the data to be read input by the user logic, thereby solving the problem of the memory read of any byte length.

According to the RapidIO physical layer data seamless segmentation and alignment device, a determined conversion delay is achieved in the bit width conversion link, compared with an FIFO scheme, additional filling bits do not need to be processed, and compared with an asynchronous FIFO scheme for achieving equal bit width conversion and elastic buffering through a dual-port RAM, the scheme mainly depends on a register and combinational logic, and the conversion delay is determined. Storage resources can be saved, the chip area and static power consumption are correspondingly reduced, and the method is more suitable for application scenarios of large-scale SoC integration. Meanwhile, the device has universal expansibility between a high-speed interface and a Serdes chip, and the application of the device can also be expanded to high-speed interfaces such as PCIe, Ethernet and the like only by ensuring that code block bit width and synchronization head detection logic conform to protocol specifications.

The invention relates to the field of serial communication protocols, and provides a non-retransmission control method and device, a communication system and a readable storage medium. The method is executed in a RapidIO receiving end VC0 channel, a non-retransmission function control register comprising a cache non-retransmission enabling mark and a CRC non-retransmission enabling mark is arranged, and in combination with a cache management module and a CRC verification module, whether a received message has an insufficient cache error or a CRC error is judged. When only a cache insufficiency error exists or only a CRC error exists and a corresponding non-retransmission function is started, the receiving end returns a control character PA to replace the PR or the PNA, the message is discarded, and normal receiving of the port is kept; and when various errors are detected, returning to the PR or the PNA according to a standard RapidIO protocol to carry out retransmission processing. According to the invention, only the logic of the receiving end is modified, and selective non-retransmission of specific error messages can be realized according to port configuration, so that invalid retransmission is reduced, link congestion is relieved, and timeliness is improved.

The invention discloses a RapidIO network equipment enumeration and link fault self-recovery method, which adopts a breadth-first traversal strategy to execute equipment enumeration, construct a network structured data model, configure a node ID distribution rule and a routing evaluation rule, and realize efficient equipment discovery and optimal path selection. And after enumeration is completed, an independent link state monitoring thread is started, the port state is detected periodically, and a fault positioning and self-recovery process including port reset, equipment re-enumeration and route synchronization is triggered when abnormity is found. According to the method, the problems of low enumeration efficiency, non-optimal routing, lack of fault processing capability and the like under complex topology in the prior art are solved, and the reliability, the real-time performance and the maintenance efficiency of the RapidIO network are remarkably improved.

The application discloses a buffer adjustment method and device of a RapidIO protocol signal, and belongs to the technical field of communication. The application considers that a traditional fixed buffer is difficult to adapt to a rapidly changing dynamic signal, and collects the RapidIO protocol signal in real time, adjusts the buffer size in real time according to the signal characteristics of the RapidIO protocol signal, dynamically adjusts the buffer size, can adapt to real-time changes of the signal, and thus can completely capture the RapidIO protocol signal and does not cause resource waste due to setting of a too large buffer.

The application discloses a kind of SRIO middleware and bare drive data transceiver coexistence method, equipment and medium, belong to SRIO network field, including steps: S1, for SRIO middleware regular memory mapping address and receive space size;S2, for bare drive regular memory mapping address and receive space size;S3, doorbell driver unified reception doorbell information, and the classification of doorbell information is carried out;S4, SRIO middleware uses the doorbell information that can be used is distributed;S5, for SRIO bare drive the doorbell information that can be used is distributed.The application solves the problem of memory mapping address conflict and doorbell information conflict when realizing SRIO middleware and bare drive data transceiver coexistence, and can complete the transceiving of RapidIO data at high speed and high efficiency.

The invention discloses a 10-gigabit Ethernet protocol and SRIO protocol mutual conversion method based on a domestic FPGA, which comprises an FPGA platform used for mutual conversion of a 10-gigabit Ethernet protocol and an SRIO protocol, and a 10G Ethernet Subsystem IP core, a Serial RapidIO Gen2 IP core, an IP / TCP / UDP protocol stack module and a protocol conversion module are integrated in the FPGA platform. According to the invention, analysis and packaging of a 10-gigabit Ethernet IP / TCP / UDP protocol stack and an SRIO protocol are realized through FPGA hardware logic, the dependence on a processor is thoroughly eliminated, and full-hardware acceleration of a protocol conversion process is realized, so that the data throughput is greatly improved, and the transmission delay is remarkably reduced; and the method is suitable for application scenes with extremely high requirements on real-time performance and bandwidth, such as high-performance calculation, military electronics, industrial control and the like.

The application provides a kind of PHM software function automation test equipment, the PHM software function automation test equipment includes host computer 1, host computer 2, host computer 3, analog comprehensive treater;The analog comprehensive treater includes 1394 interface board, general processing board A1, general processing board A2, general processing board A3, general processing board B, FC exchange board and network exchange board;General processing board A1, general processing board A2, general processing board A3 all include processor board and PF daughter card;1394 interface board includes processor board, PF daughter card and 4 node 1394 card;General processing board B includes processor board and PF daughter card;Network exchange board includes network exchange board 1 and network exchange board 2, network exchange board 1 is RapidIO switch, and network exchange board 2 is Ethernet switch;Host computer 3 contains FC monitoring card.

The present invention relates to a compression algorithm optimization method, device, and electronic device based on the RapidIO protocol stack. The method comprises: determining an applicable compression algorithm based on the data type transmitted by RapidIO; integrating the selected compression algorithm into the transport layer of the RapidIO protocol stack and creating compression and decompression functions as independent modules; dynamically adjusting the compression strategy based on real-time network status and data characteristics; and adding a data integrity verification mechanism during the compression and decompression process. By selecting an appropriate compression algorithm and integrating it into the protocol stack, the invention can significantly reduce the amount of data transmitted, thereby improving bandwidth utilization and meeting high-bandwidth requirements. At the same time, the modular design and introduction of dynamic compression strategies enable the system to adaptively adjust according to real-time network status and data characteristics, meeting real-time requirements, facilitating efficient bandwidth utilization and reducing resource waste when processing large-scale data transmission.

A RapidIO driver virtualization method for a multi-core time-sharing partition system performs the following configuration on a multi-core communication processor: a RapidIO driver resides in each partition, and interrupt response resources are encapsulated only in the first partition; each processor is allocated a DMA engine, a DIO data receiving interface, and a DIO data sending interface; these three hardware resources are shared by all partitions running on the processor core; and a set of bportals and qportals are shared between partitions of the same-core processor. These bportals and qportals are stored in a shared memory address as structured data and provided to the partitions of the same-core processor. This method can directly perform RapidIO network data interaction through the virtualized RapidIO interface, without considering the resource occupation and release issues caused by concurrent access between multiple cores.

This invention discloses an amplitude adaptation method, apparatus, medium, and system based on RapidIO, belonging to the field of embedded system applications. The method includes the following steps: by adaptively setting the RapidIO amplitude, sequentially through pre-emphasis setting and de-emphasis setting, to find the optimal amplitude corresponding to the physical location of the module; the optimal amplitude setting is used to improve the problem of poor RapidIO signal quality caused by hardware wiring in large-scale RapidIO networks, which prevents RapidIO nodes from joining the network. This invention optimizes the signal quality of RapidIO nodes without affecting the data rate, resulting in higher efficiency and better user acceptance.

The invention relates to a management method and system for RapidIO communication system routing based on ZYNQ, and the management method comprises the steps: an SRIO IP core is deployed at a PL end of the ZYNQ, the SRIO IP core is integrated with a hardware maintenance packet interface, the SRIO IP core is a RapidIO protocol interface realized at the PL end of the ZYNQ, and interaction between a bottom layer SRIO interface and I2C interface hardware and a RapidIO communication system is realized through an SRIO driver and an I2C driver; the Linux operating system runs at the PS end of the ZYNQ, and a routing management engine and a Web service are integrated; and performing configuration management of static routing / dynamic routing through a Web configuration interface, wherein the configuration management comprises port attribute configuration and state monitoring, file function configuration, static routing / dynamic routing mode selection and routing information reading and storage. The invention further discloses a management system of the RapidIO communication system route based on the ZYNQ.

The invention discloses a RapidIO-based full-exchange radar digital system and method, a medium and equipment, and the method comprises the steps that a control center node receives encrypted code data sent by a terminal through a preset encryption protocol by using a preset bootstrap program, and distributes the decrypted code data to each target function node; each function node enters a dynamic loading mode by default after being powered on by utilizing a built-in bootstrap program, receives the decrypted code data through the RapidIO exchange chip, stores the decrypted code data in the local storage unit, and decrypts and executes the loading process of the code data. Key algorithms and programs of users are not involved, the risk of intellectual property leakage caused by direct reading of data of the memory unit by a decipher can be prevented, and the purposes of fast program upgrading, high efficiency and low maintenance difficulty are achieved.