67 results about "RapidIO" patented technology

The invention relates to a compression algorithm optimization method and device based on a RapidIO protocol stack and electronic equipment, and the method comprises the steps: determining an applicable compression algorithm according to the type of data transmitted by RapidIO; integrating the selected compression algorithm to a transmission layer of a RapidIO protocol stack, and creating compression and decompression functions as independent modules; dynamically adjusting a compression strategy according to a real-time network state and data characteristics; and a data integrity checking mechanism is added in the compression and decompression processes. By selecting a proper compression algorithm and integrating the compression algorithm into a protocol stack, the data transmission quantity can be remarkably reduced, so that the bandwidth utilization rate is improved, the high-bandwidth requirement is met, meanwhile, due to the modular design and the introduction of a dynamic compression strategy, the system can perform self-adaptive adjustment according to the real-time network state and data characteristics, and the real-time performance of the system is improved. The real-time requirement is met, the bandwidth can be effectively utilized conveniently when large-scale data transmission is processed, and resource waste is reduced.

The invention discloses a high-performance CPU-GPU (Central Processing Unit-Graphics Processing Unit) cooperative processing architecture of an audio frequency integrated signal processor, belonging to the technical field of audio frequency integrated signal processing, the architecture is based on a dynamic priority scheduling model and realizes efficient collaboration of a CPU and a GPU through hierarchical resource management and protocol level optimization, a hardware layer adopts a multi-GPU cluster and a distributed storage node, and the CPU-GPU cooperative processing architecture has the advantages that the multi-GPU cluster and the distributed storage node are integrated; high-concurrency task processing is supported; the transmission layer fuses RapidIO and an Ethernet protocol, and adapts to a short frame control signal and a long packet data stream respectively; and the application layer calculates task resource demands through dynamic priority weights, and ensures low time delay of key tasks in combination with a normalized allocation algorithm. According to the architecture, in an audio signal processing scene, the task scheduling efficiency is improved by 40%, the short frame transmission delay is as low as 0.5, the throughput of a long data stream reaches 100 Gbps, and the requirements for real-time performance and calculation precision in a complex acoustic environment can be met.

The invention provides an audio frequency integrated signal processing system based on a VPX architecture, and the system comprises a case which accords with the OpenVPX standard and is internally provided with a backboard, and the backboard is integrated with a high-speed serial RapidIO bus and an Ethernet interface; the plurality of heterogeneous computing board cards are connected into the case through VPX slots, the board cards are in point-to-point communication through high-speed serial RapidIO buses, and the heterogeneous computing board cards comprise different types of computing chips and execute different types of audio signal processing tasks; and the multi-machine stacking expansion module is connected with the case through a backboard Ethernet interface, and is connected with an external processor through the backboard Ethernet interface to carry out distributed calculation when it is detected that the calculation capability of any heterogeneous calculation board card cannot meet the audio signal processing requirement. By implementing the scheme, the overall signal processing efficiency of the system can be improved, and the error-tolerant rate and reliability of the system can be improved.

The invention belongs to the technical field of FPGA ASerDes serial interfaces, and discloses a serial high-speed interface packaging method and system based on an FPGA. A user interface module is designed, and the user interface module is used as a channel for data interaction between a user module and the SRIOIP core; a maintenance module is designed and used for carrying out maintenance operation on the RapidIO device through a read-write transaction; a request module is designed and used for executing a request test sequence, request packet packaging, a request response verification function and response packet analysis; designing a target module for responding to the request transaction packet of the initiating device; an SRIO communication software framework is designed for caching transmission data and solving rate matching of a user clock domain and an SRIO clock domain. According to the method, the use efficiency of the RapidIO bus and the simplicity and convenience of operation are improved, and the use efficiency and the development speed can be improved by packaging according to the method.

This application provides a method for diagnosing and isolating RapidIO system link faults, belonging to the technical field of RapidIO system link fault handling. Specifically, the method includes active diagnosis, which includes: route retrieval, which searches for routes on all switch devices in the RapidIO system, using a depth-first algorithm to retrieve the system's routing tables, including the device routing table and port routing table, and obtains the device IDs of all terminal devices in the system, while proactively discovering link faults during the retrieval process; route matching, which matches the device IDs of all terminal devices in the system with the system's routing table. Based on the matching results, the method locates switch nodes with routing errors and further localizes the routing errors to the corresponding switch ports. This solution improves system reliability.

The invention provides a DMA (direct memory access) engine device and a data transmission method in a PCIE (peripheral component interface express)-to-RapidIO circuit, a DMA engine comprises a sending engine and a receiving engine which are used for processing data processing and protocol conversion of data packets sent and received in a DMA transmission process; the cache FIFO is used for caching the data read by the DMA engine; and the DMA channel control module and the state control register are used for controlling the DMA engine to update the operation state. A descriptor is configured in a PCIe memory through a host to define detailed parameters of DMA operation; the DMA engine can support DMA data transmission and protocol conversion between the PCIe core and the RapidIO core, and high-speed and low-delay data transmission in the PCIe-to-RapidIO circuit is achieved.

The invention discloses an efficient management system, method and device for a complex electronic system and a medium, and belongs to the technical field of complex electronic system management.The efficient management system comprises a cluster management node, a CPU cluster, an FPGA management node cluster, an FPGA computing node cluster and a RapidIO management node; the cluster management node directly manages the CPU cluster and the FPGA management node; the FPGA management node is used as an agent for the FPGA computing node; the cluster management node, the CPU cluster and the FPGA management node are mutually communicated through the Ethernet; the FPGA nodes are mutually communicated through a RapidIO (Input / Output) bus; and the FPGA management node and the FPGA node communicate with each other through a high-speed port. According to the method, the computing efficiency of the embedded cloud native application can be improved, and the convenience of development and deployment can be improved.

The present invention discloses a high-speed real-time transmission implementation system and method based on the RapidIO protocol, comprising a data exchange module that is simultaneously connected to a source device and a destination device, the data exchange module comprising an FPGA chip, the source device and the data exchange module exchanging data via a serial transceiver, the data exchange module and the destination device exchanging data via a RapidIO interface, and the serial transceiver and the RapidIO interface both being connected to the FPGA chip via a cache module. The system of the present invention is highly flexible, highly scalable, and easy to transplant. The present invention can increase or decrease the interface between the source device and the data exchange module FPGA, and the interface between the data exchange module FPGA and the destination device according to system requirements, and adjust the data transmission bandwidth by increasing or decreasing the interface. The present invention takes into account both high bandwidth and real-time performance, adopts multi-channel transmission, increases the transmission speed, and improves the transmission efficiency.

The utility model belongs to the field of avionics, and relates to a data acquisition management processor integrating multi-type data acquisition and storage. Comprising a power conversion module, a flight parameter acquisition module, a task processing module, a 1394B bus module, an FC network monitoring module, a video acquisition module, a maintenance data card and an information data card. The power failure indication output end of the power supply conversion module is connected with the IO port of the task processing module; the lighting signal input end of the power supply conversion module is connected with the other IO port of the task processing module; the flight parameter acquisition module is connected with one SRIO port of the task processing module through an SRIO bus; the 1394B bus monitoring module is respectively connected with three PCIe ports of the task processing module through three paths of independent PCIe buses; the FC network monitoring module is connected with the other PCIe port of the task processing module through a PCIe bus; the video acquisition module is connected with a RapidIO port of the task processing module through a RapidIO bus; and the maintenance data card and the information data card are respectively connected with the PCIe bus interface of the task processing module.

The invention provides a DMA (Direct Memory Access) controller, a control method and a bridging chip. The controller comprises a PCIe (Peripheral Component Interconnect Express) splitting and combining processing module, a WDMA processing module, a control and state register, a doorbell processing module and a RapidIO splitting and combining processing module, the PCIe splitting and combining processing module is connected with the WDMA processing module and the control and state register; and the RapidIO splitting and combining processing module is connected with the WDMA processing module and the doorbell processing module. The WDMA processing module is used for reading to-be-sent data on the PCIe side, assembling a RapidIO write request according to the descriptor information, and sending the RapidIO write request to an opposite side device connected with the RapidIO controller; the control and state register is used for controlling behaviors of the WDMA processing module and storing necessary information; and the doorbell processing module is used for generating and sending a doorbell data packet and processing doorbell response. According to the scheme, the doorbell is automatically triggered after hardware finishes data migration, so that a plurality of links of software processing are omitted, the speed is higher, and the burden of a CPU (Central Processing Unit) is relieved.

The invention provides a RapidIO network equipment routing method, system and device, and the method comprises the steps: obtaining a topological structure of a RapidIO network system, and forming a topological graph; based on the topological graph, calculating an optimal link when a plurality of links exist between any two directly connected switching nodes; setting a cost and path array between all switching nodes, calculating the minimum cost between any two switching nodes, and updating a path between the two switching nodes based on the minimum cost; starting from the host, calculating the path with the minimum cost in the possible paths passing through all the switching nodes as a planned path; starting from the last switching node of the planned path, performing backtracking based on the planned path, and forming an added planned path; and traversing from the host again, adding, planning a path, and adding the route to each switching node. According to the scheme, the maintenance packet can arrive at the destination faster through shortest path transmission, the transmission delay is reduced, and the network response speed is improved.

The application provides an audio integrated signal processing system based on a VPX architecture, which comprises: a case conforming to an OpenVPX standard, wherein a backboard is arranged in the case, the backboard is integrated with a high-speed serial RapidIO bus and an Ethernet interface; a plurality of heterogeneous computing board cards are connected to the case through VPX slots, the board cards are in point-to-point communication through the high-speed serial RapidIO bus, the heterogeneous computing board cards contain different types of computing chips and perform different types of audio signal processing tasks; and a multi-machine stacking expansion module is connected to the case through the Ethernet interface of the backboard, when it is detected that the computing capacity of any of the heterogeneous computing board cards cannot meet the audio signal processing demand, an external processing machine is connected through the Ethernet interface of the backboard to perform distributed computing. Through implementation of the scheme, the signal processing efficiency of the whole system can be improved, and the fault tolerance and reliability of the system are improved.

This application provides a fault detection and handling method for RapidIO switching networks, belonging to the field of embedded computer technology. Specifically, it includes several RapidIO service nodes, a dual-redundant RapidIO system management node, and a RapidIO switch. The RapidIO system management node connects to the RapidIO switch and the RapidIO service nodes through an independent RapidIO system management bus interface. The two RapidIO system management nodes employ a master / slave switching strategy to determine the master node. Master and slave determination is performed upon power-up, and master / slave checks are periodically performed during operation. After determining the RapidIO system management master node, it performs the detection and handling of RapidIO switching network faults. This application's solution effectively prevents the spread and deterioration of RapidIO switching network faults.

The invention belongs to the technical field of FPGA (Field Programmable Gate Array) reconfiguration, and discloses a remote dynamic reconfigurable system based on an FPGA and a reconfiguration method. According to the system, a RapidIO high-speed serial bus technology and a reconfigurable technology are fused, a DSP + FPGA + RapidIO-based framework is reconfigured and designed, non-remote dynamic reconfiguration and remote dynamic reconfiguration are realized, and the system specifically comprises a host, a DSP, an FPGA, a slave and a FLASH memory. According to the invention, the dynamic reconfigurable carrier board with a DSP + FPGA + RapidIO architecture is designed as the main control board, so that functional boards with different functional requirements can be hung, and high stability, high expansibility and high universality are achieved. The transmission bandwidth of the RapidIO bus can reach 6.5 Gbytes, and the realization of the remote dynamic reconfigurable system based on the SRIO bus provides a guarantee for realizing remote and rapid switching of complex algorithms by using a high-speed dynamic reconstruction technology.

The utility model relates to the technical field of communication system processing, and particularly discloses a communication system board card based on an FPGA (Field Programmable Gate Array), which comprises a first radio frequency signal processing unit, a second radio frequency signal processing unit and a plurality of VPX interfaces, the first radio frequency signal processing unit comprises a first FPGA chip, a first ADC module and a first SPI FLASH, and the first FPGA chip is connected with the first ADC module and the first SPI FLASH; the second radio frequency signal processing unit comprises a second FPGA chip, a second ADC module and a second SPI FLASH, the second FPGA chip is in communication connection with the first FPGA chip, and the second FPGA chip is connected with the second ADC module and the second SPI FLASH; and the first FPGA chip and the second FPGA chip are connected with the plurality of VPX interfaces and are used for processing the received first radio frequency signal and outputting a processed second radio frequency signal. A structure of FPGA + ADC + DAC is adopted, and a high-speed optical port or a RapidIO data communication interface is adopted, so that high-speed data transmission is realized.

The application discloses a kind of high-performance CPU-GPU collaborative processing architecture of audio integrated signal processor, belong to audio integrated signal processing technical field, this architecture is based on dynamic priority scheduling model, through hierarchical resource management and protocol level optimization, the efficient cooperation of CPU and GPU is realized, hardware layer uses multi-GPU cluster and distributed storage node, support high concurrency task processing;Transport layer fuses RapidIO and Ethernet protocol, respectively adapts short frame control signal and long packet data stream;Application layer calculates task resource demand by dynamic priority weight, and combines normalization allocation algorithm to guarantee the low latency of key task.The architecture in the scene of audio signal processing, task scheduling efficiency is improved by 40%, short frame transmission delay is as low as 0.5, long data stream throughput reaches 100Gbps, can satisfy the real-time and calculation accuracy demand under complex acoustic environment.

The application discloses a RapidIO link configuration system, method and medium, and belongs to the field of spaceflight TT&C (Tracking, Telemetry and Command), and comprises the following steps: firstly, a central node configures the routing between any two nodes connected through a RapidIO switching network; and secondly, a FPGA receiving node configures the link of a communication node related to the FPGA receiving node and the link of the FPGA receiving node itself. The application provides a simple and reliable RapidIO link configuration scheme with high flexibility and capable of reducing the coupling relationship between the central node and the leaf node.

The invention discloses a RapidIO dual-port link configuration synchronous data receiving and transmitting method, device, medium and system, and belongs to the field of spaceflight measurement and control, and the method comprises the steps: firstly, a main management node, a standby management node, a communication node 1 to a communication node N and an FPGA node are accessed to a RapidIO switching network through a RapidIO bus; and secondly, the FPGA node is composed of two RapidIO ports, namely, an RIO1 port and an RIO2 port. When any RapidIO port is reconfigured, the configuration information is automatically synchronized to the other RapidIO port, so that the system does not need to reconfigure the RapidIO port of the FPGA node when the system is in a fault state. According to the scheme, the hardware cost is low, the fault reconstruction time is short, the coupling between the driver and the user logic is reduced, and the overall working efficiency of the system can be improved.

The invention relates to the field of RapidIO switching networks, and provides a RapidIO line rate dynamic configuration method and a switching network system.The method comprises the steps that an RIO management node conducts link scanning on an FPGA node, and when the link state is poor, a RapidIO line rate dynamic configuration instruction is issued to the FPGA node; and after the FPGA node receives the instruction for dynamically configuring the RapidIO line rate, the RapidIO line rate dynamic configuration is started. According to the method, the link state is detected in real time through the RIO management node, when the link state is not good, the FPGA node is started to dynamically configure the RapidIO line rate in an instruction issuing mode, the problem that the link state of the FPGA node is not good is solved, normal communication of the RapidIO switching network can be effectively guaranteed, and software is easy to achieve.

The invention belongs to the technical field of computer bus interfaces, and particularly relates to a PCIe-to-RapidIO protocol conversion method and device and application. Comprising the following steps: receiving a transaction request from a PCIe end; dynamically calculating an optimal fragmentation strategy according to the initial address, the transmission data length and the effective byte indication, and outputting a fragmentation descriptor; according to the fragmentation strategy, carrying out segmentation or recombination on transmission data, and generating a corresponding RapidIO protocol packet header for each RapidIO data packet; and the plurality of packaged RapidIO data packets are sent to a RapidIO end. According to the invention, the number of data packets required by protocol conversion is reduced, and the bus overhead and transmission delay are reduced, so that the overall throughput and efficiency of a cross-protocol interconnection system are improved.

The present invention provides a rapidIO network management method, aiming to provide a method for reducing software operation anomalies caused by network congestion. This solution is achieved through the following technical solutions: Each processor node on the signal processing module is interconnected through a rapidIO network switch to form a rapidIO sub-network, and the rapidIO sub-networks on each module are interconnected to form a rapidIO backbone network. The master node in the sub-network maintains the status of each node in the sub-network, executes fault handling measures when an anomaly occurs, and periodically sends the sub-network status to the master node of the main module. The master node of the main module maintains the status of each sub-network. When the master node of the main module fails, the master node of the backup module maintains the status of the backbone network.

The application discloses a data exchange device for network interface equipment and SRIO interface equipment, which comprises a main chip and a network exchange chip, the main chip adopts an FMQL45T900 chip, and a processor system PS and programmable logic PL are integrated in the chip, wherein the processor system PS is connected with the network exchange chip to realize data intercommunication between various external terminals with network interfaces; the programmable logic PL constitutes an SRIO exchange network to realize physical SRIO intercommunication between various main chips and data intercommunication between various external terminals with RapidIO high-speed serial ports; and the network exchange chip adopts an SF2507 chip to realize gigabit network exchange function of a network port. The application realizes data interaction between the network interface equipment and the SRIO interface equipment, and widens the application range of the data exchange device.

The invention discloses a distributed FPGA reconstruction management method and system, and relates to the field of computer embedded technology. A connection is established between an external microsystem and an agent FPGA, and configuration data in a memory is remotely read and encrypted, and a RapidIO interface is used for efficient data transmission. Data security and transmission efficiency are ensured, and reconstruction delay is reduced. According to configuration data and external task requirements, the dynamic performance and resource allocation characteristics of each FPGA are analyzed through a dynamic priority scheduling algorithm, the priority reconstruction index is evaluated, the reconstruction order is determined, and resource utilization is optimized. During the FPGA reconstruction process, the operating environment and configuration status data are obtained, and a data fusion algorithm is used for comprehensive analysis to obtain the operating health index of each FPGA, monitor the FPGA health status in real time, and improve system reliability. According to the operating health index, the abnormal state in the reconstruction process is analyzed to help operation and maintenance personnel to promptly discover potential problems in the FPGA reconstruction process, and improve the overall operating efficiency and management level of the FPGA.

The invention provides an IO core grain NoC network node high-speed interface circuit based on RISC-V. The IO core grain NoC network node high-speed interface circuit comprises PCIe, RapidIO, a DDR and a configuration management unit. The configuration management unit comprises an RISC-V instruction core, a CROSSBAR bus, a configuration unit and an AXI 1to6 conversion bridge; the configuration unit comprises an AXI one-to-six conversion bridge and a plurality of configuration bridges; and an AXI interface output by the CRO SSBAR bus is subjected to one-to-six processing. Through the innovative design that the configuration bridge unit is additionally arranged between the RISC-V core and the interface IP, efficient initialization configuration of IO equipment is achieved.

The invention discloses a RapidIO switching network health management method and a RapidIO switching network health management platform. The management method comprises the following steps: 1) network topology management; 2) equipment configuration management; 3) monitoring the system state in real time; 4) fault monitoring and processing; according to the method, efficient, safe and stable operation of the system is ensured, and the overall operation quality of the network system is comprehensively improved through effective management, performance optimization, quick fault response, safety guarantee, configuration and maintenance simplification, reasonable resource allocation, statistical analysis and compliance requirement meeting.

The application discloses a complex electronic system RapidIO link quality guarantee method, device, medium and system, belongs to the field of spaceflight TT&C communication, and the method comprises the steps of setting at least two redundant connections between system exchange chips; reserving and configuring NVram for each exchange chip; according to the communication demand of a newly-inserted function and the existing routing configuration in the NVram, the management software recalculates the port routing of the newly-inserted function; the newly-calculated port routing is stored in the configuration NVram of the related exchange chip, and takes effect after power-on again. The application provides a simple system and software implementation scheme, and can reduce the high-speed communication interference influence between the existing function and the newly-inserted function.

The invention provides a RapidIO line rate adaptive matching method and a switching network system. The method comprises the following steps: detecting a link establishment signal Linkinit; and when the link building signal Linkinit is invalid, line rate matching between the FPGA node and the RapidIO exchange chip is automatically completed based on line rate traversal. Through a line rate traversal matching mode of the FPGA node and the RapidIO exchange chip, the problem that in a traditional design, multiple different RapidIO line rates of the RapidIO port of the exchange chip are matched by compiling multiple FPGA software versions is solved, the system development integration efficiency is improved, and software is easy to implement.

The application discloses a data packet transmission method for a network on chip and a RapidIO device, and belongs to the field of integrated circuit communication. The data transmission format in the network on chip is defined, wherein the data transmission in the network on chip is carried out in units of data packets, and the data transmitted on one data link in the network on chip in one clock cycle is defined as a microchip, the data bit width of the microchip is 154 bits, and each data packet is composed of a plurality of microchips. The NWRITE packet data load format of an AXI request received / sent by a conversion interface is specified; wherein the received NWRITE packet is divided into an NWRITE initial configuration packet, an NWRITE request packet and an NWRITE write data packet, and the data load format of the sent NWRITE packet is divided into an NWRITE read response data packet and an NWRITE various notification information packet. The application supports efficient communication between the network on chip and the RapidIO device, and reduces the data packet transmission delay.

The invention provides an implementation method for reading and writing any byte length in a RapidIO memory. The implementation method comprises the steps that a communication node and an FPGA node are connected with a RapidIO exchange chip through a RapidIO bus; and the FPGA node performs unpacking and complementing operation on a length field of memory write sending or memory read sending logically input by a user, so that the RapidIO memory can read and write any byte length. According to the method, the FPGA node performs unpacking and complementing operation on the length field of memory write sending or memory read sending logically input by a user, on one hand, for memory write sending, after all data are sent, the actual application data length is sent out, and the problem that any byte length is written in the memory is solved; on the other hand, according to memory read sending, data received by memory read response is discarded according to the length of the data to be read input by the user logic, and the problem that the memory reads any byte length is solved.

The present invention provides a method and apparatus for measuring the delay performance of a RapidIO switch chip. The method uses the RapidIO switch chip RTL code as the DUT (object under test). The DUT includes digital circuit code and analog circuit code. The analog circuit code includes a SerDes model, which is used to generate RapidIO protocol data packets as test stimuli and reflects the actual timing behavior of the physical analog circuit. The digital circuit code is transmitted within the DUT under the clock ticks corresponding to the analog circuit code. The method records the time value T1 corresponding to the rising edge of the first beat of the data packet at the switch chip input port S0_I and the time value T2 corresponding to the rising edge of the first beat of the data at S1_I. The time difference between T2 and T1 represents the delay of the entire transmission path of the RapidIO switch chip. The method and apparatus for measuring the delay performance of a RapidIO switch chip described herein replace the object under test with the RTL design code, resolving the problem that existing testers cannot support delay testing of RapidIO switch chips at frequencies above 6.25Gbps.