Method and system for processing multicore DSP array medium based on RapidIO interconnection

A processing system, multi-core technology, applied in the fields of electrical digital data processing, television, instruments, etc., can solve problems such as insufficient bus bandwidth, achieve the effect of improving processing density and ensuring feasibility

Inactive Publication Date: 2008-10-08
AVONACO COMM SYST SUZHOU
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Problems solved by technology

The main problem of the general-purpose bus structure is: when there are multiple devices on the system bus, each device shares the bus bandwidth, and the bus needs to be occupied by time sharing through arbitration, resulting in insufficient bus bandwidth for each device

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  • Method and system for processing multicore DSP array medium based on RapidIO interconnection
  • Method and system for processing multicore DSP array medium based on RapidIO interconnection
  • Method and system for processing multicore DSP array medium based on RapidIO interconnection

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Embodiment 1

[0017] See attached figure 1 , which is a schematic diagram of the multi-core DSP star topology based on RapidIO interconnection in this embodiment; five multi-core DSPs are connected in a star shape through the RapidIO Switch. Among the multi-core DSPs, one is a high-definition encoder, one is a picture fuser, and three For HD codec. In this embodiment, five DSP cores are packaged in one chip, and the cores communicate through a high-speed bus and a shared memory. Each DSP core runs independently at a frequency up to 1GHz, which greatly improves the processing density of a single DSP chip while reducing power consumption and area.

[0018] For complex video processing, such as H.264 encoding of 1280x720, a single DSP core cannot handle it. With the technical solution of the present invention, these complex video applications can be processed in a pipelined manner, and each DSP chip only undertakes processing a certain For example: video decoding or picture synthesis, a vide...

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Abstract

The invention relates to a multi-core DSP array media processing system based on RapidIO interconnection and method thereof. Three more multi-core DSP are serially interconnected by RapidIO and are packaged inside a chip, communications between the cores are realized by employing high-speed bus and shared memory; the media processing method is: transmitting high-definition media processing streams respectively to multiple DSP high-definition decoders for decoding; transmitting the result to another multi-core DSP image synthesizer through RapidIO, and inputting the processed signal to the multi-core DSP high-definition encoders for encoding. RapidIO switching technology is employed by the invention, which can respectively provide a low-delay data switching path with maximum transmission speed of 10Gbps between each DSP chip, which ensures feasibility of pipeline processing and greatly improves processing density for a signal DSP, which can real-time distribute processing task effectively according to processing load of each DSP kernel.

Description

technical field [0001] The invention relates to a task scheduling method in a multi-core DSP system, in particular to a multi-core DSP array media processing system based on RapidIO interconnection and a method thereof. Background technique [0002] Multimedia processing (such as H.263, MPEG-4, H.264 encoding, decoding and transcoding) involves very complex mathematical operations and consumes a lot of processing resources. For example: H.264 CIF (352x288 pixels) format real-time The encoding operation of 30 frames per second needs to consume more than 1000Mhz of general-purpose CPU computing resources. Currently, the fastest Intel P4 4GHz CPU can only support 4-5 channels, and the fastest single-core DSP can only support 7-8 channels. A traditional single-core DSP cannot handle high-definition (HD Full HD) video. In order to meet a large number of parallel data processing, DSP can realize multi-DSP bus interconnection through PCI bridge with the help of PCI bus interface, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26G06F13/40H04N19/00
Inventor 虞水中吴涛
Owner AVONACO COMM SYST SUZHOU
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