Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

RapidIO network switching method for VPX switching board

A technology of network switching and switching boards, which is applied in the field of rapidIO network switching of VPX switching boards, can solve problems such as waste of resources, dead links, inconvenient management of rapidIO nodes, etc., and achieve the effect of saving resources and boards

Active Publication Date: 2017-11-24
THE 724TH RES INST OF CHINA SHIPBUILDING IND
View PDF3 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This design is a waste of resources for systems that do not need PowerPC boards, and it is inconvenient to manage rapidIO nodes. Any PowerPC can be enumerated, which will inevitably cause conflicts, resulting in dead links.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • RapidIO network switching method for VPX switching board
  • RapidIO network switching method for VPX switching board
  • RapidIO network switching method for VPX switching board

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] The present invention mainly implements rapidIO network enumeration, hot plugging and bandwidth allocation functions on the FPGA of the switch board, and integrates the rapidIO-FC optical fiber switching module. The specific implementation method is as follows:

[0014] 1) Construction of SOPC hardware system based on MicroBlaze:

[0015] Using Xilinx's vivado suite, the SOPC system-on-chip hardware framework is built by combining MicroBlaze soft core, AXI Connect core, UART, and custom rapidIO switching IP core. The IP core of the peripheral device is connected through the AXI bus, and the devices interact with each other through the AXI bus protocol. The block diagram of the SOPC-based RapidIO switch board is as follows: figure 1 As shown, the logical design block diagram of the rapidIO switching IP core is shown in figure 2 shown.

[0016] 2) RapidIO network enumeration and bandwidth allocation implementation:

[0017] Under the hardware framework, using the SDK...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a rapidIO network switching method for a VPX switching board. On an FPGA chip of the VPX cabinet switching board, based on an SOPC architecture, a self-defined IP core is invented, a rapidIO-FC conversion function and an interface between a rapidIO maintenance port and a CPU soft core are integrated, and under the hardware architecture, SDK software is adopted to complete rapidIO driving and a network enumeration algorithm, and bandwidth allocation and hot pluggable management functions are realized.

Description

technical field [0001] The method relates to an improved method for rapidIO high-speed data exchange of a VPX chassis. Background technique [0002] RapidIO is an embedded system interconnection technology and an open point-to-point interchange standard, which has the advantages of high bandwidth, low latency, and high reliability. It can also connect processors, memory, and external devices across the backplane in the VPX chassis. It has been widely used in radar signal transmission. [0003] In the past, the switch board in the VPX chassis only added the rapidIO switch chip to realize the rapidIO data exchange between the chassis, and the enumeration of the rapidIO network was realized through a certain PowerPC board; the data exchange between the chassis and the chassis was through FC optical fiber communication, That is, the conversion between rapidIO and FC data is performed through an FC board on the rear IO. This design wastes resources for systems that do not need ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/931H04L29/06H04L12/02
CPCH04L12/02H04L49/35H04L49/40H04L69/08
Inventor 王静娇姜小祥翟刚毅李云飞
Owner THE 724TH RES INST OF CHINA SHIPBUILDING IND
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com