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2607results about How to "Reduce processing load" patented technology

Catalysis and micro-electrolysis combined technology for high-concentration refractory organic wastewater

The invention relates to a catalysis and micro-electrolysis combined technology for high-concentration refractory organic wastewater; the organic wastewater is collected to an adjusting tank and enters an air floatation tank for air floatation treatment to remove part of the organic matters after the adjustment of water volume and water quality; the scruff is collected or recovered; the wastewatergoes through Ph adjustment and then enters a catalytic iron-carbon and micro-electrolysis unit to improve the biochemical quality; the effluent goes through Ph adjustment and then enters a sedimentation tank; the effluent of the sedimentation tank adopts anoxic-aerobic biochemistry treatment to remove the organic matters and ammonia nitrogen and then is emitted after reaching the standard; and the filler of the catalytic iron-carbon and micro-electrolysis unit comprises iron, carbon and a catalyst, wherein the mass ratio of the iron, carbon and catalyst is 1: (0.3-1.5): (0.01-0.5). The invention can effectively improve the micro-electrolysis electrochemical reaction efficiency and the degrading capability to the organic matters, and reduce the wastewater treatment cost with convenient technological operation.
Owner:CENT SOUTH UNIV

Semiconductor device and manufacturing process therefor

To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip. It is possible to realize a unique connection structure having a high reliability in accordance with the caulking action using the plastic flow of a metallic bump in a very-low-cost short-TAT process and provide a three-dimensional inter-chip connection structure having a high practicability.
Owner:RENESAS TECH CORP
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