22 results about "Logical combination" patented technology

The present application relates to the technical field of data query, in particular to a multi-index horizontal expansion data processing method and system, comprising the following steps: collecting time series and dimension attributes to generate a business detail wide table, matching non-empty measure fields to form independent index logic, combining rule nodes to build a general materialized architecture, and outputting multi-index processing results through scheduling mapping and window aggregation. In the present application, a wide table is constructed in the model layer and atomic and derived indexes are centrally managed, realizing a unified index definition method independent of dimension combination. When a user queries, dimension parameters are dynamically combined by the query engine to automatically build an aggregation statement and calculate the result, avoiding the problem of derived index explosion caused by the expansion of the number of dimensions. Meanwhile, multi-index joint analysis is completed in the same materialized table without the need for multiple table joins, improving query execution efficiency, having high adaptability to index updates and dimension changes, and significantly reducing data development and operation and maintenance burden.

The invention discloses a physical-level anti-quantum key packaging device and method, and the method comprises the steps: cutting off a byte stream to a first modulus through a bit mask operation, and generating a polynomial matrix in a constant physical clock period; calculating an inner product of a private key vector of the polynomial matrix, executing logic combination operation, compressing modulus, and generating a public key vector; after receiving the public key vector, the second communication node reconstructs a system state by using the temporary private key and outputs a ciphertext; and the first communication node receives the ciphertext, performs fault-tolerant restoration and re-encryption, drives a bottom multiplexer to generate a mask, and selects one of a real session key and a random noise key to be output in a constant physical clock period. According to the anti-quantum cryptography algorithm, logic combination operation, algebraic divide-and-conquer and physical circuit characteristics are utilized, hardware simplification is achieved, meanwhile, safety is improved, strategic expansion capacity is achieved, and the problems that an existing anti-quantum cryptography algorithm faces the computing power bottleneck and the side channel attack risk in a low-power-consumption node lacking a hardware divider circuit are solved.

The invention relates to the technical field of networks, in particular to an interpretation language generation method and device suitable for protocol decoding and a medium, and provides an interpretation language suitable for protocol decoding. The method supports the description of logic combination and complex nested structures, has strong expression ability and good readability, is simple enough in design, greatly reduces the manufacturing difficulty and reading difficulty of decoding scripts and the total amount of codes, and greatly shortens the development period. Meanwhile, in protocol decoding, each network protocol is regarded as a formal language, abstraction is carried out to describe most protocols, an interpretation language which is concise in design is designed to standardize and describe basic logic and combination of the formal language, a plain text protocol decoding script is used for replacing a traditional hard coding decoder, and a complete three-level grammar system of words, sentences and segments is constructed.

The embodiment of the application discloses a decoding logic derivation method, a failed storage particle positioning method and related equipment, comprising: collecting all first error physical addresses generated by testing a same failed storage particle in a first physical slot to form a first error physical address set; collecting all second error physical addresses generated by testing the same failed storage particle in a second physical slot to form a second error physical address set; searching the first error physical address set and the second error physical address set to find k address bits, or a logical combination thereof, which is always a same value in binary logic values of all the first error physical addresses and is always an opposite value of the same value in binary logic values of all the second error physical addresses; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. The application can automatically restore hidden physical address decoding logic and realize automatic, accurate and efficient positioning of the physical position of the failed storage particle.

The embodiment of the invention discloses a decoding logic derivation method, a failure storage particle positioning method and related equipment, and the method comprises the steps: collecting all first error physical addresses generated by testing the same failure storage particle in a first physical slot, and forming a first error physical address set; collecting all second error physical addresses generated by testing the same invalid storage particle in the second physical slot to form a second error physical address set; the first error physical address set and the second error physical address set are searched, k address bits are found, the binary logic values of the k address bits or the logic combination of the k address bits at all the first error physical addresses are constantly the same value, and the binary logic values of the k address bits or the logic combination of the k address bits at all the second error physical addresses are constantly the inverse value of the same value; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. According to the method, hidden physical address decoding logic can be automatically restored, and automatic, accurate and efficient positioning of the physical position of the failure storage particle is realized.

The application provides a control circuit for an airborne radar or a pilot switch, belongs to the technical field of airborne computers, and specifically utilizes a heartbeat signal and a watchdog circuit of an FPGA to ensure that the system continues to output a stable signal only after the FPGA normally operates, and enables the bus driver to be timely cut off in an abnormal state. The uncertainty of the IO port output state of the FPGA is converted into a determinable safe output state through exclusive or logical combination operation of a judgment circuit, and the fault tolerance of the system is enhanced. The opening and closing states of a magnetic latching relay are read back by using the FPGA, and the state of the magnetic latching relay when powered on is confirmed. The safety state design of the application not only improves the reliability of the system, but also simplifies the circuit design, significantly reduces the risk of overall circuit failure caused by single-point failure, and thus ensures the high safety of the airborne radar or the pilot switch control.

Embodiments of the present invention provide a custom control method, device, and energy storage system for an energy storage system. The custom control method includes: associating logically combined trigger conditions with at least one execution action, whereby the execution action corresponds to a control command from at least one digital output interface to form user-defined control rules; real-time acquisition of operating parameters of the energy storage system; periodic judgment of the trigger conditions in the user-defined control rules based on the acquired operating parameters; and when the trigger condition is satisfied, executing the associated execution action, generating a corresponding control command, and outputting it through a corresponding digital output interface to control the operating status of external devices. The solution of the present invention improves the flexibility and personalization of rule configuration for home energy storage systems.

A server builds an update file to update software. The server compiles source code of an updated version of the software, generating a binary file of the updated version of the software. Memory locations are mapped to sections of the binary file based on mappings of sections of a binary file of a prior version of the software. Bits of sections of a plurality of sections of the binary file of the prior version are logically combined, bit-by-bit, with bits of corresponding sections of the binary file of the updated version. The logically combining includes: applying an exclusive or operation; or applying an exclusive nor operation. The update file is built based on the mapping of the memory locations and on results of the logical combining.

This invention discloses a multi-source oscillating true random number generator based on configurable logic combination enable control. It introduces a user-controllable multi-logic combination mechanism, fusing internal entropy with external input to achieve dynamic and diversified generation of enable signals. Specifically, the true random number generator includes: a random signal generation module, a sampling module, a post-processing module, and a configurable logic combination control unit. The random signal generation module includes N ring oscillators RO_i, each with an independent enable port EN_i, outputting an oscillation signal only when EN_i=1, i=0~N-1. The sampling module is connected to the output of each ring oscillator for asynchronous sampling of the output. Typically, a low-frequency sampling clock can be used to asynchronously sample the high-frequency output of each ring oscillator. This invention enables dynamic and diversified generation of enable signals, improving the anti-attack capability of the entropy source.

This application provides a true random number generation circuit, which continuously generates and outputs random bits through an entropy source module, then uses a sampling module to collect and output random bits according to an external clock signal to improve the randomness of the output random bits, and finally uses an encryption operation module to perform shift and logical combination operations on the random bits to ensure that the output random bits meet both the quantity requirements and the randomness requirements, thereby obtaining a high-quality random number sequence.

This invention provides a method and system for defining triggering conditions and actions in industrial control. The method includes: Step S1, configuring triggering logic, combinational logic, and basic actions on a host computer to generate a configuration file; Step S2, sending the configuration file to a secondary computer; Step S3, the secondary computer collects monitoring data through sensors and performs triggering logic operations on the monitoring data based on the triggering logic carried in the configuration file to obtain the triggering logic operation result; Step S4, the script engine of the secondary computer performs combinational logic operations based on the triggering logic operation result and the combinational logic carried in the configuration file to obtain the combinational logic operation result; Step S5, based on the combinational logic operation result, segmenting the action combination expression to obtain an action chain list; Step S6, controlling the corresponding actuator to execute basic actions based on the action chain list. The advantages of this invention are: greatly improving the flexibility and scalability of triggering conditions and action definitions.

The invention relates to the technical field of rail transit braking control, and discloses a rail transit braking heavy fault control circuit and method based on hardware logic. The circuit is applied to a multi-marshalling train and comprises at least two CAN units, two brake main valves which are redundant to each other are arranged in each unit, and BOGI1 and BOGI2 signals indicating frame brake faults are output. Through logic combination design in the units and between the units, accurate judgment of fault signals is realized. Or logic operation is adopted in the units, BOGI1 signals among the units adopt AND logic, BOGI2 signals among the units adopt OR logic, and a brake heavy fault relay is jointly controlled. When any relay is powered on, a braking heavy fault signal is output, emergency braking is triggered, and safe operation of the train is ensured.

The application discloses a clock synchronization method and device, wherein the clock synchronization method comprises the following steps: presetting a first field on an incoming direction port table; the first field defines whether a peer chip of an incoming direction connection is a chip supporting a synchronization domain; presetting a second field on an outgoing direction port table; the second field defines whether a peer chip of an outgoing direction connection is a chip supporting a synchronization domain; and according to a logical combination of the first field and the second field, a CF value of a PTP message is selected to be updated to adapt to a chip stacking system in a synchronization domain or a non-synchronization domain. Through the device and the method, the problems of low time precision or poor system expansion of an existing PTP TC clock synchronization mechanism can be solved.

The embodiment of the invention provides an automatic skill combination method and device based on an AI agent, equipment and a storage medium. The method comprises the following steps: pre-constructing a skill library in which atomic skills are stored; the AI agent retrieves a matched atomic skill in a skill library according to a target combination demand; and checking the retrieved atomic skills, and carrying out logic combination on the plurality of atomic skills passing the checking to generate a combined skill. In addition, an intermediate result of executing each link by the AI agent is stored in an audit log, and a skill version snapshot corresponding to the combined skill is recorded. When the combined skill is executed, whether the actual version of the current atomic skill is compatible with the version in the skill version snapshot or not is detected, and if the versions are not compatible or execution fails, an audit log is traced back, reasons are positioned, and suggestion information is output. According to the method and the device, end-to-end automatic generation from user requirements to executable combined skills is realized, and the robustness and the maintainability of the system in a dynamic environment are improved.

Techniques for sharing processor data within a network are disclosed. A system-on-a-chip (SOC) is accessed. The SOC includes a network-on-a-chip (NOC), which comprises an M×N mesh topology. The mesh includes a coherent tile at each mesh point. Each tile includes local snoop vectors (LSVs). A first coherent tile initiates a snoop operation. The tile generates a snoop vector that indicates other tiles to be notified of the snoop operation. The first coherent tile creates directional snoop vectors (DSVs). The creating logically combines the snoop vector with each of the LSVs. A coherent tile adjacent to the first coherent tile is selected. The adjacent tile is located in a cardinal direction from the first tile. A first DSV is chosen based on the cardinal direction. The first tile sends the snoop operation and the chosen first DSV to the selected adjacent tile.

The present disclosure provides a memory control method, a memory controller and an electronic device. The memory control method is executed by programmable circuitry for controlling a target memory, and includes: detecting, by the programmable circuitry, a plurality of target events in real time; when a type and a number of the detected target events satisfy a trigger condition of any one of a plurality of preset states, selecting to run an action execution circuit module corresponding to the preset state, the trigger condition including a logical combination of one target event or a plurality of target events; and executing, by the action execution circuit module corresponding to the preset state, one or more actions corresponding to the preset state, at least one of the one or more actions being used for controlling the target memory. The embodiments of the present disclosure can flexibly configure a memory control scheme and improve the efficiency of sending control signals to the memory.

The embodiment of the application discloses a data query method and system based on a large language model, which comprises the following steps: receiving natural language data for describing a target population, performing semantic analysis on the natural language data, extracting semantic elements related to population screening, and forming an initial condition element set; inputting the initial condition element set into a preset large language model, and converting the initial condition element set into a structured label condition group; based on pre-constructed automobile label metadata and corresponding mapping rules, performing field mapping and value conversion processing on condition elements in the structured label condition group to obtain standardized label condition data matched with a target database; logically combining the standardized label condition data to construct a hierarchical condition structure; generating a query statement executable for the target database based on the hierarchical condition structure, and screening user data in the database by using the query statement to obtain target user data.

The invention provides a large-bit-width cyclic redundancy check calculation method and device, and relates to the field of integrated circuit design. The method comprises the following steps: asymmetrically dividing input data into at least one first type data block and a plurality of second type data blocks; in the first clock period, carrying out parallel calculation on all the data blocks to generate and latch an intermediate check value; and in a second clock period, selecting a target intermediate check value according to the effective length control signal, and carrying out logic combination on the target intermediate check value and a feedback check value generated based on the result of the previous period to generate a final check result. According to the method, the time sequence performance is remarkably improved through the two-stage pipeline architecture, meanwhile, the hardware resource consumption is optimized through the asymmetric division strategy, and the balance between the performance and the area is achieved.

This invention belongs to the field of auxiliary equipment protection and control technology, and relates to an auxiliary equipment protection system and method for tripping when the outlet valve is fully closed. The system includes a signal acquisition unit, a runtime sequence control unit, an outlet valve full-closure timing control unit, an outlet valve status anti-jitter and anomaly detection unit, an anomaly alarm unit, and a multi-condition tripping integrated unit. By acquiring the auxiliary equipment operating status, outlet valve position, upstream pressure, and downstream flow signals, and after delay processing to avoid startup and instantaneous interference, it uses a combination of NOT gates and pulse logic to identify valve status anomalies, and combines this with S-R triggers to implement alarms and interlocking. Finally, it generates a tripping command based on multi-condition logic integration. This invention solves the problems of false tripping, failure to tripping, and unknown anomalies that easily occur under traditional single-point signal or combinational logic, significantly improving the reliability and safety of the auxiliary equipment protection system.

This application provides a method and apparatus for generating sine and cosine signals. Based on trigonometric and angle formulas, it generates sine signals by pre-configured base values ​​and pipelined multiply-accumulate iterations to generate iterative values, thus avoiding the complex logic of DDS data cache management and Cordic multi-round iterative calculations. Furthermore, the m-stage pipelined multiply-accumulate module breaks down the logical combination of multiplication and addition operations in the multiply-accumulate operation into m clock cycles, thereby optimizing the FPGA's operating frequency. This embodiment relies only on common logic operations such as accumulation counting, data selection, and basic multiply-accumulate, eliminating the need for the large amount of BRAM required in the DDS scheme to store complete sine wave data. It also avoids the large-scale parallel iterative logic required by the Cordic scheme to ensure accuracy and throughput. In actual implementation, only a small number of LUT tables and DSP resources are needed, significantly reducing the FPGA's hardware resource consumption.

The embodiment of the invention provides an LCU system architecture with function safety, a control method and equipment, and is applied to the technical field of power electronics. The system architecture comprises at least two security hosts, IO board cards corresponding to the security hosts and a backboard parallel bus used for connecting the security hosts and the corresponding IO board cards. Wherein the security host comprises a processor, the IO board card is a non-intelligent board card without a processor, and the security host directly accesses and controls each input and output point location on the IO board card in an address mapping mode through the backboard parallel bus. According to the invention, the system is centralized to the security host, the IO board card is degraded into a pure and program-free logic combination circuit, the host directly controls each IO point location through the parallel bus in an address mapping mode, a processor on the IO board card is canceled, software development, protocol design and field configuration work related to the IO board card are fundamentally eliminated, the operation process is simplified, and the operation efficiency is improved. And potential software fault points are reduced.

A scalable and configurable clustered systolic array is described. An example of apparatus includes a cluster including multiple cores; and a cache memory coupled with the cluster, wherein each core includes multiple processing resources, a memory coupled with the plurality of processing resources, a systolic array coupled with the memory, and one or more interconnects with one or more other cores of the plurality of cores; and wherein the systolic arrays of the cores are configurable by the apparatus to form a logically combined systolic array for processing of an operation by a cooperative group of threads running on one or more of the plurality of cores in the cluster.