48 results about "Logical combination" patented technology

The invention discloses a data quality intelligent auditing system and method based on a dynamic rule base, and belongs to the technical field of data auditing, and the system comprises a rule base construction module which is used for analyzing business scene parameters through a scene analysis unit according to business scene demands and data type features to generate a rule configuration instruction; the multi-source monitoring engine module is connected to the rule base construction module and is used for collecting multi-source data in real time and loading corresponding checking rules; the automatic verification execution module is used for executing normalized quality verification on the multi-source data based on the verification rule base; and the feedback optimization module analyzes a rule hit rate and a false alarm rate in a verification result through a reinforcement learning algorithm, and dynamically iteratively updates a rule threshold value and a logic combination in the rule base. By constructing a full-automatic process of rule generation, execution, feedback and updating, the problems that a traditional system depends on manual intervention, response is slow, the industry average rule updating period is 3-7 days, and real-time updating is achieved through the scheme are solved.

The invention discloses a decentralized identity management method based on a trusted execution environment, and the method comprises the steps: generating, isolating and storing a user decentralized identity in the trusted execution environment of equipment, carrying out the Hash signature of a decentralized identity document, and recording an uplink; the block chain consensus node verifies the decentralized document uplink transaction through a Byzantine fault-tolerant consensus mechanism and achieves consistency, and writes the metadata of the decentralized identity into the block; encrypting and storing the voucher in a trusted execution environment of the equipment by adopting a Pearson commitment, and supporting voucher Hash uplink and commitment uplink; and introducing a multilevel access structure based on a binary tree, and verifying the and / or logic combination voucher by adopting a depth-first search algorithm. According to the method, decentralized autonomy of the user identity and hardware security isolation are supported, and the reliability and privacy protection capability of user identity management are improved.

The invention relates to the technical field of artificial intelligence, and provides a code generation method, device and equipment based on an AI agent and a computer readable storage medium. First, initial description information is analyzed through the AI agent, and an initial task element component corresponding to a target code is determined; the target big language model further generates a related question list of the target code according to the initial description information and the initial task element component, and executes interactive inquiry on the target user based on the related question list to obtain supplementary description information of the target code, and then analyzes the supplementary description information through the AI agent to obtain the supplementary description information of the target code. And determining a supplementary task element component corresponding to the target code. And finally, generating a target code based on the initial task element component, the supplementary task element component and the component combinatorial logic combination. Therefore, the code is automatically generated through the AI agent and the target large language model, the code generation efficiency is improved, and the user experience is improved.

Apparatuses, methods, and systems for filtering entities within a database. One method includes identifying a user-defined query, wherein the user-defined query comprises multiple user-defined segment definitions, wherein an original format of each of the user-defined segment definitions includes logical filters, mapping each logical filter to one or more of the user-defined segment definitions, executing each of the logical filters on entities of the database, wherein each of the logical filters is executed a single time, storing filtered results in a mapped format based on the executing of the logical filters according to the mapping in the database, converting from the mapped format into the original format of the user-defined segment definitions that represents the set of entities that qualify for user-defined segments, identifying which entities qualify to be included within the user-defined segment definitions comprising logically combining the conditions and the condition groups.

Performance monitoring circuitry (40) has event counters (42) that each maintain a respective event count value based on monitoring events during processing of software by the processing circuitry. A control circuit (44) configures the event counter based on the counter configuration information. For at least a subset of the event counters, a given event counter (42) within the subset supports a chained counter operation that includes incrementing the given event count value by an increment value determined based on a logical combination of a first event state indication and a second event state indication, the first event state indication indicates a state of a first event type assigned by the counter configuration information to be monitored by a given event counter, and the second event state indication indicates a state of a second event type assigned by the counter configuration information to be monitored by a further event counter.

Receiving a codeword of a forward error correction (FEC) code, each codeword in the FEC code having a minimum distance of at least seven to any other codeword in the FEC code, calculating multi-bit syndromes by applying columns of a check matrix to the received codeword using combinatorial logic, and responsively determining the received codeword comprises at least three errors, determining coefficients of an error locator polynomial using a coefficient combinatorial logic circuit by combining the multi-bit syndromes using non-iterative combinatorial logic performing arithmetic operations in a finite field F(2 n ), determining respective error positions for each error of the at least three errors by determining roots of the error locator polynomial using a non-iterative root-finding combinatorial logic circuit, the non-iterative root-finding combinatorial logic circuit performing arithmetic operations in the finite field F(2 n ), and correcting each of the at least three errors in the received codeword.

The invention discloses a control method for intelligent and accurate connection of a high-speed wire packaging machine and a gasket adding device. The control method comprises the following steps: firstly, designing a gasket adding and packaging control mode, a related action time sequence, a logic interlocking condition and an instruction driving unit; then, a gasket feeding in-place signal is transmitted to a packer control system, and a packing time sequence and logic interlocking are updated; the packer control system obtains a prepared signal of the gasket feeding equipment system, performs combined control with a time sequence driving command of the packer control system and designs a new instruction; then, a gasket adding device selection input state signal is transmitted to a packer control system for interlocking combination design; meanwhile, logic combination and signal output design are carried out on relevant states and commands of the packing machine and are transmitted to the gasket adding device; the in-situ state of the baling head and the pressing disc of the baling machine is set as an associated interlocking control signal of the gasket adding device; and finally, a new interlocking program is designed in a gasket adding device control system according to the single-channel and double-channel states of the packing machine, and intelligent and accurate connection of the two is achieved.

The present application relates to the technical field of data query, in particular to a multi-index horizontal expansion data processing method and system, comprising the following steps: collecting time series and dimension attributes to generate a business detail wide table, matching non-empty measure fields to form independent index logic, combining rule nodes to build a general materialized architecture, and outputting multi-index processing results through scheduling mapping and window aggregation. In the present application, a wide table is constructed in the model layer and atomic and derived indexes are centrally managed, realizing a unified index definition method independent of dimension combination. When a user queries, dimension parameters are dynamically combined by the query engine to automatically build an aggregation statement and calculate the result, avoiding the problem of derived index explosion caused by the expansion of the number of dimensions. Meanwhile, multi-index joint analysis is completed in the same materialized table without the need for multiple table joins, improving query execution efficiency, having high adaptability to index updates and dimension changes, and significantly reducing data development and operation and maintenance burden.

The invention discloses a physical-level anti-quantum key packaging device and method, and the method comprises the steps: cutting off a byte stream to a first modulus through a bit mask operation, and generating a polynomial matrix in a constant physical clock period; calculating an inner product of a private key vector of the polynomial matrix, executing logic combination operation, compressing modulus, and generating a public key vector; after receiving the public key vector, the second communication node reconstructs a system state by using the temporary private key and outputs a ciphertext; and the first communication node receives the ciphertext, performs fault-tolerant restoration and re-encryption, drives a bottom multiplexer to generate a mask, and selects one of a real session key and a random noise key to be output in a constant physical clock period. According to the anti-quantum cryptography algorithm, logic combination operation, algebraic divide-and-conquer and physical circuit characteristics are utilized, hardware simplification is achieved, meanwhile, safety is improved, strategic expansion capacity is achieved, and the problems that an existing anti-quantum cryptography algorithm faces the computing power bottleneck and the side channel attack risk in a low-power-consumption node lacking a hardware divider circuit are solved.

The invention relates to the technical field of networks, in particular to a network data packet analysis system, and provides a system for network data packet analysis, which comprises a protocol decoding engine, a graph optimization engine and a graph traversal engine, in a protocol decoding engine, a plain text concise language specification is adopted to describe basic logic and logic combination of formal languages, description of logic combination and complex nested structures is supported, high expression ability and good readability are achieved, the design is concise enough, the manufacturing difficulty of decoding scripts and the total number of codes can be greatly reduced, and the decoding efficiency is improved. In the graph optimization engine and the graph traversal engine, grammar logic of an original graph structure processed by the protocol decoding engine is converted into graph logic by adopting a graph algorithm to realize performance optimization during operation, and flexible analysis of different types of protocols is supported for a multi-graph engine architecture; and a graph structure designed in a classified manner comprises a character string graph, a regular graph and the like, and a standardized graph traversal mechanism is realized by unifying a multi-graph traversal engine.

The invention relates to the technical field of networks, in particular to an interpretation language generation method and device suitable for protocol decoding and a medium, and provides an interpretation language suitable for protocol decoding. The method supports the description of logic combination and complex nested structures, has strong expression ability and good readability, is simple enough in design, greatly reduces the manufacturing difficulty and reading difficulty of decoding scripts and the total amount of codes, and greatly shortens the development period. Meanwhile, in protocol decoding, each network protocol is regarded as a formal language, abstraction is carried out to describe most protocols, an interpretation language which is concise in design is designed to standardize and describe basic logic and combination of the formal language, a plain text protocol decoding script is used for replacing a traditional hard coding decoder, and a complete three-level grammar system of words, sentences and segments is constructed.

The embodiment of the application discloses a decoding logic derivation method, a failed storage particle positioning method and related equipment, comprising: collecting all first error physical addresses generated by testing a same failed storage particle in a first physical slot to form a first error physical address set; collecting all second error physical addresses generated by testing the same failed storage particle in a second physical slot to form a second error physical address set; searching the first error physical address set and the second error physical address set to find k address bits, or a logical combination thereof, which is always a same value in binary logic values of all the first error physical addresses and is always an opposite value of the same value in binary logic values of all the second error physical addresses; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. The application can automatically restore hidden physical address decoding logic and realize automatic, accurate and efficient positioning of the physical position of the failed storage particle.

The invention discloses a heterogeneous computing power-oriented tensor parallel optimization method and system, and the method comprises the steps: dividing computing equipment in a heterogeneous computing cluster into primary cards and secondary cards, carrying out the logic combination simulation of a plurality of secondary cards into a virtual primary tensor parallel node, and enabling each primary card to independently serve as a primary tensor parallel node; executing secondary tensor parallel cutting on a primary tensor parallel node simulated by a secondary card; local matrix calculation is executed on the secondary tensor parallel nodes, All-Gather operation is carried out through a built-in high-speed network, and intermediate results of all secondary cards are combined into a complete calculation result of the simulated primary tensor parallel nodes; and carrying out All-Gather operation among the first-level tensor parallel nodes through a cross-machine network to finish final tensor calculation convergence. According to the method and the device, the heterogeneous computing resources and the network resources can be managed, and the problems of load imbalance, communication bottleneck and low resource utilization rate caused by non-uniformity of the computing power in the heterogeneous computing environment are effectively solved.

According to the sinusoidal signal generation method and device and the cosine signal generation method and device provided by the invention, based on triangle and angle formula expansion, a sinusoidal signal is generated in a manner of generating an iterative value through preconfiguration of a basic value and pipeline multiplication and addition iteration, and complex logics such as data cache management of a DDS and multi-round iterative calculation of Cordic are avoided. Moreover, the multiply-add operation module of the m-level assembly line splits the logic combination of multiplication and addition operation in multiply-add operation into m clock periods, so that the operation frequency of the FPGA is optimized. The method only depends on common logic operations such as accumulative counting, data selection and basic multiplication and addition, a large number of BRAMs for storing sine wave complete data in a DDS scheme are not needed, large-scale parallel iterative logic needed by a Cordic scheme for guaranteeing precision and throughput rate is also avoided, only a small number of LUT tables and DSP resources are needed in actual implementation, and hardware resource occupation of an FPGA is greatly reduced.

The invention provides a control circuit for an airborne radar or a conduction switch, belongs to the technical field of airborne computers, and particularly ensures that a system continues to output stable signals only after an FPGA (Field Programmable Gate Array) is normally operated by utilizing heartbeat signals of the FPGA and a watchdog circuit, and bus driver enabling is timely cut off in an abnormal state. The uncertainty of the IO port output state of the FPGA is converted into a determinable safe output state through the XOR and logic combination operation of the judgment circuit, and the fault-tolerant capability of the system is enhanced. And reading back the opening and closing state of the magnetic latching relay by using the FPGA, and confirming the power-on state of the magnetic latching relay. The safety state design not only improves the reliability of the system, but also simplifies the circuit design, and significantly reduces the risk of failure of the whole circuit caused by a single-point fault, thereby ensuring the high safety of airborne radar or conduction switch control.

The embodiment of the invention discloses a decoding logic derivation method, a failure storage particle positioning method and related equipment, and the method comprises the steps: collecting all first error physical addresses generated by testing the same failure storage particle in a first physical slot, and forming a first error physical address set; collecting all second error physical addresses generated by testing the same invalid storage particle in the second physical slot to form a second error physical address set; the first error physical address set and the second error physical address set are searched, k address bits are found, the binary logic values of the k address bits or the logic combination of the k address bits at all the first error physical addresses are constantly the same value, and the binary logic values of the k address bits or the logic combination of the k address bits at all the second error physical addresses are constantly the inverse value of the same value; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. According to the method, hidden physical address decoding logic can be automatically restored, and automatic, accurate and efficient positioning of the physical position of the failure storage particle is realized.

The application provides a control circuit for an airborne radar or a pilot switch, belongs to the technical field of airborne computers, and specifically utilizes a heartbeat signal and a watchdog circuit of an FPGA to ensure that the system continues to output a stable signal only after the FPGA normally operates, and enables the bus driver to be timely cut off in an abnormal state. The uncertainty of the IO port output state of the FPGA is converted into a determinable safe output state through exclusive or logical combination operation of a judgment circuit, and the fault tolerance of the system is enhanced. The opening and closing states of a magnetic latching relay are read back by using the FPGA, and the state of the magnetic latching relay when powered on is confirmed. The safety state design of the application not only improves the reliability of the system, but also simplifies the circuit design, significantly reduces the risk of overall circuit failure caused by single-point failure, and thus ensures the high safety of the airborne radar or the pilot switch control.

The invention relates to the technical field of software testing, and provides an automatic test case obtaining method and device, equipment and a storage medium, and the method comprises the steps: splitting a target algorithm expression of a software product in a development stage into a first type of algorithm elements and a second type of algorithm elements; the first type of algorithm elements comprise variables, constants and / or functions, and the second type of algorithm elements comprise operators; constructing an algorithm element matrix according to the first type of algorithm elements; generating a full-amount algorithm element logic combination according to the algorithm element matrix and the second type of algorithm elements; automatically generating a test case subset corresponding to each algorithm element logic combination; and when a test case acquisition request for a specified test object associated with the target algorithm expression is received, matching a test case subset corresponding to the specified test object so as to test the specified test object. According to the embodiment of the invention, the timeliness of software testing can be improved.

The invention belongs to the crossing field of aviation equipment guarantee and predictive maintenance, and relates to an SIMD (Single Instruction Multiple Data) multi-thread distributed parallel interpretation calculation method, which comprises the following steps of: forming a hardware acceleration closed loop without software intervention through single calculation nodes (SIMD vectorization processing), RDMA (Remote Direct Memory Access) network (submicrosecond transmission) and FPGA (Field Programmable Gate Array) (nanosecond timing verification); a four-level thread assembly line of data prefetching, arithmetic operation, logic combination and threshold comparison is constructed, state vectors calculated by all threads are directly written into an RDMA registration memory pool, zero-copy transmission of the state vectors among nodes is achieved through RDMA, a distributed state machine is introduced to achieve duration tracking, and the reliability of the RDMA registration memory pool is improved. Cooperative verification is initiated when the timer value is greater than or equal to the preset duration threshold, so that the feature interpretation delay and the threshold updating delay are greatly reduced, the network bandwidth occupation and the communication overhead are reduced, and the interpretation speed is greatly improved while the accuracy is ensured.

An adaptive system for managing, in an integrated way, multiple EC with variable configuration, with prosumer and / or proconstomer and / or constorer nodes that are dynamically aggregated over the time, through a partitionable digital platform that includes logics for the automatic management. To each platform portion corresponds an EC and an oriented combination of logics in turn selected, sequenced and parametrized according to the optimization purposes provided by the EC, to locally implement, through the controller of each node, the commands imparted to its devices and optimize energy flows, by first adapting to EC logics and then to single node logics. The oriented combination is continually recalculated, within 50 milliseconds from the reading of the data of each aggregated node, to adapt in real time to the variable configuration of an EC and its nodes.

The invention belongs to the technical field of communication scheduling, and relates to a converged communication scheduling method and system based on an intelligent command console, and the method comprises the following steps: building a static binding relation between an action role and a key equipment resource, and generating a comprehensive task instruction set; matching according to the comprehensive task instruction set to generate a dynamic resource situation map; setting a communication scheduling strategy taking a logic combination of a personnel state and a key equipment resource operation state bound with the personnel as a trigger condition, and forming a resource linkage type scheduling rule base; generating a scheduling trigger signal; packaging the communication action into an automatic dispatching instruction packet; establishing a temporary task dedicated communication channel for the specified communication participant; and starting a channel dismantling program to release communication resources, and completing closed-loop adaptive scheduling. The problems that distribution and management of communication resources are extensive, automatic adjustment is difficult to achieve according to dynamic changes of task scenes, and the overall commanding and dispatching efficiency is reduced are solved.

Embodiments of the present invention provide a custom control method, device, and energy storage system for an energy storage system. The custom control method includes: associating logically combined trigger conditions with at least one execution action, whereby the execution action corresponds to a control command from at least one digital output interface to form user-defined control rules; real-time acquisition of operating parameters of the energy storage system; periodic judgment of the trigger conditions in the user-defined control rules based on the acquired operating parameters; and when the trigger condition is satisfied, executing the associated execution action, generating a corresponding control command, and outputting it through a corresponding digital output interface to control the operating status of external devices. The solution of the present invention improves the flexibility and personalization of rule configuration for home energy storage systems.

The invention provides a trigger condition and action definition method and system for industrial control in the technical field of industrial control, and the method comprises the steps: S1, configuring a trigger logic, a combinational logic and a basic action by an upper computer to generate a configuration file; s2, sending the configuration file to a middle computer; s3, the middle computer collects monitoring data through a sensor, trigger logic operation is carried out on the monitoring data based on trigger logic carried by the configuration file, and a trigger logic operation result is obtained; s4, the script engine of the middle computer performs combinational logic operation based on the trigger logic operation result and combinational logic carried by the configuration file to obtain a combinational logic operation result; step S5, segmenting the action combination expression to obtain an action chain table based on a combination logic operation result; and S6, controlling a corresponding execution mechanism to execute the basic action based on the action chain table. The method has the advantages that the flexibility and expansibility of the triggering condition and action definition are greatly improved.

A server builds an update file to update software. The server compiles source code of an updated version of the software, generating a binary file of the updated version of the software. Memory locations are mapped to sections of the binary file based on mappings of sections of a binary file of a prior version of the software. Bits of sections of a plurality of sections of the binary file of the prior version are logically combined, bit-by-bit, with bits of corresponding sections of the binary file of the updated version. The logically combining includes: applying an exclusive or operation; or applying an exclusive nor operation. The update file is built based on the mapping of the memory locations and on results of the logical combining.

This invention discloses a multi-source oscillating true random number generator based on configurable logic combination enable control. It introduces a user-controllable multi-logic combination mechanism, fusing internal entropy with external input to achieve dynamic and diversified generation of enable signals. Specifically, the true random number generator includes: a random signal generation module, a sampling module, a post-processing module, and a configurable logic combination control unit. The random signal generation module includes N ring oscillators RO_i, each with an independent enable port EN_i, outputting an oscillation signal only when EN_i=1, i=0~N-1. The sampling module is connected to the output of each ring oscillator for asynchronous sampling of the output. Typically, a low-frequency sampling clock can be used to asynchronously sample the high-frequency output of each ring oscillator. This invention enables dynamic and diversified generation of enable signals, improving the anti-attack capability of the entropy source.

The present disclosure relates to a vehicle electronics technology, in particular to a method, an apparatus, and a non-transitory computer-readable storage medium storing computer programs / instructions for implementing the method for diagnosing a vehicle fault, and a computer program product. The method comprises the following steps: in response to a trigger event monitored by a buried point, determining a first fault matched with the trigger event by using a first fault diagnosis model; when the matched first fault does not exist, a second fault diagnosis model is used for determining a second fault associated with a trigger event, the trigger event is a first abnormal event or a second abnormal event, the first fault diagnosis model defines the corresponding relation between the first fault and the first abnormal event, and the second fault diagnosis model defines the corresponding relation between the first fault and the second abnormal event. The second fault diagnosis model defines a correspondence between i) a second fault and ii) a fault feature or a logical combination of a plurality of fault features associated with a second anomalous event, the fault features being determined based on the vehicle operating state information.

This application provides a true random number generation circuit, which continuously generates and outputs random bits through an entropy source module, then uses a sampling module to collect and output random bits according to an external clock signal to improve the randomness of the output random bits, and finally uses an encryption operation module to perform shift and logical combination operations on the random bits to ensure that the output random bits meet both the quantity requirements and the randomness requirements, thereby obtaining a high-quality random number sequence.

A security coprocessor 200 for use with a processor having a stack is configured to receive a tag value 204 from the processor, generate a canary value 206 based on the tag value and a salt, and return the canary value to the processor for incorporation in the stack. The canary value may be generated as logical combination of bits of the tag and bits of the salt such that different tags are guaranteed to yield different canary values and / or for any two different tags, each is a function of at least one salt bit that the other is not a function of. In another embodiment, a security coprocessor is configured to receive a redundant value from the processor, validate the redundant value and issue a panic instruction if the redundant value is not valid. In a further embodiment, a security coprocessor is configured to initiate a counter in response to a write counter instruction, and in response to a check counter instruction including a count value, check that the count value matches a current value of the counter and increment the counter.

This invention provides a method and system for defining triggering conditions and actions in industrial control. The method includes: Step S1, configuring triggering logic, combinational logic, and basic actions on a host computer to generate a configuration file; Step S2, sending the configuration file to a secondary computer; Step S3, the secondary computer collects monitoring data through sensors and performs triggering logic operations on the monitoring data based on the triggering logic carried in the configuration file to obtain the triggering logic operation result; Step S4, the script engine of the secondary computer performs combinational logic operations based on the triggering logic operation result and the combinational logic carried in the configuration file to obtain the combinational logic operation result; Step S5, based on the combinational logic operation result, segmenting the action combination expression to obtain an action chain list; Step S6, controlling the corresponding actuator to execute basic actions based on the action chain list. The advantages of this invention are: greatly improving the flexibility and scalability of triggering conditions and action definitions.

The invention relates to the technical field of rail transit braking control, and discloses a rail transit braking heavy fault control circuit and method based on hardware logic. The circuit is applied to a multi-marshalling train and comprises at least two CAN units, two brake main valves which are redundant to each other are arranged in each unit, and BOGI1 and BOGI2 signals indicating frame brake faults are output. Through logic combination design in the units and between the units, accurate judgment of fault signals is realized. Or logic operation is adopted in the units, BOGI1 signals among the units adopt AND logic, BOGI2 signals among the units adopt OR logic, and a brake heavy fault relay is jointly controlled. When any relay is powered on, a braking heavy fault signal is output, emergency braking is triggered, and safe operation of the train is ensured.