8 results about "Branch predictor" patented technology

Embodiments of this disclosure provide an instruction processing method and apparatus, a processor, an electronic device, and a storage medium. The instruction processing method includes, in response to identifying a first conditional branch instruction with a back jump from an instruction stream, recording instruction information of the first conditional branch instruction; in response to identifying the first conditional branch instruction with a back jump at least once more, determining that the first conditional branch instruction is an end branch instruction in a loop body instruction and performing a backfilling operation on the loop body instruction, the loop body instruction including at least one second branch instruction other than the first conditional branch instruction; performing the backfilling operation on the loop body instruction includes: backfilling the instruction information of the second branch instruction into an instruction information cache; invoking a branch predictor to obtain first prediction information of the second branch instruction, and backfilling the first prediction information into a branch instruction information cache. This instruction processing method expands the scope of loop body instruction recognition and reduces cache access power consumption.

Embodiments of the present specification relate to the field of computers, and provide a processor branch prediction method, device, equipment, storage medium and product, comprising: in a program execution process, using a fixed-capacity global history register to record the jump direction of an executed branch instruction, to obtain a global history register value; in response to a function call instruction in a program execution flow, generating function call information corresponding to the function call instruction; at a program point where branch prediction is needed, obtaining a plurality of function call information corresponding to the executed function call instruction and generating a function call history register value; concatenating the function call history register value and the global history register value to obtain enhanced history information; and using a branch predictor to perform processor branch direction prediction based on the enhanced history information. Through the embodiments of the present specification, the length of the used history information can be increased on the basis of using lower hardware overhead, thereby improving the accuracy of processor branch prediction.

The application relates to the technical field of processor verification, and provides a RISC-V branch predictor closed-loop verification method and system, which comprises the following steps: providing a plurality of test modes facing a branch predictor micro-architecture, each test mode corresponds to a branch behavior feature and has a parameterized configuration; receiving a random seed, selecting a target test mode from the plurality of test modes based on the random seed, and determining parameters for the target test mode; generating a corresponding RISC-V assembly test program according to the target test mode and the parameters, so as to perform closed-loop verification on the RISC-V branch predictor. Through the parameterized test mode facing the micro-architecture and the random seed driving mechanism, efficient closed-loop verification is realized, the problem that test excitation randomness is too high or simulation time is too long in the prior art is solved, and the verification efficiency is effectively improved.

This specification relates to the field of computer technology, and in particular to a multi-level branch predictor, a branch prediction method, a processor, and an electronic device. The multi-level branch predictor includes a first-level direction predictor, a second-level direction predictor, and a consistency determiner. The consistency determiner queries consistency entry records based on the instruction information of the current instruction to obtain the prediction consistency confidence level. When the prediction consistency confidence level meets a preset condition, the first-level direction prediction result generated by the first-level direction predictor based on the instruction information of the current instruction is used as the final direction prediction result, and a first control signal is output to prevent the second-level direction predictor from starting. This eliminates the power consumption caused by redundant high-precision prediction calculations for a large number of simple branch instructions, thereby significantly reducing the dynamic power consumption of the branch prediction module and even the entire processor, and improving the system's energy efficiency ratio.

This invention provides a microprocessor and a branch prediction control method. In one embodiment, a microprocessor includes: a table including a plurality of edges, wherein at least a first edge includes a first conditional branch predictor having a first set of prediction tables, wherein at least a second edge includes a second conditional branch predictor having a second set of prediction tables, wherein the second conditional branch predictor is configured to provide a first prediction based on a prediction table hit for a branch instruction including information in the second edge, and wherein the first conditional branch predictor has higher complexity than the second conditional branch predictor; and control logic, wherein, based on receiving an indication of an incorrect prediction corresponding to the first prediction for the branch instruction, the control logic is configured to write information for the branch instruction into one of the first set of prediction tables of the first edge.

An apparatus includes a branch predictor to generate a prediction associated with a branch instruction outcome for a block of at least one instruction. The branch predictor includes: lookup circuitry configured to perform a lookup of stored prediction information to identify a plurality of prediction entries associated with alternative paths of program flow, the plurality of prediction entries comprising a main prediction entry to be used for generating the prediction and one or more alternative prediction entries each associated with an alternative path of program flow; prediction generation circuitry configured to generate the prediction based on the main prediction entry; and alternative prediction storage circuitry configured to store the one or more alternative prediction entries identified by the lookup circuitry; in which responsive to a flush signal indicative of the prediction being incorrect, the prediction generation circuitry is configured to generate an alternative prediction associated with the block of the at least one instruction based on the one or more alternative prediction entries stored by the alternative prediction storage circuitry.

An apparatus and method for an instruction cache miss throttler. An example method comprises: storing instructions in an instruction cache; predicting, by a branch predictor circuit, whether one or more branch instructions will result in taken branches and responsively providing IPs corresponding to the predicted taken branches; storing the IPs corresponding to the predicted taken branches, wherein the IPs are to be used to perform a lookup for corresponding instructions in the instruction cache; storing IPs of instructions from the fetch queue which missed in the instruction cache, the IPs to indicate instructions to be filled into the instruction cache from the memory subsystem; tracking a number of cachelines which resulted in instruction cache misses since a last predicted branch was taken; and throttling the branch predictor circuit in response to a threshold reached for the number of cachelines which resulted in instruction cache misses.