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175 results about "Branch predictor" patented technology

In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g. an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow in the instruction pipeline. Branch predictors play a critical role in achieving high effective performance in many modern pipelined microprocessor architectures such as x86.

Instruction acquisition control method based on simultaneous multithreading

The invention provides an instruction acquisition control method based on simultaneous multithreading, which includes the steps: in each clock cycle of a processor, reading a PC (personable computer) value of instructions by an instruction acquisition component according to a program counter, selecting two threads with high priority as instruction acquisition threads firstly, and then computing the actual instruction number required by each instruction acquisition thread so as to read the instructions; according to an IPC (inter-process communication) value and the Cache failure rate, enabling a dual-priority resource allocation mechanism to compute system resources required by the threads in an instruction acquisition stage and complete dynamic allocation of the resources; matching a TBHBP (thread branch history branch predictor) with the instruction acquisition operations of the instruction acquisition component, acquiring a pattern type match position Sc by connecting global historical information with local historical information read by a branch instruction Bi to utilize as an index of a secondary PHT (pattern history table), and inputting computed results to a BRT (branch result table); and when the branch instruction Bi is executed again, judging whether CONF fields are larger than or equal to 2 or not by the aid of a selector, directly outputting the recorded branch results if the CONF fields are larger than or equal to 2, and finally placing the acquired instruction into an instruction Cache, so that all operations of instruction acquisition control are completed.
Owner:HARBIN ENG UNIV

Branch prediction apparatus and method for low power consumption

A branch prediction apparatus may include a first branch predictor for executing a first branch prediction algorithm and a second branch predictor for executing a second branch prediction algorithm. A choice predictor may generate a control signal for controlling operations of the first branch predictor and the second branch predictor. The choice predictor may also select and output a prediction result of the first branch predictor or the second branch predictor. The first branch predictor and the second branch predictor may respectively execute the prediction algorithms depending on the control signal. The choice predictor may include a shift register for shifting stored branch prediction values of the branch prediction apparatus to the left by one bit. A choice prediction table may be indexed by a value of the shift register to output a predictor selection value. A predictor selecting unit may generate the control signal and a selection signal for selecting an output of one of the first and the second branch predictors. An MUX circuit may output a branch prediction value of the first branch predictor or a branch prediction value of the second branch predictor depending on the selection signal. A computer-readable medium may include instructions causing a computer to perform the functions of selecting one branch predictor from among a plurality of branch predictors by using previous branch prediction results, and executing a branch prediction for a branch instruction by using the selected branch predictor.
Owner:SAMSUNG ELECTRONICS CO LTD

System and method for processing jump instruction of microprocessor in branch prediction way

The invention discloses a system and a method for processing a jump instruction of a microprocessor in a branch prediction way. The system comprises a coding module and a transmission module, wherein the coding module comprises a branch predictor used for predicting by adopting a static prediction method when the jump instruction to be processed is in the jump execution type or adopting a dynamicprediction method when the jump instruction to be processed is not in the jump execution type after the coding module judges that an instruction to be processed is the jump instruction and judges thetype of the jump instruction through precoding, and directly writing the jump instruction to be processed and a delay slot instruction thereof in an operational queue in a sequence of the instructions in a program; and the transmission module comprises a prediction result processor used for canceling the instruction executed by error and continue fetching in a correct jump direction when the branch predictor predicts the jump instruction by error after the jump instruction is executed and written back to the transmission module. The system cancels operation by adopting different cancellation methods on the basis that whether the instruction is the jump execution instruction or not when the instruction is cancelled.
Owner:LOONGSON TECH CORP

Branch predictor, system and method of branch prediction

A method, system and branch predictor for branch prediction. The system includes a processor core for executing instructions, a branch target buffer for fetching a branch address, and a branch predictor for first predicting a branch of a current instruction address and indicating to the processor core when to fetch the branch address from the branch target buffer. A branch predictor, including a branch prediction table for storing a plurality of branch prediction values of previous branch instructions, and a controller for selecting one of the plurality of branch prediction values and outputting the selected one of the plurality of branch prediction values to a processor core, the selected one of the plurality of branch prediction values indicating to the processor core when to fetch a branch address from a branch target buffer. A method of branch prediction, including first outputting a current instruction address from a processor core to a branch predictor, predicting whether a branch occurs based on the received current instruction address and a global history, and second outputting a branch prediction value from the branch predictor to the processor core, the branch prediction value indicating whether the processor core fetches a branch address from a branch target buffer.
Owner:SAMSUNG ELECTRONICS CO LTD
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