44 results about "Branch predictor" patented technology

The invention discloses a branch prediction unit power consumption management method and device, and the method comprises the steps: setting a multi-stage branch predictor and a low-power-consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, and enabling the multi-stage branch predictor to comprise three stages of predictors which are sequentially accessed in an assembly line, the hardware resource consumption and the prediction accuracy of each predictor are gradually increased from front to back; monitoring the prediction condition of each predictor in real time through low-power-consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement within a first preset time according to a front-to-back sequence; branch jump addresses are divided into high-order address fields and low-order address fields by BTBs in the multiple levels of predictors except the first-level predictor to be stored in different storage blocks, and label registers used for taking the high-order addresses as label indexes are arranged. The power consumption unit of each predictor can be finely controlled, the energy consumption is greatly reduced, system-level cooperation is not needed, and the universality is high.

The invention discloses a hybrid branch predictor capable of dynamically selecting different prediction methods and application, and relates to the technical field of high-performance processor design, the hybrid branch predictor mainly comprises a branch direction predictor and a branch target predictor; the branch direction predictor is used for predicting whether a branch instruction jumps or not; and the branch target predictor is used for predicting a specific jump target address when the branch direction is predicted to be jump. By implementing the hybrid branch predictor capable of dynamically selecting different prediction methods and the application provided by the invention, the branch prediction accuracy can be improved, and the hardware resource overhead can be reduced.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.

A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.

A microprocessor includes a prediction unit (PRU) comprising a fetch block (FBlk) predictor (FBP) that predicts a sequence of FBlks, each FBlk having a corresponding fetch block start address (FBSA), and branch predictors; a macro-op (MOP) cache (MOC) includes MOC entries (MEs) including multi-FBlk MOC entries (MF-MEs) for holding MOPs decoded from instructions of multiple FBlks. The PRU detects a hit of a current FBSA on an MF-ME; performs a set of actions K times: looking up the current FBSA in the FBP and branch predictors to obtain outputs, using the outputs to predict a successor FBSA of a successor FBlk; and making the current FBSA the successor FBSA; and predicts that an FBSA of a successor FBlk to the MF-ME is the current FBSA resulting from performing K times the set of actions. K is a number of FBlks built into the MF-ME (alternatively times a loop unroll factor).

This application relates to adjustable branch prediction methods and microprocessors. In one embodiment, a microprocessor includes prediction logic including a branch predictor including a set of multiple-set associative tables, each table corresponding to a different length branch pattern history, and control logic configured to provide an adjustable write policy for the prediction logic.

The invention relates to the technical field of processors, and provides a memory dependency prediction method and device based on a branch predictor and a processor architecture, and the method comprises the steps: selecting a prediction block from an instruction fetching queue; determining a target load instruction in the prediction block; and predicting memory dependence information of the target load instruction according to global branch historical information of the branch direction predictor. According to the embodiment of the invention, the prediction precision of memory dependency prediction can be improved, the memory dependency prediction cost can be reduced, and the method is suitable for a modern processor which is high in performance, performs out-of-order execution and is provided with a decoupling front-end framework.

A processing unit executes a sequence of instructions comprising a branch instruction and selects a target branch predictor for the branch instruction from a plurality of branch predictors. The selection is based on a language model trained on a set of training instruction sequences that comprise branch instructions. The target branch predictor then determines the outcome of the branch instruction. The language model is trained to identify the branch instructions as having easy-to-predict outcomes or hard-to-predict outcomes based on sequence of instructions. Information generated by the language model is provided to a branch prediction unit, which uses the information to determine whether branch instructions are easy-to-predict or hard-to-predict.

Embodiments of this disclosure provide an instruction processing method and apparatus, a processor, an electronic device, and a storage medium. The instruction processing method includes, in response to identifying a first conditional branch instruction with a back jump from an instruction stream, recording instruction information of the first conditional branch instruction; in response to identifying the first conditional branch instruction with a back jump at least once more, determining that the first conditional branch instruction is an end branch instruction in a loop body instruction and performing a backfilling operation on the loop body instruction, the loop body instruction including at least one second branch instruction other than the first conditional branch instruction; performing the backfilling operation on the loop body instruction includes: backfilling the instruction information of the second branch instruction into an instruction information cache; invoking a branch predictor to obtain first prediction information of the second branch instruction, and backfilling the first prediction information into a branch instruction information cache. This instruction processing method expands the scope of loop body instruction recognition and reduces cache access power consumption.

The invention discloses a hardware Trojan horse design method based on an RISC-V architecture processor branch predictor, and relates to the field of processors and hardware Trojan horses. The hardware Trojan horse designed by the invention is divided into three parts: an interference triggering module, an interference signal generator and a control signal generator, and can implement hidden attack on a branch predictor in a processor. The hardware Trojan is based on a condition triggering mechanism, and allows an attacker to set a specific triggering condition according to the actual operation state and environment of the system, so that the interference behavior is accurately controlled. When the interference triggering module detects a predefined triggering instruction, the interference signal generator generates a specific interference signal and injects the specific interference signal into the branch predictor, so that normal work of the branch predictor is interfered, and the performance of the processor is reduced. Aiming at the working principle of the branch predictor, a targeted interference mode and a non-targeted interference mode are designed and can be flexibly selected according to requirements. The purposeless interference mode comprises a random interference mode and a branch historical interference mode, and disordered interference is carried out on a processor branch prediction mechanism. The purposeful interference mode directly interferes the normal operation process of the processor by modifying the content of the branch target buffer in a targeted manner. The hardware Trojan can effectively interfere the normal operation of the branch predictor, so that the overall performance of the processor is remarkably reduced.

The application relates to a fine-grained processor chip branch predictor content isolation method based on randomization index and an electronic device. It comprises a unit program block random key configuration method and a branch predictor content locking mechanism, unit program block random key configuration is realized through process key distribution and block key instruction generation, and branch predictor content locking is realized through entry locking of a branch jump target address table and a branch mode history table. Meanwhile, process key distribution is realized through random numbers of software or hardware, process keys are generated, block key instructions are generated through source code analysis and executable file analysis, and program blocks with security risks are identified; block keys are generated based on the calculation of a cryptography algorithm and program block context information through a code segment or an instruction for generating a block key. The application also has the advantages of more flexible key management, convenient content locking mechanism, more effective randomization index, great difficulty in attack training and safe and reliable branch prediction.

Circuits and methods for conditional fence instructions are described. In some examples, a hardware processor (e.g., a core) includes a branch predictor to predict one of an taken path and an untaken path of a conditional branch instruction; decoder circuitry to decode an instruction to a decoded instruction, the instruction including a field indicating a condition set by executing another instruction and an opcode indicating that the execution circuitry will implement an execution fence in response to the condition being satisfied to delay execution of the instruction prior to execution of a previous instruction in a program order, the opcode indicating that the execution circuitry will implement the execution fence in response to the condition being satisfied. And before the instruction is executed, delaying execution of an instruction following the instruction according to the program order; and the execution circuit is used for executing the decoded instruction according to the operation code.

The invention provides a processor and a branch predictor. The processor comprises a branch predictor with a cache module and a register module, and the branch predictor is configured to execute the following branch prediction process: matching a low-order TAG of a current branch instruction address with a TAG domain in a target table entry of the cache module, the target table entry corresponding to an index field of the current branch instruction address, the TAG domain in the target table item is used for storing a low-order TAG of a historical branch instruction address; if the low-order TAG of the current branch instruction address is matched with the TAG domain in the target table item of the cache module, a high-order index is obtained, and the high-order index points to a high-order TAG table item corresponding to the low-order TAG recorded in the TAG domain in the target table item in a high-order TAG table; matching the high-order TAG of the current branch instruction address with the high-order TAG in the high-order TAG table entry; and if the high-order TAG of the current branch instruction address is matched with the high-order TAG in the high-order TAG table entry, determining that the branch prediction is hit. The resource utilization rate and the prediction accuracy can be considered.

Disclosed is a branch predictor unit (BPU), comprising a first branch predictor configured to generate a first prediction of a branch based at least in part on a first prediction entry point of two predictions prior to the first prediction, and a second branch predictor configured to generate a second prediction of the branch based at least in part on a second prediction entry point of one prediction prior to the second prediction, wherein either the first prediction or the second prediction is generated based on a determination of whether the branch follows a flush.

Embodiments of the present disclosure provide a branch predictor for multiple threads, an operating method, a processor, an electronic device and a storage medium. The branch predictor comprises multiple tag prediction tables of different levels, and the multiple threads share the multiple tag prediction tables. The operating method comprises: setting a tag offset value for the multiple threads; and in response to an operation of a target thread in the multiple threads on the multiple tag prediction tables, determining a storage area corresponding to the target thread for each tag prediction table based on a target tag offset value corresponding to the target thread and a prediction table identifier of each tag prediction table. The operating method can alleviate the capacity competition problem of different threads on the same branch predictor, reduce the interference between threads, and improve the branch prediction accuracy.

This disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium. The method includes: responding to the current instruction being a conditional branch instruction, using a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the current instruction being a loop branch instruction, using a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the second prediction result differing from the first prediction result, using the second prediction result to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

The invention relates to the technical field of processor verification, and provides an RISC-V branch predictor closed-loop verification method and system, and the method comprises the steps: providing a plurality of branch predictor micro-architecture-oriented test modes, and each test mode corresponds to a branch behavior feature and has parameterized configuration; receiving a random seed, selecting a target test mode from the plurality of test modes based on the random seed, and determining parameters for the target test mode; and according to the target test mode and the parameters thereof, generating a corresponding RISC-V assembly test program so as to perform closed-loop verification on the RISC-V branch predictor. According to the method and the device, efficient closed-loop verification is realized through a micro-architecture-oriented parameterized test mode and a random seed driving mechanism, the problem that the test excitation randomness is too high or the simulation time is too long in the prior art is solved, and the verification efficiency is effectively improved.

This invention discloses a formal verification method for processor branch prediction attack vulnerabilities, comprising the following steps: S1, establishing the security attributes violated by the branch prediction attack, wherein the security attributes describe the security specifications that a secure branch predictor design should comply with; S2, establishing a branch prediction behavior model, describing the branch prediction attack as a combination of a series of abstract branch operations; wherein the branch operation is a quintuple consisting of operator, operation type, operation address, jump direction, and jump address, which is an abstract representation of a certain branch instruction; S3, modeling the branch predictor design as accepting branch prediction behavior instructions, and designing different variations of the branch prediction model state machine according to different input instructions, outputting the prediction result, checking the security specifications, and converting the branch prediction attack into a path specification on the state machine; S4, performing model verification on the state machine of the branch predictor design to determine whether it has a branch prediction attack vulnerability.

Embodiments of the present specification relate to the field of computers, and provide a processor branch prediction method, device, equipment, storage medium and product, comprising: in a program execution process, using a fixed-capacity global history register to record the jump direction of an executed branch instruction, to obtain a global history register value; in response to a function call instruction in a program execution flow, generating function call information corresponding to the function call instruction; at a program point where branch prediction is needed, obtaining a plurality of function call information corresponding to the executed function call instruction and generating a function call history register value; concatenating the function call history register value and the global history register value to obtain enhanced history information; and using a branch predictor to perform processor branch direction prediction based on the enhanced history information. Through the embodiments of the present specification, the length of the used history information can be increased on the basis of using lower hardware overhead, thereby improving the accuracy of processor branch prediction.

The application discloses a multi-stage branch predictor supporting branch target buffer compression and a prediction method. The predictor comprises a three-stage structure. The first-stage branch predictor is a single-cycle predictor, which is used for giving a prediction result in one cycle. The second-stage branch predictor is a double-cycle predictor, which is used for giving a prediction result in the second cycle. The third-stage branch predictor is a triple-cycle predictor, which is used for giving a prediction result in the third cycle. A per-cycle PC multiplexer simultaneously sends the selected PC into the three-stage branch predictor, and the three-stage branch predictor respectively gives corresponding prediction results. The low delay of the low-stage predictor guarantees the continuous flow of instructions in the pipeline. The high accuracy of the high-stage predictor reduces the pipeline refresh times caused by branch prediction failure. The combination of the short prediction cycle of the low-stage branch predictor and the high prediction accuracy of the high-stage branch predictor optimizes and compresses the branch target buffer structure of the branch predictor, and reduces the area of the branch target buffer.

The invention provides a prediction method, a branch predictor and a processor, when different threads run the same program, if the branch predictor shares data of each thread among the threads, whether a tag in a historical prediction table is the same as a tag to be compared is compared, and if yes, the data of each thread is obtained. And taking the jump direction of the saturation counter in the historical prediction table corresponding to the branch history with the same label and the to-be-compared label and the longest historical length as the predicted jump direction. If the branch predictor independently stores the data of each thread, comparing whether a label and a to-be-compared label in the historical prediction table are the same or not and whether a thread label and a thread number are the same or not, and historically corresponding a branch with the same label and the to-be-compared label, the same thread label and the same thread number and the longest historical length to the historical prediction table, and the jump direction of the saturation counter is used as a prediction jump direction, so that table entries can be shared among threads, the threads corresponding to the table entries can be distinguished, the error prediction rate of simultaneous multi-thread processor branch prediction is reduced, and the instruction fetching efficiency is improved.

A processing unit executes a sequence of instructions comprising a branch instruction and selects a target branch predictor for the branch instruction from a plurality of branch predictors. The selection is based on a language model trained on a set of training instruction sequences that comprise branch instructions. The target branch predictor then determines the outcome of the branch instruction. The language model is trained to identify the branch instructions as having easy-to-predict outcomes or hard-to-predict outcomes based on sequence of instructions. Information generated by the language model is provided to a branch prediction unit, which uses the information to determine whether branch instructions are easy-to-predict or hard-to-predict.

The application provides a novel double-branch prediction BTB structure, belonging to the technical field of BTB structure, and comprising the following steps: S1, an improved BTB structure design step, which comprises a multi-path group association structure link and a multi-target address storage link, and further comprises branch information association, each branch instruction is associated with a corresponding Tgt and a label field according to its position in an instruction block; S2, a BTB query and data reading step, which comprises an input PC processing link, a Tag matching and hit determination link and a data reading link; S3, a parallel branch prediction step, which comprises a branch predictor cooperative working link and a prediction result output link; in view of the problem that the traditional method can only predict a single branch or has limitations on the prediction of multiple branches, the application can generate at most two jump target addresses in the same period, thereby improving the branch prediction throughput.

The invention provides an automatic circuit design method of a TAGE branch predictor, which comprises the following steps: constructing a superscalar front-end simulator comprising a branch prediction unit, an instruction cache, an instruction queue and a prediction information cache, and simulating processor front-end behaviors through parameterized configuration; a time sequence and combinatorial logic decoupling normal form is introduced into the branch prediction unit, the branch prediction unit is decomposed into a time sequence component and a combinatorial logic component, the time sequence component comprises a global historical register, a folding historical register and a multi-stage prediction table, and the combinatorial logic component comprises a metadata generation unit, a direction prediction unit, a table item updating unit and a historical maintenance unit; obtaining input and output data of the branch prediction unit in the execution process; and based on the input and output data, generating a hardware description language code of the combinatorial logic component by using an automatic circuit design algorithm so as to realize automatic circuit design of the TAGE branch predictor. Therefore, the design efficiency and the performance of automatically designing the branch prediction component can be improved.

The invention provides a novel instruction prefetching method and device based on FDIP and electronic device.The method comprises the steps that after a target instruction block address enters a target instruction fetching queue, the target instruction block address is matched with a label array of instruction cache for the first time; when it is determined that an instruction block corresponding to the target instruction block address is in an instruction cache, locking a target cache line corresponding to the target instruction block address, and unlocking the target cache line after an instruction fetching process of the target instruction block address is completed; when the target instruction block becomes the first entry of the target fetch queue, the fetch unit obtains the target instruction block from the instruction cache. According to the scheme, after the branch predictor generates the target instruction block address, the target instruction block address only needs to be matched with the tag array once, so that access conflicts and dynamic power consumption caused by two times of matching can be avoided, additional area overhead is avoided, the performance of a CPU can be improved, and the power consumption of the CPU can be reduced.

A branch predictor predicts a first outcome for a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. In response to taking the first predicted outcome, information representing a remainder of the first block is stored. In response to not taking the first branch instruction, the branch predictor is restarted based on the remainder block. In some cases, an address of the first block is used as an index into a branch prediction structure to access an entry corresponding to a second block along a speculative path from the first block. A corresponding set of instances of branch condition logic are used to simultaneously predict outcomes for branch instructions in the second block, and in response to a misprediction, the predicted outcomes are used in combination with the remainder block to restart the branch predictor.

A microprocessor efficiently performs instruction prefetching, having an instruction cache, a branch predictor, a fetch target queue coupled between the branch predictor and the instruction cache, and a comparator. The instruction cache caches contents for fetching in response to a fetch address. The fetch target queue stores at least one instruction address predicted by the branch predictor to be in a branch direction, to be read out as the fetch address, or output as a plurality of prefetch candidate addresses for selection as a prefetch address to operate the instruction cache for instruction prefetching. The comparator compares the plurality of prefetch candidate addresses with a previous prefetch address to determine which prefetch candidate address is the prefetch address, to exclude instruction prefetching of consecutive instructions of the same cache line.

Embodiments of the present application provide a branch predictor, a related device and a branch prediction method. The branch predictor comprises a base predictor and a plurality of labeled branch predictors with labels, wherein each labeled branch predictor has two storage units, a first storage unit is a single-port storage unit, used to store a high bit of a saturation counter and a flag bit in a label prediction table corresponding to the current labeled branch predictor; and a second storage unit is a dual-port storage unit, used to store a low bit of the saturation counter and a valid bit in the label prediction table corresponding to the current labeled branch predictor. Embodiments of the present application are suitable for various chips including CISC instruction set, RISC instruction set (especially RISC-V instruction set) or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips, etc.

The application relates to the technical field of processor verification, and provides a RISC-V branch predictor closed-loop verification method and system, which comprises the following steps: providing a plurality of test modes facing a branch predictor micro-architecture, each test mode corresponds to a branch behavior feature and has a parameterized configuration; receiving a random seed, selecting a target test mode from the plurality of test modes based on the random seed, and determining parameters for the target test mode; generating a corresponding RISC-V assembly test program according to the target test mode and the parameters, so as to perform closed-loop verification on the RISC-V branch predictor. Through the parameterized test mode facing the micro-architecture and the random seed driving mechanism, efficient closed-loop verification is realized, the problem that test excitation randomness is too high or simulation time is too long in the prior art is solved, and the verification efficiency is effectively improved.

Embodiments of the present application provide a branch prediction method, a branch predictor and related devices, wherein the method comprises: obtaining address information and first identification information of a to-be-predicted instruction; based on the address information, obtaining a target address of a target instruction corresponding to the to-be-predicted instruction and redundancy information of the target address, which are stored in advance, the redundancy information comprising second identification information and permission information; if the to-be-predicted instruction is a user state instruction, determining whether the first identification information and the second identification information are consistent; if the first identification information and the second identification information are consistent, allowing access of the target address to be executed; if the to-be-predicted instruction is a kernel state instruction, determining whether the permission information is a privilege level identification; if yes, and the first identification information and the second identification information are consistent or inconsistent, allowing access of the target address to be executed. Embodiments of the present application can improve the instruction processing efficiency.