105 results about "Branch predictor" patented technology

A quantum computer, comprising: at least one CPU and at least one QPU. The CPU includes: a branch predictor configured to form one or more result predictions or algorithm branches of a result of a measurement being performed or to be performed by the QPU; a compiler configured to generate respective sets of quantum gates corresponding to each of the one or more result predictions by performing respective one or more compilation tasks, each of the compilation tasks comprising compiling a portion of a hybrid quantum algorithm; and a quantum gate selector configured to receiving the result of the measurement and respond by passing to the QPU a set of quantum gates from the sets of quantum gates that corresponds to the result of the measurement.

The embodiment of the invention provides a branch prediction method, a branch predictor, a processor and an electronic device. The branch predictor comprises a plurality of label prediction tables of different levels, each table item of each label prediction table in the plurality of label prediction tables comprises a prediction value representing a prediction result of the corresponding table item, and the branch prediction method comprises the following steps: in response to a selected target table item, obtaining a target prediction result based on the prediction value of the target table item; and in response to the target prediction result error, judging whether to apply for a new table item with a higher level than the target table item. According to the branch prediction method, performance loss caused by the fact that a traditional TAGE branch predictor only uses a prediction result of a high table and extra power consumption caused by application of the high table can be reduced.

The invention discloses a branch prediction unit power consumption management method and device, and the method comprises the steps: setting a multi-stage branch predictor and a low-power-consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, and enabling the multi-stage branch predictor to comprise three stages of predictors which are sequentially accessed in an assembly line, the hardware resource consumption and the prediction accuracy of each predictor are gradually increased from front to back; monitoring the prediction condition of each predictor in real time through low-power-consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement within a first preset time according to a front-to-back sequence; branch jump addresses are divided into high-order address fields and low-order address fields by BTBs in the multiple levels of predictors except the first-level predictor to be stored in different storage blocks, and label registers used for taking the high-order addresses as label indexes are arranged. The power consumption unit of each predictor can be finely controlled, the energy consumption is greatly reduced, system-level cooperation is not needed, and the universality is high.

The invention discloses a branch predictor selection method and device and a storage medium. The method comprises the steps of obtaining record data of a target jump instruction in a local historical register and a global historical register based on the target jump instruction; determining an instruction type of the target jump instruction based on the recorded data; determining a load state of the processor based on the operation parameters of the processor; and determining a target predictor according to the instruction type and the load state, and outputting a branch prediction result based on the target predictor. According to the selection method provided by the invention, the prediction accuracy can be improved, the adaptability is higher, the energy consumption is reduced, and the optimal balance between the prediction accuracy and the energy efficiency is realized.

Disclosed techniques relate to branch prediction and trace caching. A processor may include both an instruction cache and a trace cache configured to store instructions. A branch predictor may include one or more prediction tables (e.g., tagged geometric length (TAGE) tables) configured to predict directions of conditional control transfer instructions. Rather than including a separate branch predictor for branches in the trace cache, the processor may share the prediction table(s) for instruction cache and trace cache predictions. In particular, the processor may include an additional trace prediction lane configured to access the prediction table to predict a direction of a final control transfer instruction in a trace cached by the trace cache circuitry. This may advantageously provide accurate predictions with limited impacts to circuit area and power consumption, e.g., relative to a separate predictor for the trace cache.

The invention discloses a hybrid branch predictor capable of dynamically selecting different prediction methods and application, and relates to the technical field of high-performance processor design, the hybrid branch predictor mainly comprises a branch direction predictor and a branch target predictor; the branch direction predictor is used for predicting whether a branch instruction jumps or not; and the branch target predictor is used for predicting a specific jump target address when the branch direction is predicted to be jump. By implementing the hybrid branch predictor capable of dynamically selecting different prediction methods and the application provided by the invention, the branch prediction accuracy can be improved, and the hardware resource overhead can be reduced.

The invention discloses a branch prediction attack prevention method and device, a chip and a medium. The method comprises the steps of determining a program category of a program to which a target branch instruction belongs; if the program category is a security trusted program, determining the configuration condition of a branch predictor; when it is determined that a first preset branch predictor and a second preset branch predictor exist according to the configuration condition of the branch predictors, predicting the target branch instruction by using the second preset branch predictor; when determining that a first preset branch predictor exists according to the configuration condition of the branch predictor, determining that the first preset branch predictor predicts an enabling state of a target branch instruction, and processing the target branch instruction according to the enabling state; wherein the first preset branch predictor is used for predicting a branch instruction of the unsecure trusted program. By adopting the method, the risk of branch prediction can be reduced on hardware and software, the safety of branch prediction is ensured, and the probability of sensitive information leakage is reduced.

The invention discloses a test case generation method, a branch predictor verification method and related equipment, and the test case generation method comprises the steps: obtaining a target global branch historical sequence which is generated by a TAGE branch predictor in a target application scene; according to the target global branch historical sequence, a corresponding target linear address sequence is obtained, and the target linear address sequence is obtained by arranging addresses of a plurality of target branch instructions in a target branch instruction stream in sequence; and according to the obtained multiple target linear address sequences, generating a target test case for testing the target branch instruction stream. According to the technical scheme provided by the embodiment of the invention, the verification coverage rate of the TAGE branch predictor can be improved, so that the verification efficiency and accuracy of the TAGE branch predictor are improved.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.

The invention belongs to the technical field of cloud computing heterogeneous resource scheduling, and particularly provides a multi-architecture virtualization environment integration and unified operation and maintenance method and system, and the method comprises the steps: detecting the underlying hardware characteristics of a source architecture and a target architecture; generating a hardware semantic abstract model based on the underlying hardware characteristics; carrying out compatibility analysis on the cross-architecture virtual machine instruction stream, and identifying atomic operation semantic conflicts and interrupt routing logic conflicts; generating an instruction translation rule and a micro-architecture cleaning strategy; converting an instruction stream and cleaning a branch predictor of a source architecture and a residual state of an out-of-order execution buffer area; and synchronizing the cleaned micro-architecture state and the conversion instruction stream to the target virtual machine. According to the method and the system, instruction stream conversion in a virtual machine migration process can be dynamically matched with micro-architecture characteristics of a target architecture, seamless connection of execution environments in a cross-architecture migration process is realized, cross-architecture conflicts can be prevented, and the problems of migration conflicts and performance degradation of the virtual machine of a virtualization platform are solved.

A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.

The invention discloses a sleep apnea detection method and system based on a multi-mode audio signal, and the method comprises the following steps: obtaining a trachea sound and an environment sound of a sleep record, and dividing the trachea sound and the environment sound into audio segments, respectively extracting trachea sound features and environment sound features from the trachea sound and the environment sound of each audio clip, calculating a corresponding trachea sound weight and a corresponding environment sound weight, and carrying out weighted fusion on the trachea sound features and the environment sound features of each audio clip to obtain corresponding multi-mode audio features; and detecting an abnormal breathing event for each multi-mode audio feature by using an enhanced branch pre-device, and evaluating the severity of sleep apnea according to the number of the detected abnormal breathing events. According to the invention, the accuracy and sensitivity of sleep apnea detection are obviously improved.

The embodiment of the invention provides a data processing method, a branch predictor and related equipment, the method is applied to the branch predictor, prediction data are stored in the branch predictor, and the prediction data comprise prediction data belonging to a host mode and prediction data belonging to a virtual machine mode; the method comprises the following steps: acquiring a data disabling command, wherein the data disabling command is sent out in a mode switching process of a host mode and a virtual machine mode; and based on the data disabling command, disabling prediction data belonging to a virtual machine mode in the branch predictor, and keeping prediction data belonging to a host mode in the branch predictor in an available state. According to the embodiment of the invention, the instruction prediction efficiency can be improved on the premise of ensuring the data security.

The invention provides a cyclic branch prediction instruction fetching device, a processor and electronic equipment. A reference unit generates a reference address according to acquired address data; the instruction storage unit reads a historical reference address to pre-fetch an instruction, and when the instruction storage unit is hit, after K clock cycles, a target instruction corresponding to the historical reference address is transmitted to the first branch predictor; the first branch predictor is used for reading a historical reference address, performing address prediction according to the historical reference address and a target instruction corresponding to the historical reference address, and providing a predicted address to the reference unit; and the second branch predictor is used for reading the historical reference address, and providing the stored cycle start address to the reference unit under the condition that the historical reference address is the same as the cycle end address stored in the historical reference address and the number of to-be-cycled times is greater than 0. The instructions are reduced to maintain cyclic variables and judgment conditions, so that the complexity and maintenance difficulty of codes can be reduced, the acquisition efficiency of the instructions is improved, and the performance potential of a processor is fully exerted.

A microprocessor includes a prediction unit (PRU) comprising a fetch block (FBlk) predictor (FBP) that predicts a sequence of FBlks, each FBlk having a corresponding fetch block start address (FBSA), and branch predictors; a macro-op (MOP) cache (MOC) includes MOC entries (MEs) including multi-FBlk MOC entries (MF-MEs) for holding MOPs decoded from instructions of multiple FBlks. The PRU detects a hit of a current FBSA on an MF-ME; performs a set of actions K times: looking up the current FBSA in the FBP and branch predictors to obtain outputs, using the outputs to predict a successor FBSA of a successor FBlk; and making the current FBSA the successor FBSA; and predicts that an FBSA of a successor FBlk to the MF-ME is the current FBSA resulting from performing K times the set of actions. K is a number of FBlks built into the MF-ME (alternatively times a loop unroll factor).

A branch predictor predicts a first outcome of a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. Information representing a remainder of the first block is stored in response to the first predicted outcome being taken. In response to the first branch instruction being not taken, the branch predictor is restarted based on the remainder block. In some cases, entries corresponding to second blocks along speculative paths from the first block are accessed using an address of the first block as an index into a branch prediction structure. Outcomes of branch instructions in the second blocks are concurrently predicted using a corresponding set of instances of branch conditional logic and the predicted outcomes are used in combination with the remainder block to restart the branch predictor in response to mispredictions.

Systems, methods, and other embodiments associated with branch prediction in workflows are described. In one embodiment, a branch predictor is configured to make branch predictions at decision elements of a workflow that executes serially, by at least: monitoring the workflow to identify when a decision element is encountered during execution. In response to encountering a first decision element in the workflow that includes a plurality of branch paths: (i) executing a prediction that predicts a resulting path of the first decision element to predict a first user interface from a plurality of possible user interfaces that are associated with the workflow; and (ii) pre-building the first user interface into memory including a structure and content configured for being rendered on a display. The pre-built first user interface is then displayed on a display device when the workflow reaches a first terminal element associated with the first user interface.

This application relates to adjustable branch prediction methods and microprocessors. In one embodiment, a microprocessor includes prediction logic including a branch predictor including a set of multiple-set associative tables, each table corresponding to a different length branch pattern history, and control logic configured to provide an adjustable write policy for the prediction logic.

Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

The invention relates to the technical field of processors, and provides a memory dependency prediction method and device based on a branch predictor and a processor architecture, and the method comprises the steps: selecting a prediction block from an instruction fetching queue; determining a target load instruction in the prediction block; and predicting memory dependence information of the target load instruction according to global branch historical information of the branch direction predictor. According to the embodiment of the invention, the prediction precision of memory dependency prediction can be improved, the memory dependency prediction cost can be reduced, and the method is suitable for a modern processor which is high in performance, performs out-of-order execution and is provided with a decoupling front-end framework.

A processing unit executes a sequence of instructions comprising a branch instruction and selects a target branch predictor for the branch instruction from a plurality of branch predictors. The selection is based on a language model trained on a set of training instruction sequences that comprise branch instructions. The target branch predictor then determines the outcome of the branch instruction. The language model is trained to identify the branch instructions as having easy-to-predict outcomes or hard-to-predict outcomes based on sequence of instructions. Information generated by the language model is provided to a branch prediction unit, which uses the information to determine whether branch instructions are easy-to-predict or hard-to-predict.

The embodiment of the invention provides a branch predictor for multiple threads, an operation method, a processor, electronic equipment and a storage medium. The branch predictor comprises a plurality of label prediction tables of different levels, a plurality of threads share the plurality of label prediction tables, and the operation method comprises the following steps: setting label offset values for the plurality of threads; and in response to an operation of a target thread in the plurality of threads on the plurality of label prediction tables, determining a storage area, corresponding to the target thread, of each label prediction table based on a target label deviation value corresponding to the target thread and respective prediction table identifiers of the plurality of label prediction tables. According to the operation method, the problem of capacity competition of different threads for the same branch predictor can be relieved, the interference between the threads is reduced, and the branch prediction precision is improved.

Embodiments of this disclosure provide an instruction processing method and apparatus, a processor, an electronic device, and a storage medium. The instruction processing method includes, in response to identifying a first conditional branch instruction with a back jump from an instruction stream, recording instruction information of the first conditional branch instruction; in response to identifying the first conditional branch instruction with a back jump at least once more, determining that the first conditional branch instruction is an end branch instruction in a loop body instruction and performing a backfilling operation on the loop body instruction, the loop body instruction including at least one second branch instruction other than the first conditional branch instruction; performing the backfilling operation on the loop body instruction includes: backfilling the instruction information of the second branch instruction into an instruction information cache; invoking a branch predictor to obtain first prediction information of the second branch instruction, and backfilling the first prediction information into a branch instruction information cache. This instruction processing method expands the scope of loop body instruction recognition and reduces cache access power consumption.

The invention discloses a hardware Trojan horse design method based on an RISC-V architecture processor branch predictor, and relates to the field of processors and hardware Trojan horses. The hardware Trojan horse designed by the invention is divided into three parts: an interference triggering module, an interference signal generator and a control signal generator, and can implement hidden attack on a branch predictor in a processor. The hardware Trojan is based on a condition triggering mechanism, and allows an attacker to set a specific triggering condition according to the actual operation state and environment of the system, so that the interference behavior is accurately controlled. When the interference triggering module detects a predefined triggering instruction, the interference signal generator generates a specific interference signal and injects the specific interference signal into the branch predictor, so that normal work of the branch predictor is interfered, and the performance of the processor is reduced. Aiming at the working principle of the branch predictor, a targeted interference mode and a non-targeted interference mode are designed and can be flexibly selected according to requirements. The purposeless interference mode comprises a random interference mode and a branch historical interference mode, and disordered interference is carried out on a processor branch prediction mechanism. The purposeful interference mode directly interferes the normal operation process of the processor by modifying the content of the branch target buffer in a targeted manner. The hardware Trojan can effectively interfere the normal operation of the branch predictor, so that the overall performance of the processor is remarkably reduced.

The application relates to a fine-grained processor chip branch predictor content isolation method based on randomization index and an electronic device. It comprises a unit program block random key configuration method and a branch predictor content locking mechanism, unit program block random key configuration is realized through process key distribution and block key instruction generation, and branch predictor content locking is realized through entry locking of a branch jump target address table and a branch mode history table. Meanwhile, process key distribution is realized through random numbers of software or hardware, process keys are generated, block key instructions are generated through source code analysis and executable file analysis, and program blocks with security risks are identified; block keys are generated based on the calculation of a cryptography algorithm and program block context information through a code segment or an instruction for generating a block key. The application also has the advantages of more flexible key management, convenient content locking mechanism, more effective randomization index, great difficulty in attack training and safe and reliable branch prediction.

The invention provides an instruction processing method and device, electronic equipment, a chip and a storage medium, and the method comprises the steps: employing a first branch predictor to predict the branch direction of a current instruction in response to the current instruction being a conditional branch instruction, so as to obtain a first prediction result; wherein the first prediction result is used for indicating whether jumping occurs or not after the current instruction is executed; in response to the current instruction being a cyclic branch instruction, predicting the branch direction of the current instruction by adopting a second branch predictor to obtain a second prediction result; wherein the second prediction result is used for indicating whether jumping occurs or not after the current instruction is executed; and in response to the fact that the second prediction result is different from the first prediction result, the second prediction result is adopted to correct the first prediction result, so that the accuracy of the first prediction result is improved, and based on the accurate first prediction result, the performance loss caused by prediction errors can be reduced.

A branch predictor [110] of a processor [100] includes one or more prediction structures [112, 114, 116] that identify predicted branches, including predicted branch addresses and predicted branch directions. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information, and filters the selected structures so that the filtered structures are not used for branch prediction. Thus, the branch predictor reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.

Methods and circuitry for efficient management of local branch history registers are described. An example processor includes a pipeline comprising a plurality of stages and a bit-vector associated with each of in-flight branches associated with the pipeline. The processor includes a recovery counter for tracking a number of bits needing recovery before a local branch history register is valid for participation in branch prediction. The processor includes branch predictor circuitry configured to, in response to an update of a local branch history register by a branch, set a bit in a corresponding bit-vector indicative of the update of the local branch history register. The branch predictor circuitry is configured to, upon a flush, determine a value indicative of an extent of recovery required for each local branch history register affected by the flush, and set a corresponding recovery counter to the value indicative of the extent of recovery required.

Circuits and methods for conditional fence instructions are described. In some examples, a hardware processor (e.g., a core) includes a branch predictor to predict one of an taken path and an untaken path of a conditional branch instruction; decoder circuitry to decode an instruction to a decoded instruction, the instruction including a field indicating a condition set by executing another instruction and an opcode indicating that the execution circuitry will implement an execution fence in response to the condition being satisfied to delay execution of the instruction prior to execution of a previous instruction in a program order, the opcode indicating that the execution circuitry will implement the execution fence in response to the condition being satisfied. And before the instruction is executed, delaying execution of an instruction following the instruction according to the program order; and the execution circuit is used for executing the decoded instruction according to the operation code.

A quantum computer, comprising: at least one CPU and at least one QPU. The CPU includes: a branch predictor configured to form one or more result predictions or algorithm branches of a result of a measurement being performed or to be performed by the QPU; a compiler configured to generate respective sets of quantum gates corresponding to each of the one or more result predictions by performing respective one or more compilation tasks, each of the compilation tasks comprising compiling a portion of a hybrid quantum algorithm; and a quantum gate selector configured to receiving the result of the measurement and respond by passing to the QPU a set of quantum gates from the sets of quantum gates that corresponds to the result of the measurement.