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Suppression of control transfer instructions on incorrect speculative execution paths

A technology of control transfer and execution path, which is applied in the direction of program control design, concurrent instruction execution, machine execution device, etc., and can solve problems such as incorrect update of IFU, flushing of forged instructions, etc.

Active Publication Date: 2014-03-05
ORACLE INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This younger CTI can also lead to spurious instruction flushes and / or incorrect updates to the IFU

Method used

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  • Suppression of control transfer instructions on incorrect speculative execution paths
  • Suppression of control transfer instructions on incorrect speculative execution paths
  • Suppression of control transfer instructions on incorrect speculative execution paths

Examples

Experimental program
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Embodiment Construction

[0016] This specification includes reference to "one embodiment" or "an embodiment." The appearances of the phrase "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Particular features, structures or characteristics may be combined in any suitable manner consistent with the disclosure.

[0017] the term. The following paragraphs provide definitions and / or context for terms that appear in this disclosure, including the appended claims.

[0018] "Include". The term is open ended. As used in the appended claims, the term does not exclude additional structure or steps. Consider a claim that reads "means comprising one or more processor units...". Such claims do not exclude that the device contains additional components (eg network interface unit, graphics circuitry, etc.).

[0019] "is configured as". Various units, circuits or other components may be described or claimed to be "configured to" perform a task or tasks. In this c...

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PUM

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Abstract

Techniques are disclosed relating to a processor that is configured to execute control transfer instructions (CTIs). In some embodiments, the processor includes a mechanism that suppresses results of mispredicted younger CTIs on a speculative execution path. This mechanism permits the branch predictor to maintain its fidelity, and eliminates spurious flushes of the pipeline. In one embodiment, a misprediction bit is be used to indicate that a misprediction has occurred, and younger CTIs than the CTI that was mispredicted are suppressed. In some embodiments, the processor may be configured to execute instruction streams from multiple threads. Each thread may include a misprediction indication. CTIs in each thread may execute in program order with respect to other CTIs of the thread, while instructions other than CTIs may execute out of program order.

Description

technical field [0001] This disclosure relates to processors, and more particularly, to preventing branch predictor errors in out-of-order processors. Background technique [0002] Contemporary superscalar microprocessors achieve high performance by executing multiple instructions in parallel, out of program order. Control transfer instructions (CTIs) such as branches, calls, and returns, which are highly prevalent in a program, can cause a pipelined microprocessor to stall because the instructions to be executed after the control transfer instruction are not known until the control transfer instruction is executed. These stalls can result in a significant loss of performance. [0003] Contemporary microprocessors use branch prediction techniques to speculatively fetch and execute instructions beyond the CTI. Branch prediction involves predicting the direction and target of a CTI. If a CTI is mispredicted due to incorrect direction prediction or target prediction, all ins...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3842G06F9/3806G06F9/3851G06F9/3861G06F9/3844
Inventor C·H·奥尔森M·K·沙
Owner ORACLE INT CORP
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