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Microprocessor and execution method thereof

A technology of microprocessors and execution units, applied in the field of non-sequential microprocessors, which can solve problems such as adverse effects of branch instructions

Active Publication Date: 2010-10-20
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Although in the field of microprocessor design, the use of branch predictors is beneficial to performance, in hyperpipelined microprocessors, the adverse impact of branch instructions on performance is well known

Method used

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  • Microprocessor and execution method thereof
  • Microprocessor and execution method thereof
  • Microprocessor and execution method thereof

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Embodiment Construction

[0028] figure 1 is a block diagram of the microprocessor 100 of the present invention. The microprocessor 100 includes a pipeline composed of multiple stages or functional units. The pipeline includes an instruction fetch unit 122, an instruction cache 102, an instruction formatter ( instruction formatter) 124, formatted instruction queue (formatted instruction queue) 126, instruction translator (instruction translator) 104, translated instruction queue (translated instruction queue) 128, register alias table (register alias table) 106, reservation station (reservation station) ) 108, an execution unit 112, and a retirement unit 114. The microprocessor 100 also includes a branch predictor 118 coupled to the fetch unit 122 . The microprocessor 100 also includes a reorder buffer 116 coupled to the register alias table 106 , the reservation station 108 , the execution unit 112 and the retirement unit 114 .

[0029] The execution unit 112 includes a load unit 166 , an execution...

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Abstract

A microprocessor and an execution method thereof are used for pipelined out-of-order execution in-order retire. The microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.

Description

technical field [0001] The invention relates to the field of non-sequentially executed microprocessors, in particular to the execution of branch instructions thereof. Background technique [0002] Superscalar microprocessors have multiple execution units for executing the instruction set of the microprocessor. A superscalar microprocessor improves processing performance through multiple execution units, so a superscalar microprocessor can execute multiple instructions simultaneously in each clock cycle. The key to the potential performance improvement of a superscalar microprocessor is that instructions must be continuously supplied to the execution units for execution; otherwise, the performance of a superscalar microprocessor will not be better than that of a scalar microprocessor, and A superscalar microprocessor will cost more hardware than a scalar microprocessor. For example, the execution unit is used to load and store instruction operands, calculate addresses, exec...

Claims

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Application Information

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IPC IPC(8): G06F9/38
Inventor 杰拉德·M·卡尔罗德尼·E·虎克布莱恩·W·伯格
Owner VIA TECH INC
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