Instruction acquisition control method based on simultaneous multithreading

Abstract

The invention provides an instruction acquisition control method based on simultaneous multithreading, which includes the steps: in each clock cycle of a processor, reading a PC (personable computer) value of instructions by an instruction acquisition component according to a program counter, selecting two threads with high priority as instruction acquisition threads firstly, and then computing the actual instruction number required by each instruction acquisition thread so as to read the instructions; according to an IPC (inter-process communication) value and the Cache failure rate, enabling a dual-priority resource allocation mechanism to compute system resources required by the threads in an instruction acquisition stage and complete dynamic allocation of the resources; matching a TBHBP (thread branch history branch predictor) with the instruction acquisition operations of the instruction acquisition component, acquiring a pattern type match position Sc by connecting global historical information with local historical information read by a branch instruction Bi to utilize as an index of a secondary PHT (pattern history table), and inputting computed results to a BRT (branch result table); and when the branch instruction Bi is executed again, judging whether CONF fields are larger than or equal to 2 or not by the aid of a selector, directly outputting the recorded branch results if the CONF fields are larger than or equal to 2, and finally placing the acquired instruction into an instruction Cache, so that all operations of instruction acquisition control are completed.

Description

technical field [0001] The invention relates to an instruction fetch control method. Specifically, it is an instruction acquisition processing method based on simultaneous multithreading. Background technique [0002] With the development of computer architecture, in order to meet people's urgent needs for high-performance processors, multi-thread processors emerged as the times require, and have become the mainstream microprocessor structure. Various researches on simultaneous multi-threaded processors have become very active, and at the same time, the instruction fetch control method of multi-threaded processors has attracted much attention as a research hotspot in the field of high-performance processors. [0003] In recent years, many experts, scholars and scientific research institutions at home and abroad have carried out active research and exploration on it. In terms of fetching strategies, Professor Tullsen of the University of Washington in the United States prop...

AI Technical Summary

Problems solved by technology

The ICOUNT policy grants higher priority to fast-running threads, effectively preventing a certain thread from blocking the instruction queue, maximizing the parallelism of instructions in the instruction queue, and it is also the best instruction fetch performance in traditional processors, but due to its The shortcomings of unbalanced instruction fetch bandwidth utilization and high instruction queue conflict rate greatly limit the full performance of simultaneous multi-threaded processors

In terms of branch predictors, the Gshare predictor proposed by McFarling, through the "XOR" processing of the high address and the historical low, makes the branch instructions that appear to be interfered be mapped to different prediction entries, effectively alleviating the inter-thread instructions. Mutual interference occurs, but it may introduce new branch alias interference into branch instructions that do not originally conflict, so branch prediction performance needs to be improved

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