157 results about "Program counter" patented technology

A pipelined decoding microarchitecture design method for RISC-V vector instructions includes the following steps: S1, extracting an instruction packet according to a PC, performing preprocessing, and writing a preprocessing result, each instruction field and preprocessed instruction information into a cache; S2, reading the cache, obtaining pre-decoding result data and recognizing each configuration instruction; S3, transmitting the pre-decoding result data to an instruction buffer, and acquiring field information, a split quantity and predicted vtype information; and splitting each instruction into multiple microoperations, and constructing a queue to store each microoperation; and S4, transmitting first, by means of the queue, each configuration instruction, performing decoding and execution, acquiring vtype information generated after execution, and when the vtype information generated after execution is identical with the predicted vtype information, controlling the number of microoperations input to multiple decoders, and transmitting a decoding result to an instruction slot.

The invention belongs to the technical field of simulation, and particularly relates to a simulation result display method and device, a storage medium and equipment, and the display method comprises the steps: obtaining a global program counting address and instruction information according to a firmware logic file, and constructing a reference address mapping table based on the global program counting address and the instruction information; wherein the firmware logic file is a file for storing firmware execution logic related information; obtaining a firmware program counting address according to the firmware signal file; wherein the global program counting address comprises the firmware program counting address, and the firmware signal file is a file for storing response signal related information generated when the firmware executes the instruction information; in the execution process of playing back the instruction information, displaying the firmware program counting address based on the firmware program counting address and the reference address mapping table; according to the method, the debugging efficiency between the software and the firmware is improved.

An analysis function providing method executed by an analysis function providing device includes first analyzing a virtual machine of a script engine, and acquiring a hook point that is a part where an analysis code is inserted by applying a hook, and a virtual program counter that is a variable indicating an instruction of the virtual machine to be executed next, second analyzing an instruction set architecture that is a system of instructions of the virtual machine and acquiring a branch virtual machine instruction that is a virtual machine instruction that causes branch, and providing an analysis function by applying a hook, to the hook point of the script engine, the hook including processing of, when an exception has occurred, changing a destination pointed by the virtual program counter to a head of a basic block immediately after a basic block in which the exception has occurred.

There is provided an apparatus, a method, and a computer program. The apparatus is provided with instruction decoding circuitry to decode instructions and processing circuitry to perform a processing operation in response to a decoded instruction. In response to an authentication code generating instruction, the processing circuitry is configured to generate an authentication code associated with an 10 authentication target value. For at least one type of the authentication code generating instruction, the processing circuitry is configured to generate an authentication code, when operating in a first code generation mode, by applying a code generating function to: a key; the authentication target value; a first modifier dependent on a stack pointer, and / or a second modifier dependent on a program counter address; and a further 15 modifier dependent on a further value obtained from an architecturally visible register different from the stack pointer register and the program counter register.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

The invention relates to the technical field of code caching, and provides a dynamic binary translation caching method and system based on hotspot discovery, and the dynamic binary translation caching method comprises the following steps: S1, taking a virtual address of a client as a key value of a Hash conflict ring structure; s2, in a certain detection, if it is detected that the same translation block is hit for the second time according to the virtual address of the client and the program counter, and the number of hit translation blocks reaches a hit threshold value, triggering a hotspot transfer thread to update a hotspot counter corresponding to translation block information, pointing a head pointer of the hash bucket to the translation block information with the highest hotspot counter value; and S3, two groups of alternately used continuous memory spaces are adopted, translation codes of the old memory space are recovered through copy-on-write, new translation codes are written into the new memory space, and the translation codes of the old memory space are asynchronously migrated to the new memory space.

The invention discloses a dynamic instruction fetch and instruction coverage method and a processor based on a double-track assembly line, and the dynamic instruction fetch method comprises the steps: when the current instruction fetch is a branch instruction, two instructions are fetched from a current instruction PC value plus 4 and a branch target address at the same time in a next clock period; and when the instruction is a non-branch instruction, taking one instruction in the next clock period. According to the instruction coverage method, primary and secondary parallel assembly lines are set, the primary assembly line processes an instruction with a previous instruction PC value plus 4, and the secondary assembly line processes a branch target address instruction; when branch jumping and target address matching are judged in the execution stage, instructions in all stages of the secondary assembly line cover instructions in corresponding stages of the main assembly line. The method can solve the problems of high delay, large misprediction penalty and low power consumption efficiency of branch prediction, and improves the performance of a processor.

An analysis function providing method executed by an analysis function providing device includes first analyzing a virtual machine of a script engine and acquiring a virtual program counter that is a variable indicating an instruction of the virtual machine to be executed next and a conditional branch flag that is an area for holding a flag as to whether or not branch is made at a time of conditional branch in an execution state, and providing an analysis function to the script engine by applying a hook including processing of detecting an instruction sequence a number of times of repeated execution of which is greater than or equal to a threshold and stopping execution of the instruction sequence by rewriting a condition related to a conditional branch at an end of the instruction sequence on a basis of the virtual program counter and the conditional branch flag.

The invention provides a visual gateway debugging system and a visual gateway debugging method based on a swan mongolian operating system, and relates to the technical field of IoT (Internet of Things) debugging. The system comprises the following steps: constructing a domain name forest structure based on DNS, TLS and HTTP traffic, and identifying an equipment identity; a debugging activation instruction is generated, and cross-device command transmission with the DSoftBus is carried out through the WebSocket and the DSoftBus; collecting program counters, stacks and variable states with microsecond-level precision; constructing a state tetrad atlas and executing compression processing; migrating a breakpoint context among multiple devices and reconstructing an execution environment; and graphically presenting a state graph, a variable track and a call stack, and supporting linkage of path playback and debugging control. According to the method, a full-process closed loop from equipment identification to debugging control and from state modeling to path playback is realized, the debugging efficiency, the automation level and the system visualization capability are improved, and the method is suitable for debugging and abnormity diagnosis scenes of the distributed intelligent terminal.

In response to an authentication code generating class of instruction, processing circuitry generates an authentication code associated with an authentication target value by applying a code generating function to the authentication target value, a key, a first modifier value and a second modifier value. For an authentication code setting instruction, the generated authentication code is written to a destination register. For an authentication code checking instruction, the processing circuitry checks whether the authentication code generated based on the authentication target value in response to the authentication code checking instruction corresponds to a reference authentication code obtained from a source register, and triggers an error response when they do not correspond. The first modifier value comprises a stack-pointer- dependent value. For at least one of the authentication code setting / checking instructions, the second modifier value comprises a program-counter-dependent value.

The embodiment of the invention provides a PC value log generation method, and relates to the technical field of storage. The method comprises the following steps: acquiring a program counter value output by a central processing unit core; compressing the program counter values to generate program counter value log data packets with specified formats corresponding to the program counter values; combining the generated one or more program counter value log data packets to obtain a combined data packet; and transmitting the combined data packet to a memory. The program counter value sequence collected by the program counter value method is compressed to generate the program counter value log data packet with the specified format, and the total size of the program counter value log data packet is smaller than the size of the program counter value sequence, so that the bandwidth for transmitting the program counter value is reduced.

A graph processing core includes a plurality of processing pipelines and an interrupt controller unit. Each processing pipeline executes one or more threads and includes, for each thread, a register indicating a currently executing program counter vector and another register indicating an interrupt or exception handler vector. The interrupt controller unit may receive interrupt or exception notifications from the processing pipelines, determine a handler vector based on the notification and a set of registers of the interrupt controller unit, and transmit the handler vector to the processing pipeline that issued the interrupt or exception notification. Further, the issuing pipeline may receive the handler vector from the interrupt controller unit, write a value in the first register into the second register, write the handler vector into the first register, and invoke an interrupt or exception hander based on the value written into the first register.

The invention provides a thread scheduling method and device, a compiling method and device, electronic equipment and a storage medium. The method for scheduling the threads comprises the following steps of: mapping a first register into a register for recording a return program counter through a first software instruction for a thread bundle to be subjected to thread bundle differentiation and synchronization, wherein the return program counter is used for recording a next instruction address to be executed in each thread of the thread bundle; the second register is mapped into a register for recording thread synchronization information for the thread bundle through a second software instruction, the thread synchronization information comprises a thread mask and a target program counter, and the thread mask is used for recording whether a thread currently participating in thread bundle differentiation and synchronization in the thread bundle is executed or not; the target program counter is used for recording a target instruction address to be skipped after synchronization is completed; and executing thread beam differentiation and synchronization by using the returned program counter obtained after mapping and thread synchronization information. According to the invention, the use of the register and the thread beam differentiation and synchronization are more flexible.

A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.

The invention relates to a performance counting device and a chip, and the performance counting device comprises a performance counting module which is used for receiving at least one instruction memory address from a program counter associated with the performance counting module, and according to the at least one instruction memory address and a pre-configured instruction memory address interval, counting the at least one instruction memory address; obtaining a statistical value of a performance signal of at least one instruction memory address in the instruction memory address interval; the storage module is used for storing the statistical value of the performance signal of the at least one instruction memory address of the performance statistical module; the write-in control module is used for writing the statistical value, obtained by the performance statistical module, of the performance signal of the at least one instruction memory address into the storage module; and the configuration module is used for configuring an instruction memory address interval of the performance statistics module. According to the method and the device, the configuration flexibility of performance statistics can be improved, performance statistics of a plurality of specified program segments can be realized at the same time on the basis, and parallel processing of the performance statistics and accurate positioning of the program segments are further realized.

Methods and systems relating to improved coprocessing architectures with static instruction caching are disclosed herein. A disclosed coprocessor architecture includes a processor, a coprocessor defined by an instruction set, a cache of static instruction blocks, and an instruction cache. The instruction set includes at least one static instruction. The instruction cache is configured to identify instructions in a series of instructions, provided by the processor for execution by the coprocessor, as either static instructions or dynamic instructions. The instruction cache is configured to, in response to identifying two or more sequential instructions in the series of instructions as static instructions, cache the two or more sequential instructions in the cache of static instruction blocks as an instruction block and store a program counter value of a program counter. The instruction cache is configured to provide the instruction block to the coprocessor from the cache of static instruction blocks when the program counter returns to the program counter value.

A processor (101) with an instruction set comprising a looping instruction and corresponding method are provided. The looping instruction is defined by a corresponding opcode and comprises a register operand for holding a sequence of subinstructions. The looping instruction causes the processor (101) to: repeatedly execute the looping instruction without incrementing a program counter, each execution of the looping instruction comprising: executing one of the subinstructions in the register operand; and modifying the register operand to contain a different set of subinstructions.

A processor circuit that includes a plurality of register circuits and an event handler circuit is disclosed. The event handler circuit may detect a processing event that causes the processor circuit to halt execution of a current instruction and transfer control to a kernel. In response to a detection of the processing event, the event handler circuit may store a program counter value corresponding to the current instruction, information indicative of a cause of the processing event, and a size of the current instruction in corresponding register circuits of the plurality of register circuits.

The invention discloses a thread scheduling method, device and equipment based on an RISC-V framework. The method is applied to the electronic equipment based on the RISC-V architecture, an operating system kernel of the electronic equipment runs in a supervision mode of the RISC-V architecture, a user program of the electronic equipment runs in a user mode of the RISC-V architecture, and the method comprises the steps that the user program is analyzed, and a user mode stack, a kernel mode stack and a thread control block are created according to an analysis result; writing the entry address of the user program in the analysis result into an abnormal program counter in a supervision mode; and executing the supervision mode exception return instruction, switching the processor of the electronic equipment from the supervision mode to the user mode, jumping to the entry address of the user program, and starting to execute the user mode thread. The thread scheduling method based on the RISC-V architecture provided by the invention can be high in safety.

The invention provides a floating point unit exception handling method and device of an industrial safety operating system and a medium. The method comprises the following steps: hooking a floating point exception handling function at an undefined instruction exception entry, and enabling the exception of a floating point unit to enter a unified handling flow; reading an abnormal comprehensive register of the processor to identify the floating point operation exception type, and reading a program counter register to obtain a trigger instruction address; performing standardized calculation on the operation under abnormal conditions according to a binary floating point arithmetic standard, generating result data corresponding to the operation, and forming abnormal mark information; writing the result data back to the destination register, and calculating a next instruction address according to the instruction set rule; and outputting the trigger instruction address, the exception type, the source operand and the result data as exception information through an interface from the kernel to a user side. According to the method, instant processing of the abnormal trigger point, continuous execution of the instruction, real-time output of the abnormal context and reduction of positioning and recovery time delay can be realized.

Embodiments of the present description provide an instruction fetching method, a processor, a system-on-chip, and a computing device. The instruction fetching method is applied to an instruction fetch unit of a processor, and the processor further comprises a cache unit, a tightly-coupled memory unit, and a program counter. The instruction fetching method comprises: receiving branch prediction information for a current jump instruction; on the basis of the branch prediction information, determining, from the cache unit and the tightly-coupled memory unit, a current storage unit where the current jump instruction is located; and on the basis of an offset of a current program counter value recorded by the program counter, fetching the current jump instruction from the current storage unit. The timing pressure is reduced, the clock rate of the processor is increased, and the additional dynamic power consumption caused by fetching jump instructions from two branches simultaneously are effectively avoided, thereby improving the performance of the processor when processing non-sequential instructions and the product battery life, and implementing more efficient and energy-saving instruction fetching without sacrificing the processing speed; the present invention is applicable to application scenarios having high requirements for real-time performance and product battery life.

Provided is a processor enabling assembly code of a direct-addressing conditional-jump subroutine to be reduced. The processor includes a logic circuit executing a conditional-jump instruction of assembly code, and logically configured to: store, into an index register, an index register number that is an index to a jump-destination effective address; store jump-destination effective addresses differing from one another, or address offsets to jump-destination effective addresses differing from one another, into plural reference registers, respectively; fetch and decode a conditional jump instruction that is one instruction that quotes the index register; and then execute (S1) acquiring a jump-destination effective address or an address offset from the reference register corresponding to the index register number of the content of the index register and (S2) setting the acquired jump-destination effective address, or a jump-destination effective address calculated from the address offset, to a register serving as the program counter.

This application discloses an instruction processing method, apparatus, device, and storage medium, relating to the field of processor technology. The method includes: generating a first immediate value through a program counter, and using the first immediate value as a first program counter value; reading a first instruction from a memory unit according to the first program counter value through a processor instruction fetch unit; passing the first instruction to a pre-decoding unit so that the pre-decoding unit decodes and judges the first instruction; if the first instruction is a first preset instruction, then fetching, decoding, and executing the instruction through the processor instruction fetch unit and / or branch prediction unit. This application can improve the processor's clock frequency.

The application provides a runtime suspension detection and positioning method and device for parallel programs, and applies to the technical field of large-scale computing. The method comprises the following steps: constructing a program counter value queue of each target execution unit at each sampling time; recording a stagnation program counter value of a target execution unit in a stagnation state; clustering the stagnation program counter value of the target execution unit to determine a suspended target execution unit; based on a machine instruction corresponding to the stagnation program counter value of the suspended target execution unit, obtaining source file and line number information corresponding to the stagnation program counter value through debugging information; and when the machine code corresponding to the stagnation program counter value of the suspended target execution unit is a call instruction, obtaining function call information. In this way, non-intrusive and low-load monitoring of parallel programs is realized, normal synchronization waiting and abnormal suspension processes are effectively distinguished, and problems are positioned to source code lines.

Disclosed embodiments provide techniques for branch prediction. A processor core is accessed. The processor core is coupled to memory and includes branch prediction circuitry. The branch prediction circuitry includes a branch target buffer (BTB) and an indirect branch target buffer (BTBI). A hashed program counter within the processor core is read. The BTB and BTBI are searched. The searching the BTB is accomplished with the hashed program counter and the searching the BTBI is accomplished with the hashed program counter and branch history information. A predicted branch target address within the BTBI or the BTB is matched. The matching within the BTBI is based on an indirect branch instruction, and the matching within the BTB is based on other branch instruction types. The predicted branch target address that was matched is predicted taken. The processor core is directed to fetch a next instruction from the predicted branch target address.

To provide an electronic control device that collects information for estimating a state of a moving body and transmits the information to an analysis device with a simple configuration, and a moving body state estimation system that estimates the state of the moving body on the basis of the information transmitted from the electronic control device.SOLUTION: The electronic control device 10 is configured to be able to transmit sampling data obtained by sampling the address values indicated by the program counters 18 and 20 to the analyzing device 40 as information for estimating the state of the moving object. The analysis device is configured to aggregate an appearance frequency of an address value for each address section with respect to the sampling data, generate operating point data having a plurality of address sections as elements, and estimate a state of the moving object based on the generated operating point data.SELECTED DRAWING: Figure 1

Multi-agent instruction execution engines for neural inference processing are provided. In various embodiments, a neural core is provided. The neural core includes an instruction memory. The instruction memory comprises a plurality of instruction streams, each instruction stream associated with one of a plurality of agents. The instruction memory further comprises a plurality of shared functional units. The neural core is adapted to concurrently execute the plurality of instruction streams on the plurality of associated agents. The execution includes maintaining a separate program counter for each of the plurality of agents, determining a plurality of operations from the instructions of each instruction stream, and directing the operations to the shared functional units. The instructions of each instruction stream are statically scheduled prior to runtime to ensure their execution is conflict free.

The invention discloses an instruction fetching method and device based on multi-level branch prediction, equipment and a storage medium. The method comprises the steps of obtaining a value of a program counter of an initial instruction; inputting the value of the program counter into a preset pipeline level for processing, and obtaining a branch prediction result in combination with a branch prediction mechanism; and verifying the consistency of the branch prediction results step by step to obtain a target instruction. According to the method, the multi-stage assembly line and branch instruction prediction under different access frequencies are combined, so that the instruction reading efficiency is improved, and the overall performance of the processor assembly line is effectively improved. Through step-by-step confirmation of the branch prediction result, the accuracy and the high efficiency of the instruction stream are ensured, so that the processor can execute the program instruction more smoothly.

An architecture of a computer processor providing a program counter (PC) for fetching instructions from a memory system comprises a program counter indexed address translation table (PCAT) having rows accessed with a program counter (PC) value, an entry in a row identifying a virtual memory address and a corresponding physical memory address. Translation between virtual memory addresses and the physical memory addresses is mediated by the PCAT holding the virtual and corresponding physical addresses. In some embodiments, this table can be accessed early in a fetch cycle and avoid likely translation lookaside buffer (TLB) misses.

This invention discloses a method, apparatus, terminal, and storage medium for handling write-time memory faults, belonging to the field of memory. The method includes: when executing a memory unrepairable fault handling method, determining whether it is a memory synchronization fault; if it is a memory synchronization fault, obtaining the context register information of the interrupted process and obtaining the value of the program counter; determining the address of the interrupted instruction; based on the interrupted instruction address, reading the binary code corresponding to the interrupted instruction and parsing the opcode in the binary code; determining whether the currently interrupted process is in a write operation phase based on the opcode parsing result; if it is in a write operation phase, determining that a write-time memory fault has occurred; when using anonymous mapping, allocating a new physical page frame and replacing the original faulty physical page frame with the new physical page frame; identifying all page table entries involved in the original faulty physical page frame; and replacing the original information in all page table entries with the new physical page frame information.