29 results about "Program counter" patented technology

Embodiments of the present description provide an instruction fetching method, a processor, a system-on-chip, and a computing device. The instruction fetching method is applied to an instruction fetch unit of a processor, and the processor further comprises a cache unit, a tightly-coupled memory unit, and a program counter. The instruction fetching method comprises: receiving branch prediction information for a current jump instruction; on the basis of the branch prediction information, determining, from the cache unit and the tightly-coupled memory unit, a current storage unit where the current jump instruction is located; and on the basis of an offset of a current program counter value recorded by the program counter, fetching the current jump instruction from the current storage unit. The timing pressure is reduced, the clock rate of the processor is increased, and the additional dynamic power consumption caused by fetching jump instructions from two branches simultaneously are effectively avoided, thereby improving the performance of the processor when processing non-sequential instructions and the product battery life, and implementing more efficient and energy-saving instruction fetching without sacrificing the processing speed; the present invention is applicable to application scenarios having high requirements for real-time performance and product battery life.

This application discloses an instruction processing method, apparatus, device, and storage medium, relating to the field of processor technology. The method includes: generating a first immediate value through a program counter, and using the first immediate value as a first program counter value; reading a first instruction from a memory unit according to the first program counter value through a processor instruction fetch unit; passing the first instruction to a pre-decoding unit so that the pre-decoding unit decodes and judges the first instruction; if the first instruction is a first preset instruction, then fetching, decoding, and executing the instruction through the processor instruction fetch unit and / or branch prediction unit. This application can improve the processor's clock frequency.

The application provides a runtime suspension detection and positioning method and device for parallel programs, and applies to the technical field of large-scale computing. The method comprises the following steps: constructing a program counter value queue of each target execution unit at each sampling time; recording a stagnation program counter value of a target execution unit in a stagnation state; clustering the stagnation program counter value of the target execution unit to determine a suspended target execution unit; based on a machine instruction corresponding to the stagnation program counter value of the suspended target execution unit, obtaining source file and line number information corresponding to the stagnation program counter value through debugging information; and when the machine code corresponding to the stagnation program counter value of the suspended target execution unit is a call instruction, obtaining function call information. In this way, non-intrusive and low-load monitoring of parallel programs is realized, normal synchronization waiting and abnormal suspension processes are effectively distinguished, and problems are positioned to source code lines.

This application proposes a method and chip device for monitoring processor program execution information, relating to the field of processor technology. It includes: real-time acquisition of the processor's raw program counter value, raw return address value, and hardware timestamp; compression processing of the raw program counter value and raw return address value to obtain compressed program counter value and compressed return address value, wherein the compression processing discards low-order alignment bits and high-order address bits; address range judgment of the raw program counter value and raw return address value to generate a program counter position flag and a return address position flag; concatenating the hardware timestamp, compressed program counter value, compressed return address value, program counter position flag, and return address position flag in a preset order into a fixed-width monitoring data packet; and reporting the monitoring data packet in response to the fulfillment of a preset trigger condition. This scheme can achieve effective monitoring of processor program execution information with low hardware overhead.

This application provides a method and system for preventing task starvation. The method includes: acquiring a set of tasks in kernel mode that hold critical section resources awaiting high-priority tasks; performing execution flow truncation on the tasks in the task set, including: dynamically counting based on the length of the critical section release instruction, determining the address of the core execution instruction for critical section release corresponding to the task, constructing the minimum kernel stack of the task, and modifying the program counter pointer and stack pointer of the task to interrupt the original execution flow of the task; and performing targeted release of critical section resources of the task after execution flow truncation based on the dynamic counting of the length of the critical section release instruction. By separating the task execution flow from the resource release operation, this application enables low-priority tasks to release critical section resources without being dependent on the advancement of their own complete business logic, thus achieving batch release of resources for multiple low-priority tasks holding different critical section resources.

This invention discloses a method for generating formal software models based on control flow graphs and large language models. The method includes the following steps: parsing the source code to be analyzed using an abstract syntax tree and constructing a control flow graph; assigning a unique node identifier to each node in the control flow graph, corresponding to the basic blocks of the program; declaring all variables in the source program, introducing a program counter variable, constructing a state machine structure model, and generating intermediate representation code in a state machine style based on the control flow graph; using the intermediate representation code and the control flow graph, guiding the large language model to generate a formal model through constraint hint templates; performing syntax constraint verification and test case-driven closed-loop verification on the formal model, iteratively refining the formal model. This invention solves the problems of existing formal model construction in software formal verification processes being highly dependent on manual labor, having low automation, and being difficult to accurately characterize complex control structures.

In an embodiment, a method includes sharing, via a publication-subscription (pub-sub) bus, an unaddressed message between a plurality of agents. The unaddressed message includes a program counter pointing to a first instruction of a program written in a programming language. The method also includes determining, by each respective agent of the plurality of agents, whether the respective agent can perform the instruction and, in response to a first agent of the plurality of agents determining that the first agent can perform the instruction, consuming, by the first agent, the unaddressed message. The method further includes removing, by the first agent, the unaddressed message from the bus, performing, by the first agent, the instruction, adding, by the first agent, one to the program counter, and posting, by the first agent, a response to the pub-sub bus for further processing of the program.

Disclosed techniques relate to supplemental (e.g., PC-based Bayesian) learning for a pattern-based prefetcher. In some embodiments, prefetch circuitry is configured to store access map data based on address information corresponding to memory accesses and generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache. In some embodiments, supplemental access tracking circuitry is configured to store initial access tracking information for offsets corresponding to a first access map evicted from the prefetch circuitry, update the access tracking information based on one or more additional access maps evicted from the prefetch circuitry that match the stored program counter information, and generate, based on the updated access tracking information, a starting access map for allocation in the prefetch circuitry.

A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

This application provides a branch execution method under a single-instruction multithreaded architecture and a general-purpose graphics processor. The method is applied to a general-purpose graphics processor (GPGPU), which includes a processing unit and a circuit unit. The method includes: the processing unit identifies a thread branch and acquires branch information, including a convergence point thread mask, a first branch count, a first branch thread mask, a second branch count, and a second branch thread mask; the processing unit inputs the branch information to the circuit unit, causing the circuit unit to complete a first setting, which includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to a first stack layer, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask; the processing unit executes a first target branch program; after the first target branch program is executed, the processing unit triggers the circuit unit to complete a second setting, which includes setting the program counter to the second branch count and the thread mask to the second branch thread mask based on the data saved in the first stack layer; the processing unit executes a second target branch program. By utilizing this branch execution method under the single instruction multithreaded architecture and the general-purpose graphics processor, good processing performance can still be maintained under the SIMT architecture with the low hardware complexity of GPGPU.

An execution in parallel method for a graphic processing unit includes providing a plurality of threads, enabling a first program counter, and the first program counter running a first program on the plurality of threads. When receiving a fork instruction, enable a second program counter, and if a first active mask of the fork instruction is set as a pass mask, and a second active mask is set as a fail mask, the first program counter activates a first set of threads corresponding to the pass mask. When the first set of threads is blocked, the second program counter activates a second set of threads corresponding to the fail mask. When the second set of threads is blocked, the first program counter activates the first set of threads. When receiving a join instruction, disable the second program counter, and the first program counter activates the plurality of threads.

An execution in parallel method for a graphic processing unit includes providing a plurality of threads (400), enabling a first program counter, and the first program counter running a first program on the plurality of threads (400). When receiving a fork instruction, enable a second program counter, and if a first active mask of the fork instruction is set as a pass mask, and a second active mask is set as a fail mask, the first program counter activates a first set of threads (410) corresponding to the pass mask. When the first set of threads is blocked, the second program counter activates a second set of threads (420) corresponding to the fail mask. When the second set of threads is blocked, the first program counter activates the first set of threads. When receiving a join instruction, disable the second program counter, and the first program counter activates the plurality of threads (450).

This application proposes an instruction access method, apparatus, electronic device, and storage medium, relating to the field of processor technology. The instruction access method includes: receiving a program counter (PC) to be fetched sent by a branch prediction unit (BPU); determining a first target PC to be fetched and performing a prefetch filtering query on the first target PC to obtain a first query result; caching the first query result in a prefetch filtering query result queue; determining a second target PC to be fetched and obtaining a second query result corresponding to the second target PC from the prefetch filtering query result queue; and retrieving the target instruction corresponding to the second target PC from the instruction cache based on the second query result, thereby improving the access efficiency of the instruction cache.

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.

The application discloses a cache data prefetching method and device, equipment and storage medium, and relates to the technical field of computers, which comprises the following steps: when the accumulation table receives a data access request initiated by a CPU, if the accumulation table has a target table item that needs to be removed, it is judged whether the number of target effective bits in the candidate bit vector corresponding to the target table item is greater than a preset threshold; if yes, it is judged whether the mode table has a target bit vector corresponding to the candidate bit vector; if not, it is judged whether the mode table has a target idle table item; if not, it is judged whether the program counter corresponding to the candidate bit vector and the training counter both satisfy a first target saturation condition; if not, it is judged whether the program counter corresponding to the candidate bit vector and the access offset corresponding to the access missing counter both satisfy a second target saturation condition; if yes, the candidate bit vector is stored in the mode table, and a cache data prefetching operation is performed based on the mode table. The accuracy and efficiency of data prefetching are improved.

Various embodiments of the present disclosure relate to branch prediction within computing systems. In one example embodiment, a technique for performing branch prediction is provided. The technique first includes performing a first comparison between a first portion of a program counter value and a first portion of a cached address (201). Next, the technique includes performing a second comparison between a second portion of the program counter value and a second portion of the cached address (203). Finally, the technique includes determining to replace the program counter value with a target address associated with the cached address based at least on the first comparison determining that the first comparison was a match and the second comparison determining that the second comparison was a match (206).

The embodiment of the application discloses a dynamic sampling method, system and device of a program counter in a graphics processor, relates to the technical field of the graphics processor, and is convenient for improving sampling coverage and accuracy and supporting performance analysis in the time dimension. The method comprises the following steps: monitoring the execution state of an active thread group, the active thread group being a processing unit used for parallel execution of multiple threads when the graphics processor executes kernel code; when it is monitored that the execution state of the active thread group is in a preset sampling condition, triggering a preset sampler to sample the active thread group, so as to obtain sampling data, the sampling data comprising basic information used for indicating the execution position and state of the active thread group and timestamp information of sampling instruction execution of the active thread group. The application is suitable for the scene of dynamic sampling of a program counter in a graphics processor.

Trap subparts of computer readable instructions and related systems, methods, and apparatus are disclosed. A processing circuit includes a processing core including a program counter that cycles through addresses and a data storage device including computer readable instructions stored thereon. The computer readable subparts correspond to subroutines. Locations of the subparts within the data storage device are associated with the addresses. A first subpart at a first location within the data storage device is indicated by a first address. A first trap subpart at a first trap location is indicated by a first trap address. The first trap address differs from the first address by only a single bit. The first trap subpart indicates the processing core to execute a first trap sub-routine to either jump to the first address or jump back to itself.

Boot of a PCIe EP coupled to a RC by a PCIe bus comprises setting, by the PCIe EP, a program counter of a CPU of the PCIe EP to an address indicative of an address of memory of the RC which stores the boot software to execute. A memory transaction to read, by the PCIe EP via the PCIe bus, a portion of the boot software stored in the address of the memory of the RC which store the boot software is performed followed by receiving by the CPU the portion which is read from the memory of the RC via the PCIe bus and PCIe controller of the EP. The portion is stored by the CPU in an instruction cache of the CPU and the CPU of the PCIe EP executes an instruction of the portion of the boot software that is received.

The application discloses a cache data prefetching method and device, equipment and storage medium, and relates to the technical field of computers, which comprises the following steps: when the accumulation table receives a data access request initiated by a CPU, if the accumulation table has a target table item that needs to be removed, it is judged whether the number of target effective bits in the candidate bit vector corresponding to the target table item is greater than a preset threshold; if yes, it is judged whether the mode table has a target bit vector corresponding to the candidate bit vector; if not, it is judged whether the mode table has a target idle table item; if not, it is judged whether the program counter corresponding to the candidate bit vector and the training counter both satisfy a first target saturation condition; if not, it is judged whether the program counter corresponding to the candidate bit vector and the access offset corresponding to the access missing counter both satisfy a second target saturation condition; if yes, the candidate bit vector is stored in the mode table, and a cache data prefetching operation is performed based on the mode table. The accuracy and efficiency of data prefetching are improved.

This invention discloses a block memory and FPGA system based on a pipelined state machine, comprising: a program counter, a workload estimator, a pipelined register set, and a block memory. During the instruction fetch phase, the program counter indicates the address of the next instruction. The instruction is fetched from the block memory according to the indicated address, stored in the pipelined register set, and the program counter is updated. During the decoding phase, the pipelined register set parses the fetched instruction into a decoded stream. Based on the workload estimator in the pipelined state machine, the load intensity in the decoded stream is predicted. Based on the predicted load intensity, the occupancy of the decoded stream is predicted. Combined with a dynamic pipeline balancing mechanism, the pipeline depth is adjusted, and control signals are generated and stored in the pipelined registers. During the execution phase, the pipelined register set performs corresponding read and write operations on the block memory according to the control signals. This invention improves the real-time performance and throughput of the block memory.

The application relates to the technical field of artificial intelligence, and particularly discloses an automatic software development system based on artificial intelligence, which collects program counter jump information and call stack snapshots in historical debugging session records, identifies cross-semantic boundary jump positions in a program execution process, extracts an execution entry slice in combination with a source code structure, further fuses semantic migration information and code structure information to generate a natural language annotation text, converts the natural language annotation text into an annotation sentence line according to an annotation syntax of a target programming language, and inserts the annotation sentence line above a semantic entry point, and determines whether to write back the source code through code semantic consistency verification, so that automatic annotation generation and backwriting facing a real debugging process are realized.

This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for handling large amounts of data, including an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes m-row radix-2 arrays arranged side-by-side. k The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories. The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of varying depths. The twiddle factor storage module stores fixed constant twiddle factors and reuses them based on the number of calculation points. The address generation module uses a program counter to generate address sequences for data read / write. The control module controls the execution of FFT calculations and can adapt to different FFT calculation requirements. This improves the utilization rate of the butterfly operation unit and the overall computational throughput of the architecture.

A method includes: acquiring a hook point and a virtual program counter by analyzing a virtual machine of a script engine; acquiring a branch virtual machine instruction by analyzing an instruction set architecture; and providing an analysis function to the script engine based on the acquired virtual program counter and the acquired branch virtual machine instruction, wherein the analysis function is provided by applying a hook to the acquired hook point and wherein the hook includes processing of, in response to an occurrence of an exception, changing a pointing destination of a virtual stack pointer to a return destination of a function immediately before a part where the exception has occurred.

This invention provides a parallel execution method for a graphics processing unit, comprising providing multiple threads, enabling a first program counter, and having the first program counter run a first program on the multiple threads. When a fork instruction is received, a second program counter is enabled, and if a first activity mask of the fork instruction is set to a pass mask and a second activity mask is set to a failure mask, the first program counter activates a first group of threads corresponding to the pass mask. When the first group of threads is blocked, the second program counter activates a second group of threads corresponding to the failure mask. When the second group of threads is blocked, the first program counter activates the first group of threads. When a merge instruction is received, the second program counter is disabled, and the first program counter activates the multiple threads.

The application relates to the technical field of chip control, in particular to a data recording method and device, a computer device, a storage medium and a program product; the method is applied to a computer device, the computer device communicates with a chip with a hardware breakpoint function; the method comprises the following steps: obtaining a running state of the chip in the process of running each instruction of a target module of the chip; instruction addresses corresponding to each instruction of the target module are configured as read-write breakpoints; in the case that the running state is a stop state, a source address stored in a program counter is read, running data is read, and a target instruction is read from the source address; the chip is controlled to execute a next instruction, the target instruction, the source address and the running data are taken as access-related information of the target instruction, and the access-related information is recorded to construct access sequence information of the target module to a register. The scheme can reduce the cost of data recording.

The application provides a low-power embedded system-level chip and a power consumption control method, relates to the technical field of chips and corresponding control methods, and comprises a main execution domain, a normal open managed domain, an execution folding engine, an execution token storage array, a conditional managed engine, a selective unfolding engine and a resource reattachment control network. When an application task runs to a preset folding boundary, the execution folding engine extracts a minimum active state set of the task, recovers a program counter, an event source identifier, a condition threshold, a deadline and a target resource identifier, generates an execution token and writes the execution token into the execution token storage array in the normal open managed domain. The application converts the existing form of the application task in the waiting stage from a processor complete thread context into an execution token object, restores a three-stage control chain through execution folding, conditional management and directional unfolding, reduces the main execution domain to maintain power consumption, reduces the number of invalid wake-up times, and shortens the response time from the waiting state to the effective execution state.

The application provides a visual gateway debugging system and method based on a Hongmeng operating system, and relates to the technical field of Internet of Things (IoT) debugging. The system comprises the following steps: constructing a domain name forest structure based on DNS, TLS and HTTP traffic and identifying device identity; generating a debugging activation instruction and transmitting a cross-device command through WebSocket and DSoftBus; collecting a program counter, a stack and a variable state with microsecond-level precision; constructing a state quadruple graph and performing compression processing; migrating a breakpoint context among multiple devices and reconstructing an execution environment; graphically presenting a state graph, a variable trajectory and a call stack, and supporting path playback and debugging control linkage. The application realizes a full-process closed loop from device identification to debugging control and from state modeling to path playback, improves debugging efficiency, automation level and system visualization capability, and is suitable for debugging and abnormal diagnosis scenarios of distributed intelligent terminals.