79 results about "Trace buffer" patented technology

In-circuit emulation (ICE) and software debug facilities are included in a processor via a debug interface that interfaces a target processor to a host system. The debug interface includes a trace controller that monitors signals produced by the target processor to detect specified conditions and produce a trace record of the specified conditions including a notification of the conditions are selected information relating to the conditions. The trace controller formats a trace information record and stores the trace information record in a trace buffer in a plurality of trace data storage elements. The trace data storage elements have a format that includes a trace code (TCODE) field indicative of a type of trace information and a trace data (TDATA) field indicative of a type of trace information data.

A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.

A method and system within a data processing system are disclosed for directly accessing code during a process by taking a trace by way of using an interruption. According to the present invention, the processor is programmed to generate a trace interrupt after each branch, or at the end of each basic block from the current process. This allows generation of exactly the same number of interruptions as would be produced by an instrumentation approach but without having to know where the basic blocks are in advance. By programming the performance monitor feature to count instructions, the exact size of each basic block is known. At each interrupt, the address of the beginning of the next basic block is saved which is the address where the interruption came from. Tracing information for the previous basic block including its address and its size (the current value of a counter) is created. If the current process is a process to be traced, the tracing information is stored in a trace buffer, the counter is reset to zero returning back to the process from the interrupt.

A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.

An electronic circuit includes a first processor (100) operable to perform processing operations, a first trace buffer (230) coupled to the first processor (100), a first triggering circuit (210) coupled to the first processor (100), the first triggering circuit (210) operable to detect a specified sequence of particular processing operations in the first processor (100); a second processor (101), a second trace buffer (231) coupled to the second processor (101), a second triggering circuit (211) coupled to the second processor (101), the second triggering circuit (211) operable to detect at least one other processing operation in the second processor (101); and a cross trace circuit (330) having a trace output and having inputs coupled to the first triggering circuit (210) and to the second triggering circuit (211), the cross trace circuit (330) configurably operable to respond to a sequence including both a detection of the sequence of particular processing operations of the first processor (100) by the first triggering circuit (210) and a detection of the at least one other processing operation of the second processor (101) by the second triggering circuit (211), to couple at least one of the first trace buffer (230) and the second trace buffer (231) to the trace output. Various circuits, devices, telecommunications products, wireless handsets, systems and processes of operation and manufacture are disclosed.

An invention is provided for debugging a computer program. Program information is recorded in a trace buffer. The program information generally includes write accesses from the computer program and the execution path of the computer program. In addition, a memory image snapshot of at least a portion of memory being utilized by the computer program is captured. Simulated re-execution of the computer program then occurs by adjusting the state of the memory image snapshot based on the program information. Further, debugging logic can be inserted into a simulated re-execution at particular points in the computer program. In particular, the debugging logic does not change the trace buffer or the memory image snapshot, and as such, do not alter the captured sequence events being debugged.

Checking the consistency of a lock step process while debugging a microcontroller code is in progress. A method provides a production microcontroller to execute an instruction code and provides the result of the instruction code to an ICE. The ICE, independent from the production microcontroller and simultaneously, executes the same instruction code and produces a result. The ICE compares the result of its computation and the result received from the production microcontroller. The ICE issues a “lock step error” when the result of the comparison is a mismatch. A trace buffer residing in the host device provides the location of the line of code causing the mismatch. After identifying the line of code causing the mismatch the user debugs the erroneous line of code. The debugging process resumes on the next line of code in the microcontroller code under test.

One embodiment relates to a computer-implemented method of generating an executable program which includes inserting predicated calls to trace routines during compilation of the source code. Each predicated call comprises a function call that is conditional upon a value stored in a predicate register. The object code generated from compiling said source code is subsequently linked with object code which includes the trace routines. Another embodiment relates to a computer-implemented method of executing a deployed computer program with low-level tracing using compiler-inserted predicated tracing calls. A tracing mode is enabled by setting one or more predicate register bits in a microprocessor. Predicated calls to trace routines insert trace data into at least one trace buffer. Upon a system crash, a core file including said trace data is written out. Other embodiments, aspects and features are also disclosed.

A system, method, and product in a logically partitioned data processing system are disclosed for preserving trace data after a partition crash. The logically partitioned data processing system includes multiple, different processors. An error is encountered in one of the processors. Data associated with the error is stored in a trace buffer. Contents of the trace buffer are stored prior to the data being overwritten.

A system provides mechanisms and techniques to retrieve trace data from a trace buffer residing in a data storage system. The software program operating on a processor within the data storage system operates in trace mode to produce trace data in the trace buffer upon occurrence of trace events. An event trace routine operates in response to a system call to access the trace buffer and return either a current value of a trace buffer pointer or the current trace buffer pointer as well as trace data read from the trace buffer beginning at a location and in an amount as specified in the system call to the event trace routine. The trace capture process can operate either within the data storage system or preferably on a remote host computer system to access trace data in the trace buffer in the data storage system by using the event trace routine. The trace capture process can periodically query the event trace routine with a frequency determined by an adaptive timing algorithm in order to detect the addition of trace data to the trace buffer. Upon detecting such a condition, the trace capture process can use the event trace routine to retrieve the trace data from the trace buffer. The trace capture process can also detect if trace data is written beyond the end of the trace buffer and can perform the proper sequence of trace data access operations using the event trace routine in order to provide continuous remote access to all trace data produced in the trace buffer.

A method and system for the management of tracing data of interest in a data processing system comprises identifying the location and length of one or more such units of interest as each unit is stored in main memory during execution of the program and recording a logical assignment of each unit of interest to a slot in a wrap around trace buffer. Copying of the units of interest to the trace buffer is deferred unless one or more predefined events occur. Such events may include an attempt to overwrite the data which has been logically assigned or a request for information stored in the trace buffer. The recorded assignments are discarded whenever it is calculated that the capacity of the trace buffer would be exceeded resulting in the corresponding units never needing to be copied to the trace buffer.

Method, apparatus, and systems for implementing flexible credit exchange within high performance fabrics. Available buffer space in a receive buffer on a receive-side of a link is managed and tracked at the transmit-side of the link using credits. Peer link interfaces coupled via a link are provided with receive buffer configuration information that specifies how the receive buffer space in each peer is partitioned and space allocated for each buffer, including a plurality of virtual lane (VL) buffers. Credits are used for tracking buffer space consumption and in credits are returned from the receive-side indicating freed buffer space. The peer link interfaces exchange credit organization information to inform the other peer of how much space each credit represents. In connection with data transfer over the link, the transmit-side de-allocates credits based on an amount of buffer space to be consumed in applicable buffers in the receive buffer. Upon space being freed in the receive buffer, the receive-side returns credit ACKnowledgements (ACKs) identifying a VL for which space has been freed.

A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.

Methods and apparatus to diagnose software including diagnostic gathering instructions are disclosed. The software is diagnosed by storing diagnostic information to a plurality of individual trace buffers responsive to the diagnostic gathering instructions, consolidating the diagnostic information from the plurality of individual trace buffers to a consolidated trace buffer, and presenting at least a portion of the consolidated diagnostic information.

A DMA controller comprises an arbitration unit for arbitrating among a plurality of channels so as to select a DMA request from among a plurality of DMA requests accepted by way of the plurality of channels according to priorities assigned to the plurality of channels in advance, and a trace buffer for storing trace data associated with the DMA request selected by the arbitration unit. The DMA controller can also include a write control unit for enabling or disabling writing of the trace data associated with the DMA request selected by the arbitration unit in the trace buffer.

A method for easily tracing the execution of an application in a computer system having a plurality of computing nodes interconnected by high speed data links is disclosed. While executing the application on one or more of the computing nodes, trace data is collected into a separate temporary trace buffer coupled to each computing node. A trace transfer request event may be generated after collecting a portion of the trace data. The trace data is recorded on a designated recording and analysis computing node by transferring the trace data from each trace buffer to a recording buffer in the designated recording node in response to the transfer request by performing memory mapped write transfers initiated by each computing node that has collected trace data. The address of the recording buffer is memory mapped into an address space of each computing node that has collected trace data.